Lines Matching refs:HDA_DSP_HDA_BAR

40 	snd_sof_dsp_update_bits(sdev, HDA_DSP_HDA_BAR, SOF_HDA_GCTL,  in hda_dsp_ctrl_link_reset()
46 gctl = snd_sof_dsp_read(sdev, HDA_DSP_HDA_BAR, SOF_HDA_GCTL); in hda_dsp_ctrl_link_reset()
76 offset = snd_sof_dsp_read(sdev, HDA_DSP_HDA_BAR, SOF_HDA_LLCH); in hda_dsp_ctrl_get_caps()
82 cap = snd_sof_dsp_read(sdev, HDA_DSP_HDA_BAR, offset); in hda_dsp_ctrl_get_caps()
175 snd_sof_dsp_update_bits(sdev, HDA_DSP_HDA_BAR, HDA_VS_INTEL_EM2, in hda_dsp_ctrl_clock_power_gating()
201 gctl = snd_sof_dsp_read(sdev, HDA_DSP_HDA_BAR, SOF_HDA_GCTL); in hda_dsp_ctrl_init_chip()
203 snd_sof_dsp_write(sdev, HDA_DSP_HDA_BAR, in hda_dsp_ctrl_init_chip()
228 snd_sof_dsp_write(sdev, HDA_DSP_HDA_BAR, in hda_dsp_ctrl_init_chip()
234 snd_sof_dsp_write(sdev, HDA_DSP_HDA_BAR, SOF_HDA_WAKESTS, in hda_dsp_ctrl_init_chip()
240 snd_sof_dsp_write(sdev, HDA_DSP_HDA_BAR, SOF_HDA_INTSTS, in hda_dsp_ctrl_init_chip()
246 snd_sof_dsp_update_bits(sdev, HDA_DSP_HDA_BAR, SOF_HDA_INTCTL, in hda_dsp_ctrl_init_chip()
252 snd_sof_dsp_write(sdev, HDA_DSP_HDA_BAR, SOF_HDA_ADSP_DPLBASE, in hda_dsp_ctrl_init_chip()
254 snd_sof_dsp_write(sdev, HDA_DSP_HDA_BAR, SOF_HDA_ADSP_DPUBASE, in hda_dsp_ctrl_init_chip()
283 snd_sof_dsp_update_bits(sdev, HDA_DSP_HDA_BAR, in hda_dsp_ctrl_stop_chip()
291 snd_sof_dsp_update_bits(sdev, HDA_DSP_HDA_BAR, SOF_HDA_INTCTL, in hda_dsp_ctrl_stop_chip()
295 snd_sof_dsp_update_bits(sdev, HDA_DSP_HDA_BAR, SOF_HDA_INTCTL, in hda_dsp_ctrl_stop_chip()
302 snd_sof_dsp_write(sdev, HDA_DSP_HDA_BAR, in hda_dsp_ctrl_stop_chip()
308 snd_sof_dsp_write(sdev, HDA_DSP_HDA_BAR, SOF_HDA_WAKESTS, in hda_dsp_ctrl_stop_chip()
314 snd_sof_dsp_write(sdev, HDA_DSP_HDA_BAR, SOF_HDA_INTSTS, in hda_dsp_ctrl_stop_chip()
321 snd_sof_dsp_write(sdev, HDA_DSP_HDA_BAR, in hda_dsp_ctrl_stop_chip()
323 snd_sof_dsp_write(sdev, HDA_DSP_HDA_BAR, in hda_dsp_ctrl_stop_chip()