Lines Matching defs:sdev
30 int hda_dsp_ctrl_link_reset(struct snd_sof_dev *sdev, bool reset)
40 snd_sof_dsp_update_bits(sdev, HDA_DSP_HDA_BAR, SOF_HDA_GCTL,
46 gctl = snd_sof_dsp_read(sdev, HDA_DSP_HDA_BAR, SOF_HDA_GCTL);
53 dev_err(sdev->dev, "error: failed to %s HDA controller gctl 0x%x\n",
58 int hda_dsp_ctrl_get_caps(struct snd_sof_dev *sdev)
60 struct hdac_bus *bus = sof_to_bus(sdev);
69 ret = hda_dsp_ctrl_link_reset(sdev, true);
72 ret = hda_dsp_ctrl_link_reset(sdev, false);
76 offset = snd_sof_dsp_read(sdev, HDA_DSP_HDA_BAR, SOF_HDA_LLCH);
79 dev_dbg(sdev->dev, "checking for capabilities at offset 0x%x\n",
82 cap = snd_sof_dsp_read(sdev, HDA_DSP_HDA_BAR, offset);
93 dev_dbg(sdev->dev, "found DSP capability at 0x%x\n",
96 sdev->bar[HDA_DSP_PP_BAR] = bus->ppcap;
99 dev_dbg(sdev->dev, "found SPIB capability at 0x%x\n",
102 sdev->bar[HDA_DSP_SPIB_BAR] = bus->spbcap;
105 dev_dbg(sdev->dev, "found DRSM capability at 0x%x\n",
108 sdev->bar[HDA_DSP_DRSM_BAR] = bus->drsmcap;
111 dev_dbg(sdev->dev, "found GTS capability at 0x%x\n",
116 dev_dbg(sdev->dev, "found ML capability at 0x%x\n",
121 dev_dbg(sdev->dev, "found capability %d at 0x%x\n",
133 void hda_dsp_ctrl_ppcap_enable(struct snd_sof_dev *sdev, bool enable)
137 snd_sof_dsp_update_bits(sdev, HDA_DSP_PP_BAR, SOF_HDA_REG_PP_PPCTL,
142 void hda_dsp_ctrl_ppcap_int_enable(struct snd_sof_dev *sdev, bool enable)
146 snd_sof_dsp_update_bits(sdev, HDA_DSP_PP_BAR, SOF_HDA_REG_PP_PPCTL,
151 void hda_dsp_ctrl_misc_clock_gating(struct snd_sof_dev *sdev, bool enable)
155 snd_sof_pci_update_bits(sdev, PCI_CGCTL, PCI_CGCTL_MISCBDCGE_MASK, val);
163 int hda_dsp_ctrl_clock_power_gating(struct snd_sof_dev *sdev, bool enable)
165 struct sof_intel_hda_dev *hda = sdev->pdata->hw_pdata;
170 snd_sof_pci_update_bits(sdev, PCI_CGCTL, PCI_CGCTL_ADSPDCGE, val);
175 snd_sof_dsp_update_bits(sdev, HDA_DSP_HDA_BAR, HDA_VS_INTEL_EM2,
180 snd_sof_pci_update_bits(sdev, PCI_PGCTL, PCI_PGCTL_ADSPPGD, val);
186 int hda_dsp_ctrl_init_chip(struct snd_sof_dev *sdev, bool detect_codec)
188 struct hdac_bus *bus = sof_to_bus(sdev);
196 hda_codec_set_codec_wakeup(sdev, true);
198 hda_dsp_ctrl_misc_clock_gating(sdev, false);
201 gctl = snd_sof_dsp_read(sdev, HDA_DSP_HDA_BAR, SOF_HDA_GCTL);
203 snd_sof_dsp_write(sdev, HDA_DSP_HDA_BAR,
207 ret = hda_dsp_ctrl_link_reset(sdev, true);
209 dev_err(sdev->dev, "error: failed to reset HDA controller\n");
216 ret = hda_dsp_ctrl_link_reset(sdev, false);
218 dev_err(sdev->dev, "error: failed to exit HDA controller reset\n");
227 hda_codec_detect_mask(sdev);
232 snd_sof_dsp_write(sdev, HDA_DSP_HDA_BAR,
238 snd_sof_dsp_write(sdev, HDA_DSP_HDA_BAR, SOF_HDA_WAKESTS,
241 hda_codec_rirb_status_clear(sdev);
244 snd_sof_dsp_write(sdev, HDA_DSP_HDA_BAR, SOF_HDA_INTSTS,
247 hda_codec_init_cmd_io(sdev);
250 snd_sof_dsp_update_bits(sdev, HDA_DSP_HDA_BAR, SOF_HDA_INTCTL,
256 snd_sof_dsp_write(sdev, HDA_DSP_HDA_BAR, SOF_HDA_ADSP_DPLBASE,
258 snd_sof_dsp_write(sdev, HDA_DSP_HDA_BAR, SOF_HDA_ADSP_DPUBASE,
267 hda_dsp_ctrl_misc_clock_gating(sdev, true);
269 hda_codec_set_codec_wakeup(sdev, false);
275 void hda_dsp_ctrl_stop_chip(struct snd_sof_dev *sdev)
277 struct hdac_bus *bus = sof_to_bus(sdev);
287 snd_sof_dsp_update_bits(sdev, HDA_DSP_HDA_BAR,
295 snd_sof_dsp_update_bits(sdev, HDA_DSP_HDA_BAR, SOF_HDA_INTCTL,
299 snd_sof_dsp_update_bits(sdev, HDA_DSP_HDA_BAR, SOF_HDA_INTCTL,
306 snd_sof_dsp_write(sdev, HDA_DSP_HDA_BAR,
312 snd_sof_dsp_write(sdev, HDA_DSP_HDA_BAR, SOF_HDA_WAKESTS,
315 hda_codec_rirb_status_clear(sdev);
318 snd_sof_dsp_write(sdev, HDA_DSP_HDA_BAR, SOF_HDA_INTSTS,
321 hda_codec_stop_cmd_io(sdev);
325 snd_sof_dsp_write(sdev, HDA_DSP_HDA_BAR,
327 snd_sof_dsp_write(sdev, HDA_DSP_HDA_BAR,