Lines Matching +full:0 +full:x800000
19 #define RESET_VECTOR_VADDR 0x596f8000
22 #define IMX8M_DAP_DEBUG 0x28800000
24 #define IMX8M_DAP_PWRCTL (0x4000 + 0x3020)
28 #define FSL_SIP_HIFI_XRDC 0xc200000e
29 #define SYSCTRL0 0x8
53 return 0;
65 if (ret < 0) {
71 IMX_SC_C_OFS_AUDIO, 0x80);
72 if (ret < 0) {
78 IMX_SC_C_OFS_PERIPH, 0x5A);
79 if (ret < 0) {
86 IMX_SC_C_OFS_IRQ, 0x51);
87 if (ret < 0) {
95 return 0;
103 IMX_SC_C_OFS_SEL, 0);
104 if (ret < 0) {
112 return 0;
124 if (ret < 0)
130 return 0;
155 return 0;
188 return 0;
195 /* Controls the HiFi4 DSP Reset: 1 in reset, 0 out of reset */
196 regmap_update_bits(regmap, SYSCTRL0, RESET_BIT, 0);
198 /* Reset HiFi4 DSP Debug logic: 1 debug reset, 0 out of reset*/
199 regmap_update_bits(regmap, SYSCTRL0, DEBUG_LOGIC_BIT, 0);
201 /* Stall HIFI4 DSP Execution: 1 stall, 0 run */
202 regmap_update_bits(regmap, SYSCTRL0, EXECUTE_BIT, 0);
204 return 0;
214 /* HiFi4 Platform Clock Enable: 1 enabled, 0 disabled */
217 /* HiFi4 PBCLK clock enable: 1 enabled, 0 disabled */
220 /* HiFi4 Clock Enable: 1 enabled, 0 disabled */
227 /* Stall HIFI4 DSP Execution: 1 stall, 0 not stall */
231 arm_smccc_smc(FSL_SIP_HIFI_XRDC, 0, 0, 0, 0, 0, 0, 0, &smc_res);
250 return 0;
265 IMX_SOF_DAI_DRV_ENTRY("micfil", 0, 0, 1, 8),
290 return 0;
338 .boot_mbox_offset = 0x800000,
339 .window_offset = 0x800000,
350 .boot_mbox_offset = 0x800000,
351 .window_offset = 0x800000,
362 .boot_mbox_offset = 0x800000,
363 .window_offset = 0x800000,
374 .boot_mbox_offset = 0x800000,
375 .window_offset = 0x800000,