Lines Matching +full:clkout +full:- +full:clock
1 // SPDX-License-Identifier: GPL-2.0
3 // Helper routines for R-Car sound ADG.
6 #include <linux/clk-provider.h>
16 #define CLKOUT 0 macro
34 struct clk *clkout[CLKOUTMAX]; member
50 (i < adg->clkin_size) && \
51 ((pos) = adg->clkin[i]); \
55 (i < adg->clkout_size) && \
56 ((pos) = adg->clkout[i]); \
58 #define rsnd_priv_to_adg(priv) ((struct rsnd_adg *)(priv)->adg)
72 [CLKOUT] = "audio_clkout",
85 for (i = 3; i >= 0; i--) { in rsnd_adg_calculate_brgx()
88 return (u32)((i << 8) | ((div / ratio) - 1)); in rsnd_adg_calculate_brgx()
138 adg->clkin_rate[CLKA], /* 0000: CLKA */ in __rsnd_adg_get_timesel_ratio()
139 adg->clkin_rate[CLKB], /* 0001: CLKB */ in __rsnd_adg_get_timesel_ratio()
140 adg->clkin_rate[CLKC], /* 0010: CLKC */ in __rsnd_adg_get_timesel_ratio()
141 adg->brg_rate[ADG_HZ_441], /* 0011: BRGA */ in __rsnd_adg_get_timesel_ratio()
142 adg->brg_rate[ADG_HZ_48], /* 0100: BRGB */ in __rsnd_adg_get_timesel_ratio()
157 diff = abs(target_rate - sel_rate[sel] / div); in __rsnd_adg_get_timesel_ratio()
179 dev_err(dev, "no Input clock\n"); in __rsnd_adg_get_timesel_ratio()
208 if (runtime->rate != in_rate) { in rsnd_adg_get_timesel_ratio()
211 } else if (runtime->rate != out_rate) { in rsnd_adg_get_timesel_ratio()
323 * find suitable clock from in rsnd_adg_clk_query()
327 if (rate == adg->clkin_rate[i]) in rsnd_adg_clk_query()
331 * find divided clock from BRGA/BRGB in rsnd_adg_clk_query()
333 if (rate == adg->brg_rate[ADG_HZ_441]) in rsnd_adg_clk_query()
336 if (rate == adg->brg_rate[ADG_HZ_48]) in rsnd_adg_clk_query()
339 return -EIO; in rsnd_adg_clk_query()
367 rsnd_mod_bset(adg_mod, BRGCKR, 0x80770000, adg->ckr | ckr); in rsnd_adg_ssi_clk_try_start()
369 dev_dbg(dev, "CLKOUT is based on BRG%c (= %dHz)\n", in rsnd_adg_ssi_clk_try_start()
371 (ckr) ? adg->brg_rate[ADG_HZ_48] : in rsnd_adg_ssi_clk_try_start()
372 adg->brg_rate[ADG_HZ_441]); in rsnd_adg_ssi_clk_try_start()
385 rsnd_mod_bset(adg_mod, BRGCKR, 0x80770000, adg->ckr); in rsnd_adg_clk_control()
386 rsnd_mod_write(adg_mod, BRRA, adg->brga); in rsnd_adg_clk_control()
387 rsnd_mod_write(adg_mod, BRRB, adg->brgb); in rsnd_adg_clk_control()
399 adg->clkin_rate[i] = clk_get_rate(clk); in rsnd_adg_clk_control()
424 struct rsnd_adg *adg = priv->adg; in rsnd_adg_null_clk_get()
426 if (!adg->null_clk) { in rsnd_adg_null_clk_get()
429 adg->null_clk = rsnd_adg_create_null_clk(priv, name, NULL); in rsnd_adg_null_clk_get()
432 return adg->null_clk; in rsnd_adg_null_clk_get()
437 struct rsnd_adg *adg = priv->adg; in rsnd_adg_null_clk_clean()
439 if (adg->null_clk) in rsnd_adg_null_clk_clean()
440 clk_unregister_fixed_rate(adg->null_clk); in rsnd_adg_null_clk_clean()
445 struct rsnd_adg *adg = priv->adg; in rsnd_adg_get_clkin()
467 adg->clkin[i] = clk; in rsnd_adg_get_clkin()
470 adg->clkin_size = clkin_size; in rsnd_adg_get_clkin()
475 dev_err(dev, "adg clock IN get failed\n"); in rsnd_adg_get_clkin()
479 return -EIO; in rsnd_adg_get_clkin()
484 struct rsnd_adg *adg = priv->adg; in rsnd_adg_unregister_clkout()
494 struct rsnd_adg *adg = priv->adg; in rsnd_adg_get_clkout()
497 struct device_node *np = dev->of_node; in rsnd_adg_get_clkout()
523 prop = of_find_property(np, "clock-frequency", NULL); in rsnd_adg_get_clkout()
527 req_size = prop->length / sizeof(u32); in rsnd_adg_get_clkout()
529 dev_err(dev, "too many clock-frequency\n"); in rsnd_adg_get_clkout()
530 return -EINVAL; in rsnd_adg_get_clkout()
533 of_property_read_u32_array(np, "clock-frequency", req_rate, req_size); in rsnd_adg_get_clkout()
547 * SSI itself can divide parent clock by 1/1 - 1/16 in rsnd_adg_get_clkout()
556 * clk_i (internal clock) can't create accurate rate, it will be approximate rate. in rsnd_adg_get_clkout()
562 * - Minimum division of BRRA/BRRB in rsnd_adg_get_clkout()
563 * - rsnd_ssi_clk_query() in rsnd_adg_get_clkout()
570 * clock-frequency = <22579200 24576000>; in rsnd_adg_get_clkout()
585 if (!adg->brg_rate[ADG_HZ_441] && req_Hz[ADG_HZ_441] && (0 == rate % 44100)) { in rsnd_adg_get_clkout()
590 adg->brg_rate[ADG_HZ_441] = rate / div; in rsnd_adg_get_clkout()
604 if (!adg->brg_rate[ADG_HZ_48] && req_Hz[ADG_HZ_48] && (0 == rate % 48000)) { in rsnd_adg_get_clkout()
609 adg->brg_rate[ADG_HZ_48] = rate / div; in rsnd_adg_get_clkout()
619 if (!(adg->brg_rate[ADG_HZ_48] && req_Hz[ADG_HZ_48]) && in rsnd_adg_get_clkout()
620 !(adg->brg_rate[ADG_HZ_441] && req_Hz[ADG_HZ_441])) in rsnd_adg_get_clkout()
636 of_property_read_u32(np, "#clock-cells", &count); in rsnd_adg_get_clkout()
638 * for clkout in rsnd_adg_get_clkout()
641 clk = clk_register_fixed_rate(dev, clkout_name[CLKOUT], in rsnd_adg_get_clkout()
646 adg->clkout[CLKOUT] = clk; in rsnd_adg_get_clkout()
647 adg->clkout_size = 1; in rsnd_adg_get_clkout()
661 adg->clkout[i] = clk; in rsnd_adg_get_clkout()
663 adg->onecell.clks = adg->clkout; in rsnd_adg_get_clkout()
664 adg->onecell.clk_num = clkout_size; in rsnd_adg_get_clkout()
665 adg->clkout_size = clkout_size; in rsnd_adg_get_clkout()
667 &adg->onecell); in rsnd_adg_get_clkout()
671 adg->ckr = ckr; in rsnd_adg_get_clkout()
672 adg->brga = brga; in rsnd_adg_get_clkout()
673 adg->brgb = brgb; in rsnd_adg_get_clkout()
678 dev_err(dev, "adg clock OUT get failed\n"); in rsnd_adg_get_clkout()
682 return -EIO; in rsnd_adg_get_clkout()
711 dbg_msg(dev, m, "%-18s : %pa : %ld\n", in rsnd_adg_clk_dbg_info()
715 adg->ckr, adg->brga, adg->brgb); in rsnd_adg_clk_dbg_info()
716 dbg_msg(dev, m, "BRGA (for 44100 base) = %d\n", adg->brg_rate[ADG_HZ_441]); in rsnd_adg_clk_dbg_info()
717 dbg_msg(dev, m, "BRGB (for 48000 base) = %d\n", adg->brg_rate[ADG_HZ_48]); in rsnd_adg_clk_dbg_info()
720 * Actual CLKOUT will be exchanged in rsnd_adg_ssi_clk_try_start() in rsnd_adg_clk_dbg_info()
724 dbg_msg(dev, m, "%-18s : %pa : %ld\n", in rsnd_adg_clk_dbg_info()
739 return -ENOMEM; in rsnd_adg_probe()
741 ret = rsnd_mod_init(priv, &adg->mod, &adg_ops, in rsnd_adg_probe()
746 priv->adg = adg; in rsnd_adg_probe()
765 struct device_node *np = dev->of_node; in rsnd_adg_remove()