29 #define TRCM_TXRX 0
103  * Returns success (0) or negative errno.
107 	int ret = 0;  in i2s_tdm_prepare_enable_mclk()
116 	return 0;  in i2s_tdm_prepare_enable_mclk()
133 	return 0;  in i2s_tdm_runtime_suspend()
156 	return 0;  in i2s_tdm_runtime_resume()
173  * when clk_trcm > 0.
214 	unsigned int xfer_mask = 0;  in rockchip_snd_xfer_clear()
215 	unsigned int xfer_val = 0;  in rockchip_snd_xfer_clear()
281 /* only used when clk_trcm > 0 */
309 		if (--i2s_tdm->refcount == 0) {  in rockchip_snd_txrxctrl()
356 	if (ret < 0 && ret != -EACCES)  in rockchip_i2s_tdm_set_fmt()
449 			tdm_val = TDM_SHIFT_CTRL(0);  in rockchip_i2s_tdm_set_fmt()
453 			tdm_val = TDM_SHIFT_CTRL(0);  in rockchip_i2s_tdm_set_fmt()
549 	unsigned int val = 0;  in rockchip_i2s_io_multiplex()
552 		return 0;  in rockchip_i2s_io_multiplex()
606 	return 0;  in rockchip_i2s_io_multiplex()
619 		return 0;  in rockchip_i2s_trcm_mode()
645 	return 0;  in rockchip_i2s_trcm_mode()
653 	unsigned int val = 0;  in rockchip_i2s_tdm_hw_params()
767 			rockchip_snd_txrxctrl(substream, dai, 0);  in rockchip_i2s_tdm_trigger()
769 			rockchip_snd_rxctrl(i2s_tdm, 0);  in rockchip_i2s_tdm_trigger()
771 			rockchip_snd_txctrl(i2s_tdm, 0);  in rockchip_i2s_tdm_trigger()
777 	return 0;  in rockchip_i2s_tdm_trigger()
789 	return 0;  in rockchip_i2s_tdm_dai_probe()
809 	return 0;  in rockchip_dai_tdm_slot()
822 	return 0;  in rockchip_i2s_tdm_set_bclk_ratio()
906 	{0x00, 0x7200000f},
907 	{0x04, 0x01c8000f},
908 	{0x08, 0x00001f1f},
909 	{0x10, 0x001f0000},
910 	{0x14, 0x01f00000},
911 	{0x30, 0x00003eff},
912 	{0x34, 0x00003eff},
913 	{0x38, 0x00000707},
934 	u32 reg = 0, val = 0, trcm = i2s_tdm->clk_trcm;  in common_soc_init()
938 		return 0;  in common_soc_init()
946 	for (i = 0; i < i2s_tdm->soc_data->config_count; i++) {  in common_soc_init()
959 	return 0;  in common_soc_init()
963 	{ 0xff060000, 0x184, PX30_I2S0_CLK_TXONLY, PX30_I2S0_CLK_RXONLY },
967 	{ 0xff7e0000, 0x190, RK1808_I2S0_CLK_TXONLY, RK1808_I2S0_CLK_RXONLY },
971 	{ 0xff300000, 0x308, RK3308_I2S0_CLK_TXONLY, RK3308_I2S0_CLK_RXONLY },
972 	{ 0xff310000, 0x308, RK3308_I2S1_CLK_TXONLY, RK3308_I2S1_CLK_RXONLY },
976 	{ 0xfe410000, 0x504, RK3568_I2S1_CLK_TXONLY, RK3568_I2S1_CLK_RXONLY },
977 	{ 0xfe410000, 0x508, RK3568_I2S1_MCLK_TX_OE, RK3568_I2S1_MCLK_RX_OE },
978 	{ 0xfe420000, 0x508, RK3568_I2S2_MCLK_OE, RK3568_I2S2_MCLK_OE },
979 	{ 0xfe430000, 0x504, RK3568_I2S3_CLK_TXONLY, RK3568_I2S3_CLK_RXONLY },
980 	{ 0xfe430000, 0x508, RK3568_I2S3_MCLK_TXONLY, RK3568_I2S3_MCLK_RXONLY },
981 	{ 0xfe430000, 0x508, RK3568_I2S3_MCLK_OE, RK3568_I2S3_MCLK_OE },
985 	{ 0xff800000, 0x10260, RV1126_I2S0_CLK_TXONLY, RV1126_I2S0_CLK_RXONLY },
989 	.softrst_offset = 0x0300,
996 	.softrst_offset = 0x0300,
1003 	.softrst_offset = 0x0400,
1004 	.grf_reg_offset = 0x0308,
1012 	.softrst_offset = 0x0400,
1019 	.softrst_offset = 0x0300,
1082 	return 0;  in rockchip_i2s_tdm_init_dai()
1097 	for (i = 0; i < num; i++) {  in rockchip_i2s_tdm_path_check()
1106 		for (j = 0; j < num; j++) {  in rockchip_i2s_tdm_path_check()
1121 	return 0;  in rockchip_i2s_tdm_path_check()
1129 	for (idx = 0; idx < num; idx++) {  in rockchip_i2s_tdm_tx_path_config()
1141 	for (idx = 0; idx < num; idx++) {  in rockchip_i2s_tdm_rx_path_config()
1165 	int num, ret = 0;  in rockchip_i2s_tdm_path_prepare()
1176 	if (num < 0) {  in rockchip_i2s_tdm_path_prepare()
1192 	if (ret < 0) {  in rockchip_i2s_tdm_path_prepare()
1200 	if (ret < 0) {  in rockchip_i2s_tdm_path_prepare()
1208 	return 0;  in rockchip_i2s_tdm_path_prepare()
1214 	return rockchip_i2s_tdm_path_prepare(i2s_tdm, np, 0);  in rockchip_i2s_tdm_tx_path_prepare()
1294 	regs = devm_platform_get_and_ioremap_resource(pdev, 0, &res);  in rockchip_i2s_tdm_probe()
1320 	if (ret < 0) {  in rockchip_i2s_tdm_probe()
1326 	if (ret < 0) {  in rockchip_i2s_tdm_probe()
1367 	ret = devm_snd_dmaengine_pcm_register(&pdev->dev, NULL, 0);  in rockchip_i2s_tdm_probe()
1373 	return 0;  in rockchip_i2s_tdm_probe()
1400 	return 0;  in rockchip_i2s_tdm_suspend()
1409 	if (ret < 0)  in rockchip_i2s_tdm_resume()