1 // SPDX-License-Identifier: GPL-2.0
3 // Helper routines for R-Car sound ADG.
6 #include <linux/clk-provider.h>
50 	     (i < adg->clkin_size) &&		\
51 	     ((pos) = adg->clkin[i]);		\
55 	     (i < adg->clkout_size) &&		\
56 	     ((pos) = adg->clkout[i]);	\
58 #define rsnd_priv_to_adg(priv) ((struct rsnd_adg *)(priv)->adg)
85 	for (i = 3; i >= 0; i--) {  in rsnd_adg_calculate_brgx()
88 			return (u32)((i << 8) | ((div / ratio) - 1));  in rsnd_adg_calculate_brgx()
136 	unsigned int min, diff;  in __rsnd_adg_get_timesel_ratio()  local
138 		adg->clkin_rate[CLKA],	/* 0000: CLKA */  in __rsnd_adg_get_timesel_ratio()
139 		adg->clkin_rate[CLKB],	/* 0001: CLKB */  in __rsnd_adg_get_timesel_ratio()
140 		adg->clkin_rate[CLKC],	/* 0010: CLKC */  in __rsnd_adg_get_timesel_ratio()
141 		adg->brg_rate[ADG_HZ_441],	/* 0011: BRGA */  in __rsnd_adg_get_timesel_ratio()
142 		adg->brg_rate[ADG_HZ_48],	/* 0100: BRGB */  in __rsnd_adg_get_timesel_ratio()
145 	min = ~0;  in __rsnd_adg_get_timesel_ratio()
157 			diff = abs(target_rate - sel_rate[sel] / div);  in __rsnd_adg_get_timesel_ratio()
158 			if (min > diff) {  in __rsnd_adg_get_timesel_ratio()
160 				min = diff;  in __rsnd_adg_get_timesel_ratio()
178 	if (min == ~0) {  in __rsnd_adg_get_timesel_ratio()
208 	if (runtime->rate != in_rate) {  in rsnd_adg_get_timesel_ratio()
211 	} else if (runtime->rate != out_rate) {  in rsnd_adg_get_timesel_ratio()
310 int rsnd_adg_clk_query(struct rsnd_priv *priv, unsigned int rate)  in rsnd_adg_clk_query()  argument
327 		if (rate == adg->clkin_rate[i])  in rsnd_adg_clk_query()
333 	if (rate == adg->brg_rate[ADG_HZ_441])  in rsnd_adg_clk_query()
336 	if (rate == adg->brg_rate[ADG_HZ_48])  in rsnd_adg_clk_query()
339 	return -EIO;  in rsnd_adg_clk_query()
349 int rsnd_adg_ssi_clk_try_start(struct rsnd_mod *ssi_mod, unsigned int rate)  in rsnd_adg_ssi_clk_try_start()  argument
358 	data = rsnd_adg_clk_query(priv, rate);  in rsnd_adg_ssi_clk_try_start()
364 	if (0 == (rate % 8000))  in rsnd_adg_ssi_clk_try_start()
367 	rsnd_mod_bset(adg_mod, BRGCKR, 0x80770000, adg->ckr | ckr);  in rsnd_adg_ssi_clk_try_start()
371 		(ckr) ?	adg->brg_rate[ADG_HZ_48] :  in rsnd_adg_ssi_clk_try_start()
372 			adg->brg_rate[ADG_HZ_441]);  in rsnd_adg_ssi_clk_try_start()
385 		rsnd_mod_bset(adg_mod, BRGCKR, 0x80770000, adg->ckr);  in rsnd_adg_clk_control()
386 		rsnd_mod_write(adg_mod, BRRA,  adg->brga);  in rsnd_adg_clk_control()
387 		rsnd_mod_write(adg_mod, BRRB,  adg->brgb);  in rsnd_adg_clk_control()
402 			adg->clkin_rate[i] = clk_get_rate(clk);  in rsnd_adg_clk_control()
404 			if (adg->clkin_rate[i])  in rsnd_adg_clk_control()
407 			adg->clkin_rate[i] = 0;  in rsnd_adg_clk_control()
439 	struct rsnd_adg *adg = priv->adg;  in rsnd_adg_null_clk_get()
441 	if (!adg->null_clk) {  in rsnd_adg_null_clk_get()
444 		adg->null_clk = rsnd_adg_create_null_clk(priv, name, NULL);  in rsnd_adg_null_clk_get()
447 	return adg->null_clk;  in rsnd_adg_null_clk_get()
452 	struct rsnd_adg *adg = priv->adg;  in rsnd_adg_null_clk_clean()
454 	if (adg->null_clk)  in rsnd_adg_null_clk_clean()
455 		clk_unregister_fixed_rate(adg->null_clk);  in rsnd_adg_null_clk_clean()
460 	struct rsnd_adg *adg = priv->adg;  in rsnd_adg_get_clkin()
482 		adg->clkin[i] = clk;  in rsnd_adg_get_clkin()
485 	adg->clkin_size = clkin_size;  in rsnd_adg_get_clkin()
494 	return -EIO;  in rsnd_adg_get_clkin()
499 	struct rsnd_adg *adg = priv->adg;  in rsnd_adg_unregister_clkout()
509 	struct rsnd_adg *adg = priv->adg;  in rsnd_adg_get_clkout()
512 	struct device_node *np = dev->of_node;  in rsnd_adg_get_clkout()
536 	 * this means all clkout0/1/2/3 will be same rate  in rsnd_adg_get_clkout()
538 	prop = of_find_property(np, "clock-frequency", NULL);  in rsnd_adg_get_clkout()
542 	req_size = prop->length / sizeof(u32);  in rsnd_adg_get_clkout()
544 		dev_err(dev, "too many clock-frequency\n");  in rsnd_adg_get_clkout()
545 		return -EINVAL;  in rsnd_adg_get_clkout()
548 	of_property_read_u32_array(np, "clock-frequency", req_rate, req_size);  in rsnd_adg_get_clkout()
562 	 * SSI itself can divide parent clock by 1/1 - 1/16  in rsnd_adg_get_clkout()
571 	 * clk_i (internal clock) can't create accurate rate, it will be approximate rate.  in rsnd_adg_get_clkout()
575 	 * clk_i needs x2 of required maximum rate.  in rsnd_adg_get_clkout()
577 	 *	- Minimum division of BRRA/BRRB  in rsnd_adg_get_clkout()
578 	 *	- rsnd_ssi_clk_query()  in rsnd_adg_get_clkout()
580 	 * Sample Settings for TDM 8ch, 32bit width  in rsnd_adg_get_clkout()
582 	 *	8(ch) x 32(bit) x 44100(Hz) x 2<Note> = 22579200  in rsnd_adg_get_clkout()
583 	 *	8(ch) x 32(bit) x 48000(Hz) x 2<Note> = 24576000  in rsnd_adg_get_clkout()
585 	 *	clock-frequency = <22579200 24576000>;  in rsnd_adg_get_clkout()
588 		u32 rate, div;  in rsnd_adg_get_clkout()  local
590 		rate = clk_get_rate(clk);  in rsnd_adg_get_clkout()
592 		if (0 == rate) /* not used */  in rsnd_adg_get_clkout()
599 			rate = (clk_get_rate(clk) / req_Hz[ADG_HZ_441]) * req_Hz[ADG_HZ_441];  in rsnd_adg_get_clkout()
600 		if (!adg->brg_rate[ADG_HZ_441] && req_Hz[ADG_HZ_441] && (0 == rate % 44100)) {  in rsnd_adg_get_clkout()
601 			div = rate / req_Hz[ADG_HZ_441];  in rsnd_adg_get_clkout()
605 				adg->brg_rate[ADG_HZ_441] = rate / div;  in rsnd_adg_get_clkout()
618 			rate = (clk_get_rate(clk) / req_Hz[ADG_HZ_48]) * req_Hz[ADG_HZ_48];  in rsnd_adg_get_clkout()
619 		if (!adg->brg_rate[ADG_HZ_48] && req_Hz[ADG_HZ_48] && (0 == rate % 48000)) {  in rsnd_adg_get_clkout()
620 			div = rate / req_Hz[ADG_HZ_48];  in rsnd_adg_get_clkout()
624 				adg->brg_rate[ADG_HZ_48] = rate / div;  in rsnd_adg_get_clkout()
634 	if (!(adg->brg_rate[ADG_HZ_48]  && req_Hz[ADG_HZ_48]) &&  in rsnd_adg_get_clkout()
635 	    !(adg->brg_rate[ADG_HZ_441] && req_Hz[ADG_HZ_441]))  in rsnd_adg_get_clkout()
639 		dev_info(dev, "It uses CLK_I as approximate rate");  in rsnd_adg_get_clkout()
648 	 * this means all clkout0/1/2/3 will be * same rate  in rsnd_adg_get_clkout()
651 	of_property_read_u32(np, "#clock-cells", &count);  in rsnd_adg_get_clkout()
661 		adg->clkout[CLKOUT] = clk;  in rsnd_adg_get_clkout()
662 		adg->clkout_size = 1;  in rsnd_adg_get_clkout()
676 			adg->clkout[i] = clk;  in rsnd_adg_get_clkout()
678 		adg->onecell.clks	= adg->clkout;  in rsnd_adg_get_clkout()
679 		adg->onecell.clk_num	= clkout_size;  in rsnd_adg_get_clkout()
680 		adg->clkout_size	= clkout_size;  in rsnd_adg_get_clkout()
682 				    &adg->onecell);  in rsnd_adg_get_clkout()
686 	adg->ckr = ckr;  in rsnd_adg_get_clkout()
687 	adg->brga = brga;  in rsnd_adg_get_clkout()
688 	adg->brgb = brgb;  in rsnd_adg_get_clkout()
697 	return -EIO;  in rsnd_adg_get_clkout()
726 		dbg_msg(dev, m, "%-18s : %pa : %ld\n",  in rsnd_adg_clk_dbg_info()
730 		adg->ckr, adg->brga, adg->brgb);  in rsnd_adg_clk_dbg_info()
731 	dbg_msg(dev, m, "BRGA (for 44100 base) = %d\n", adg->brg_rate[ADG_HZ_441]);  in rsnd_adg_clk_dbg_info()
732 	dbg_msg(dev, m, "BRGB (for 48000 base) = %d\n", adg->brg_rate[ADG_HZ_48]);  in rsnd_adg_clk_dbg_info()
739 		dbg_msg(dev, m, "%-18s : %pa : %ld\n",  in rsnd_adg_clk_dbg_info()
754 		return -ENOMEM;  in rsnd_adg_probe()
756 	ret = rsnd_mod_init(priv, &adg->mod, &adg_ops,  in rsnd_adg_probe()
761 	priv->adg = adg;  in rsnd_adg_probe()
783 	struct device_node *np = dev->of_node;  in rsnd_adg_remove()