11 #define LPAIF_I2SCTL_REG_ADDR(v, addr, port) \  argument
12 	(v->i2sctrl_reg_base + (addr) + v->i2sctrl_reg_stride * (port))
14 #define LPAIF_I2SCTL_REG(v, port)	LPAIF_I2SCTL_REG_ADDR(v, 0x0, (port))  argument
17 #define LPAIF_I2SCTL_LOOPBACK_ENABLE	1
20 #define LPAIF_I2SCTL_SPKEN_ENABLE	1
23 #define LPAIF_I2SCTL_MODE_SD0		1
46 #define LPAIF_I2SCTL_SPKMONO_MONO	1
49 #define LPAIF_I2SCTL_MICEN_ENABLE	1
54 #define LPAIF_I2SCTL_MICMONO_MONO	1
57 #define LPAIF_I2SCTL_WSSRC_EXTERNAL	1
60 #define LPAIF_I2SCTL_BITWIDTH_24	1
68 #define LPAIF_IRQ_REG_ADDR(v, addr, port) \  argument
69 	(v->irq_reg_base + (addr) + v->irq_reg_stride * (port))
73 #define LPAIF_IRQEN_REG(v, port)	LPAIF_IRQ_REG_ADDR(v, 0x0, (port))  argument
74 #define LPAIF_IRQSTAT_REG(v, port)	LPAIF_IRQ_REG_ADDR(v, 0x4, (port))  argument
75 #define LPAIF_IRQCLEAR_REG(v, port)	LPAIF_IRQ_REG_ADDR(v, 0xC, (port))  argument
78 #define LPAIF_RXTX_IRQ_REG_ADDR(v, addr, port) \  argument
79 		(v->rxtx_irq_reg_base + (addr) + v->rxtx_irq_reg_stride * (port))
81 #define LPAIF_RXTX_IRQEN_REG(v, port) LPAIF_RXTX_IRQ_REG_ADDR(v, 0x0, port)  argument
82 #define LPAIF_RXTX_IRQSTAT_REG(v, port) LPAIF_RXTX_IRQ_REG_ADDR(v, 0x4, port)  argument
83 #define LPAIF_RXTX_IRQCLEAR_REG(v, port) LPAIF_RXTX_IRQ_REG_ADDR(v, 0xC, port)  argument
86 #define LPAIF_VA_IRQ_REG_ADDR(v, addr, port) \  argument
87 		(v->va_irq_reg_base + (addr) + v->va_irq_reg_stride * (port))
89 #define LPAIF_VA_IRQEN_REG(v, port) LPAIF_VA_IRQ_REG_ADDR(v, 0x0, port)  argument
90 #define LPAIF_VA_IRQSTAT_REG(v, port) LPAIF_VA_IRQ_REG_ADDR(v, 0x4, port)  argument
91 #define LPAIF_VA_IRQCLEAR_REG(v, port) LPAIF_VA_IRQ_REG_ADDR(v, 0xC, port)  argument
93 #define LPASS_HDMITX_APP_IRQ_REG_ADDR(v, addr)  \  argument
94 	((v->hdmi_irq_reg_base) + (addr))
96 #define LPASS_HDMITX_APP_IRQEN_REG(v)			LPASS_HDMITX_APP_IRQ_REG_ADDR(v, 0x4)  argument
97 #define LPASS_HDMITX_APP_IRQSTAT_REG(v)			LPASS_HDMITX_APP_IRQ_REG_ADDR(v, 0x8)  argument
98 #define LPASS_HDMITX_APP_IRQCLEAR_REG(v)		LPASS_HDMITX_APP_IRQ_REG_ADDR(v, 0xC)  argument
102 #define LPAIF_IRQ_PER(chan)		(1 << (LPAIF_IRQ_BITSTRIDE * (chan)))
107 #define LPAIF_IRQ_HDMI_REQ_ON_PRELOAD(chan)	(1 << (14 + chan))
108 #define LPAIF_IRQ_HDMI_SDEEP_AUD_DIS(chan)	(1 << (24 + chan))
112 #define LPAIF_HDMI_RDMA_REG_ADDR(v, addr, chan) \  argument
113 	(v->hdmi_rdma_reg_base + (addr) + v->hdmi_rdma_reg_stride * (chan))
117 #define LPAIF_HDMI_RDMACTL_REG(v, chan)		LPAIF_HDMI_RDMA_REG_ADDR(v, 0x00, (chan))  argument
118 #define LPAIF_HDMI_RDMABASE_REG(v, chan)	LPAIF_HDMI_RDMA_REG_ADDR(v, 0x04, (chan))  argument
119 #define	LPAIF_HDMI_RDMABUFF_REG(v, chan)	LPAIF_HDMI_RDMA_REG_ADDR(v, 0x08, (chan))  argument
120 #define LPAIF_HDMI_RDMACURR_REG(v, chan)	LPAIF_HDMI_RDMA_REG_ADDR(v, 0x0C, (chan))  argument
121 #define	LPAIF_HDMI_RDMAPER_REG(v, chan)		LPAIF_HDMI_RDMA_REG_ADDR(v, 0x10, (chan))  argument
122 #define	LPAIF_HDMI_RDMAPERCNT_REG(v, chan)	LPAIF_HDMI_RDMA_REG_ADDR(v, 0x14, (chan))  argument
124 #define LPAIF_RDMA_REG_ADDR(v, addr, chan) \  argument
125 	(v->rdma_reg_base + (addr) + v->rdma_reg_stride * (chan))
129 #define LPAIF_RDMACTL_REG(v, chan)	LPAIF_RDMA_REG_ADDR(v, 0x00, (chan))  argument
130 #define LPAIF_RDMABASE_REG(v, chan)	LPAIF_RDMA_REG_ADDR(v, 0x04, (chan))  argument
131 #define	LPAIF_RDMABUFF_REG(v, chan)	LPAIF_RDMA_REG_ADDR(v, 0x08, (chan))  argument
132 #define LPAIF_RDMACURR_REG(v, chan)	LPAIF_RDMA_REG_ADDR(v, 0x0C, (chan))  argument
133 #define	LPAIF_RDMAPER_REG(v, chan)	LPAIF_RDMA_REG_ADDR(v, 0x10, (chan))  argument
134 #define	LPAIF_RDMAPERCNT_REG(v, chan)	LPAIF_RDMA_REG_ADDR(v, 0x14, (chan))  argument
136 #define LPAIF_WRDMA_REG_ADDR(v, addr, chan) \  argument
137 	(v->wrdma_reg_base + (addr) + \
138 	 v->wrdma_reg_stride * (chan - v->wrdma_channel_start))
140 #define LPAIF_WRDMACTL_REG(v, chan)	LPAIF_WRDMA_REG_ADDR(v, 0x00, (chan))  argument
141 #define LPAIF_WRDMABASE_REG(v, chan)	LPAIF_WRDMA_REG_ADDR(v, 0x04, (chan))  argument
142 #define	LPAIF_WRDMABUFF_REG(v, chan)	LPAIF_WRDMA_REG_ADDR(v, 0x08, (chan))  argument
143 #define LPAIF_WRDMACURR_REG(v, chan)	LPAIF_WRDMA_REG_ADDR(v, 0x0C, (chan))  argument
144 #define	LPAIF_WRDMAPER_REG(v, chan)	LPAIF_WRDMA_REG_ADDR(v, 0x10, (chan))  argument
145 #define	LPAIF_WRDMAPERCNT_REG(v, chan)	LPAIF_WRDMA_REG_ADDR(v, 0x14, (chan))  argument
147 #define LPAIF_INTFDMA_REG(v, chan, reg, dai_id)  \  argument
149 		LPAIF_HDMI_RDMA##reg##_REG(v, chan) : \
150 		 LPAIF_RDMA##reg##_REG(v, chan))
152 #define __LPAIF_DMA_REG(v, chan, dir, reg, dai_id)  \  argument
154 		(LPAIF_INTFDMA_REG(v, chan, reg, dai_id)) : \
155 		LPAIF_WRDMA##reg##_REG(v, chan))
157 #define LPAIF_DMACTL_REG(v, chan, dir, dai_id) \  argument
159 	__LPAIF_CDC_DMA_REG(v, chan, dir, CTL, dai_id) : \
160 	__LPAIF_DMA_REG(v, chan, dir, CTL, dai_id))
161 #define LPAIF_DMABASE_REG(v, chan, dir, dai_id) \  argument
163 	__LPAIF_CDC_DMA_REG(v, chan, dir, BASE, dai_id) : \
164 	__LPAIF_DMA_REG(v, chan, dir, BASE, dai_id))
165 #define LPAIF_DMABUFF_REG(v, chan, dir, dai_id) \  argument
167 	__LPAIF_CDC_DMA_REG(v, chan, dir, BUFF, dai_id) : \
168 	__LPAIF_DMA_REG(v, chan, dir, BUFF, dai_id))
169 #define LPAIF_DMACURR_REG(v, chan, dir, dai_id) \  argument
171 	__LPAIF_CDC_DMA_REG(v, chan, dir, CURR, dai_id) : \
172 	__LPAIF_DMA_REG(v, chan, dir, CURR, dai_id))
173 #define LPAIF_DMAPER_REG(v, chan, dir, dai_id)  \  argument
175 	__LPAIF_CDC_DMA_REG(v, chan, dir, PER, dai_id) : \
176 	__LPAIF_DMA_REG(v, chan, dir, PER, dai_id))
177 #define LPAIF_DMAPERCNT_REG(v, chan, dir, dai_id) \  argument
179 	__LPAIF_CDC_DMA_REG(v, chan, dir, PERCNT, dai_id) : \
180 	__LPAIF_DMA_REG(v, chan, dir, PERCNT, dai_id))
182 #define LPAIF_CDC_RDMA_REG_ADDR(v, addr, chan, dai_id) \  argument
184 	(v->rxtx_rdma_reg_base + (addr) + v->rxtx_rdma_reg_stride * (chan)) : \
185 	(v->va_rdma_reg_base + (addr) + v->va_rdma_reg_stride * (chan)))
187 #define LPAIF_CDC_RXTX_RDMACTL_REG(v, chan, dai_id) \  argument
188 		LPAIF_CDC_RDMA_REG_ADDR(v, 0x00, (chan), dai_id)
189 #define LPAIF_CDC_RXTX_RDMABASE_REG(v, chan, dai_id) \  argument
190 		LPAIF_CDC_RDMA_REG_ADDR(v, 0x04, (chan), dai_id)
191 #define LPAIF_CDC_RXTX_RDMABUFF_REG(v, chan, dai_id) \  argument
192 		LPAIF_CDC_RDMA_REG_ADDR(v, 0x08, (chan), dai_id)
193 #define LPAIF_CDC_RXTX_RDMACURR_REG(v, chan, dai_id) \  argument
194 		LPAIF_CDC_RDMA_REG_ADDR(v, 0x0C, (chan), dai_id)
195 #define LPAIF_CDC_RXTX_RDMAPER_REG(v, chan, dai_id) \  argument
196 		LPAIF_CDC_RDMA_REG_ADDR(v, 0x10, (chan), dai_id)
197 #define LPAIF_CDC_RXTX_RDMA_INTF_REG(v, chan, dai_id) \  argument
198 	LPAIF_CDC_RDMA_REG_ADDR(v, 0x50, (chan), dai_id)
200 #define LPAIF_CDC_VA_RDMACTL_REG(v, chan, dai_id) LPAIF_CDC_RDMA_REG_ADDR(v, 0x00, (chan), dai_id)  argument
201 #define LPAIF_CDC_VA_RDMABASE_REG(v, chan, dai_id) LPAIF_CDC_RDMA_REG_ADDR(v, 0x04, (chan), dai_id)  argument
202 #define LPAIF_CDC_VA_RDMABUFF_REG(v, chan, dai_id) LPAIF_CDC_RDMA_REG_ADDR(v, 0x08, (chan), dai_id)  argument
203 #define LPAIF_CDC_VA_RDMACURR_REG(v, chan, dai_id) LPAIF_CDC_RDMA_REG_ADDR(v, 0x0C, (chan), dai_id)  argument
204 #define LPAIF_CDC_VA_RDMAPER_REG(v, chan, dai_id) LPAIF_CDC_RDMA_REG_ADDR(v, 0x10, (chan), dai_id)  argument
205 #define LPAIF_CDC_VA_RDMA_INTF_REG(v, chan, dai_id) \  argument
206 	LPAIF_CDC_RDMA_REG_ADDR(v, 0x50, (chan), dai_id)
208 #define LPAIF_CDC_WRDMA_REG_ADDR(v, addr, chan, dai_id) \  argument
210 	(v->rxtx_wrdma_reg_base + (addr) + \
211 		v->rxtx_wrdma_reg_stride * (chan - v->rxtx_wrdma_channel_start)) : \
212 	(v->va_wrdma_reg_base + (addr) + \
213 		v->va_wrdma_reg_stride * (chan - v->va_wrdma_channel_start)))
215 #define LPAIF_CDC_RXTX_WRDMACTL_REG(v, chan, dai_id) \  argument
216 	LPAIF_CDC_WRDMA_REG_ADDR(v, 0x00, (chan), dai_id)
217 #define LPAIF_CDC_RXTX_WRDMABASE_REG(v, chan, dai_id) \  argument
218 	LPAIF_CDC_WRDMA_REG_ADDR(v, 0x04, (chan), dai_id)
219 #define LPAIF_CDC_RXTX_WRDMABUFF_REG(v, chan, dai_id) \  argument
220 	LPAIF_CDC_WRDMA_REG_ADDR(v, 0x08, (chan), dai_id)
221 #define LPAIF_CDC_RXTX_WRDMACURR_REG(v, chan, dai_id) \  argument
222 	LPAIF_CDC_WRDMA_REG_ADDR(v, 0x0C, (chan), dai_id)
223 #define LPAIF_CDC_RXTX_WRDMAPER_REG(v, chan, dai_id) \  argument
224 	LPAIF_CDC_WRDMA_REG_ADDR(v, 0x10, (chan), dai_id)
225 #define LPAIF_CDC_RXTX_WRDMA_INTF_REG(v, chan, dai_id) \  argument
226 	LPAIF_CDC_WRDMA_REG_ADDR(v, 0x50, (chan), dai_id)
228 #define LPAIF_CDC_VA_WRDMACTL_REG(v, chan, dai_id) \  argument
229 	LPAIF_CDC_WRDMA_REG_ADDR(v, 0x00, (chan), dai_id)
230 #define LPAIF_CDC_VA_WRDMABASE_REG(v, chan, dai_id) \  argument
231 	LPAIF_CDC_WRDMA_REG_ADDR(v, 0x04, (chan), dai_id)
232 #define LPAIF_CDC_VA_WRDMABUFF_REG(v, chan, dai_id) \  argument
233 	LPAIF_CDC_WRDMA_REG_ADDR(v, 0x08, (chan), dai_id)
234 #define LPAIF_CDC_VA_WRDMACURR_REG(v, chan, dai_id) \  argument
235 	LPAIF_CDC_WRDMA_REG_ADDR(v, 0x0C, (chan), dai_id)
236 #define LPAIF_CDC_VA_WRDMAPER_REG(v, chan, dai_id) \  argument
237 	LPAIF_CDC_WRDMA_REG_ADDR(v, 0x10, (chan), dai_id)
238 #define LPAIF_CDC_VA_WRDMA_INTF_REG(v, chan, dai_id) \  argument
239 	LPAIF_CDC_WRDMA_REG_ADDR(v, 0x50, (chan), dai_id)
241 #define __LPAIF_CDC_RDDMA_REG(v, chan, dir, reg, dai_id) \  argument
242 		(is_rxtx_cdc_dma_port(dai_id) ? LPAIF_CDC_RXTX_RDMA##reg##_REG(v, chan, dai_id) : \
243 			LPAIF_CDC_VA_RDMA##reg##_REG(v, chan, dai_id))
245 #define __LPAIF_CDC_WRDMA_REG(v, chan, dir, reg, dai_id) \  argument
246 		(is_rxtx_cdc_dma_port(dai_id) ? LPAIF_CDC_RXTX_WRDMA##reg##_REG(v, chan, dai_id) : \
247 			LPAIF_CDC_VA_WRDMA##reg##_REG(v, chan, dai_id))
249 #define __LPAIF_CDC_DMA_REG(v, chan, dir, reg, dai_id) \  argument
251 			__LPAIF_CDC_RDDMA_REG(v, chan, dir, reg, dai_id) : \
252 			__LPAIF_CDC_WRDMA_REG(v, chan, dir, reg, dai_id))
254 #define LPAIF_CDC_INTF_REG(v, chan, dir, dai_id) \  argument
256 		LPAIF_CDC_RDMA_INTF_REG(v, chan, dai_id) : \
257 		LPAIF_CDC_WRDMA_INTF_REG(v, chan, dai_id))
259 #define LPAIF_INTF_REG(v, chan, dir, dai_id) \  argument
261 		LPAIF_CDC_INTF_REG(v, chan, dir, dai_id) : \
262 		LPAIF_DMACTL_REG(v, chan, dir, dai_id))
265 #define LPAIF_DMACTL_BURSTEN_INCR4	1
268 #define LPAIF_DMACTL_WPSCNT_TWO		1
281 #define LPAIF_DMACTL_FIFOWM_2		1
314 #define LPAIF_DMACTL_ENABLE_ON		1
317 #define LPAIF_DMACTL_DYNCLK_ON		1