Lines Matching +full:sc7180 +full:- +full:lpass +full:- +full:cpu
1 // SPDX-License-Identifier: GPL-2.0-only
5 * lpass-hdmi.c -- ALSA SoC HDMI-CPU DAI driver for QTi LPASS HDMI
14 #include <sound/soc-dai.h>
15 #include <dt-bindings/sound/sc7180-lpass.h>
16 #include "lpass-lpaif-reg.h"
17 #include "lpass.h"
33 struct lpass_dp_metadata_ctl *meta_ctl = drvdata->meta_ctl;
34 struct lpass_sstream_ctl *sstream_ctl = drvdata->sstream_ctl;
39 dev_err(dai->dev, "%s invalid bit width given : %d\n",
52 dev_err(dai->dev, "%s invalid bit width given : %d\n",
54 return -EINVAL;
68 dev_err(dai->dev, "%s invalid bit width given : %d\n",
70 return -EINVAL;
77 ret = regmap_field_write(drvdata->tx_ctl->soft_reset, LPASS_TX_CTL_RESET);
81 ret = regmap_field_write(drvdata->tx_ctl->soft_reset, LPASS_TX_CTL_CLEAR);
85 ret = regmap_field_write(drvdata->hdmitx_legacy_en, LPASS_HDMITX_LEGACY_DISABLE);
89 ret = regmap_field_write(drvdata->hdmitx_parity_calc_en, HDMITX_PARITY_CALC_EN);
93 ret = regmap_field_write(drvdata->vbit_ctl->replace_vbit, REPLACE_VBIT);
97 ret = regmap_field_write(drvdata->vbit_ctl->vbit_stream, LINEAR_PCM_DATA);
101 ret = regmap_field_write(drvdata->hdmitx_ch_msb[0], ch_sts_buf1);
105 ret = regmap_field_write(drvdata->hdmitx_ch_lsb[0], ch_sts_buf0);
109 ret = regmap_field_write(drvdata->hdmi_tx_dmactl[0]->use_hw_chs, HW_MODE);
113 ret = regmap_field_write(drvdata->hdmi_tx_dmactl[0]->hw_chs_sel, SW_MODE);
117 ret = regmap_field_write(drvdata->hdmi_tx_dmactl[0]->use_hw_usr, HW_MODE);
121 ret = regmap_field_write(drvdata->hdmi_tx_dmactl[0]->hw_usr_sel, SW_MODE);
125 ret = regmap_field_write(meta_ctl->mute, LPASS_MUTE_ENABLE);
129 ret = regmap_field_write(meta_ctl->as_sdp_cc, channels - 1);
133 ret = regmap_field_write(meta_ctl->as_sdp_ct, LPASS_META_DEFAULT_VAL);
137 ret = regmap_field_write(meta_ctl->aif_db4, LPASS_META_DEFAULT_VAL);
141 ret = regmap_field_write(meta_ctl->frequency, sampling_freq);
145 ret = regmap_field_write(meta_ctl->mst_index, LPASS_META_DEFAULT_VAL);
149 ret = regmap_field_write(meta_ctl->dptx_index, LPASS_META_DEFAULT_VAL);
153 ret = regmap_field_write(sstream_ctl->sstream_en, LPASS_SSTREAM_DISABLE);
157 ret = regmap_field_write(sstream_ctl->dma_sel, ch);
161 ret = regmap_field_write(sstream_ctl->auto_bbit_en, LPASS_SSTREAM_DEFAULT_ENABLE);
165 ret = regmap_field_write(sstream_ctl->layout, LPASS_SSTREAM_DEFAULT_DISABLE);
169 ret = regmap_field_write(sstream_ctl->layout_sp, LPASS_LAYOUT_SP_DEFAULT);
173 ret = regmap_field_write(sstream_ctl->dp_audio, LPASS_SSTREAM_DEFAULT_ENABLE);
177 ret = regmap_field_write(sstream_ctl->set_sp_on_en, LPASS_SSTREAM_DEFAULT_ENABLE);
181 ret = regmap_field_write(sstream_ctl->dp_sp_b_hw_en, LPASS_SSTREAM_DEFAULT_ENABLE);
185 ret = regmap_field_write(sstream_ctl->dp_staffing_en, LPASS_SSTREAM_DEFAULT_ENABLE);
196 ret = regmap_field_write(drvdata->sstream_ctl->sstream_en, LPASS_SSTREAM_ENABLE);
200 ret = regmap_field_write(drvdata->meta_ctl->mute, LPASS_MUTE_DISABLE);
209 struct lpass_dp_metadata_ctl *meta_ctl = drvdata->meta_ctl;
210 struct lpass_sstream_ctl *sstream_ctl = drvdata->sstream_ctl;
211 int ret = -EINVAL;
217 ret = regmap_field_write(sstream_ctl->sstream_en, LPASS_SSTREAM_ENABLE);
221 ret = regmap_field_write(meta_ctl->mute, LPASS_MUTE_DISABLE);
229 ret = regmap_field_write(sstream_ctl->sstream_en, LPASS_SSTREAM_DISABLE);
233 ret = regmap_field_write(meta_ctl->mute, LPASS_MUTE_ENABLE);
237 ret = regmap_field_write(sstream_ctl->dp_audio, 0);
253 MODULE_DESCRIPTION("QTi LPASS HDMI Driver");