1 // SPDX-License-Identifier: (GPL-2.0 OR MIT)
17 #include <sound/soc-dai.h>
19 #include "axg-fifo.h"
38 	struct axg_fifo *fifo = snd_soc_dai_get_drvdata(dai);  in g12a_frddr_dai_prepare()  local
41 	regmap_update_bits(fifo->map, FIFO_CTRL1,  in g12a_frddr_dai_prepare()
43 	regmap_update_bits(fifo->map, FIFO_CTRL1,  in g12a_frddr_dai_prepare()
45 	regmap_update_bits(fifo->map, FIFO_CTRL1,  in g12a_frddr_dai_prepare()
55 	struct axg_fifo *fifo = snd_soc_dai_get_drvdata(dai);  in axg_frddr_dai_hw_params()  local
56 	unsigned int period, depth, val;  in axg_frddr_dai_hw_params()  local
60 	/* Trim the FIFO depth if the period is small to improve latency */  in axg_frddr_dai_hw_params()
61 	depth = min(period, fifo->depth);  in axg_frddr_dai_hw_params()
62 	val = (depth / AXG_FIFO_BURST) - 1;  in axg_frddr_dai_hw_params()
63 	regmap_update_bits(fifo->map, FIFO_CTRL1, CTRL1_FRDDR_DEPTH,  in axg_frddr_dai_hw_params()
72 	struct axg_fifo *fifo = snd_soc_dai_get_drvdata(dai);  in axg_frddr_dai_startup()  local
75 	/* Enable pclk to access registers and clock the fifo ip */  in axg_frddr_dai_startup()
76 	ret = clk_prepare_enable(fifo->pclk);  in axg_frddr_dai_startup()
81 	regmap_update_bits(fifo->map, FIFO_CTRL0, CTRL0_FRDDR_PP_MODE, 0);  in axg_frddr_dai_startup()
89 	struct axg_fifo *fifo = snd_soc_dai_get_drvdata(dai);  in axg_frddr_dai_shutdown()  local
91 	clk_disable_unprepare(fifo->pclk);  in axg_frddr_dai_shutdown()
377 		.compatible = "amlogic,axg-frddr",
380 		.compatible = "amlogic,g12a-frddr",
383 		.compatible = "amlogic,sm1-frddr",
392 		.name = "axg-frddr",
398 MODULE_DESCRIPTION("Amlogic AXG/G12A playback fifo driver");