1 // SPDX-License-Identifier: GPL-2.0
7 #include <linux/clk.h>
10 #include <sound/soc-dai.h>
41 	/* Always operate in split (classic interleaved) mode */  in aiu_encoder_i2s_setup_desc()
58 		return -EINVAL;  in aiu_encoder_i2s_setup_desc()
68 		return -EINVAL;  in aiu_encoder_i2s_setup_desc()
94 		dev_err(component->dev, "Unsupported i2s divider: %u\n", bs);  in aiu_encoder_i2s_set_legacy_div()
95 		return -EINVAL;  in aiu_encoder_i2s_set_legacy_div()
117 	 * In most configuration, the i2s divider is 'mclk / blck'.  in aiu_encoder_i2s_set_more_div()
118 	 * However, in 16 bits - 8ch mode, this factor needs to be  in aiu_encoder_i2s_set_more_div()
124 			dev_err(component->dev,  in aiu_encoder_i2s_set_more_div()
125 				"Cannot increase i2s divider by 50%%\n");  in aiu_encoder_i2s_set_more_div()
126 			return -EINVAL;  in aiu_encoder_i2s_set_more_div()
131 	/* Use CLK_MORE for mclk to bclk divider */  in aiu_encoder_i2s_set_more_div()
139 						 bs - 1));  in aiu_encoder_i2s_set_more_div()
153 	fs = DIV_ROUND_CLOSEST(clk_get_rate(aiu->i2s.clks[MCLK].clk), srate);  in aiu_encoder_i2s_set_clocks()
156 		return -EINVAL;  in aiu_encoder_i2s_set_clocks()
167 						 64 - 1));  in aiu_encoder_i2s_set_clocks()
171 	if (aiu->platform->has_clk_ctrl_more_i2s_div)  in aiu_encoder_i2s_set_clocks()
191 	struct snd_soc_component *component = dai->component;  in aiu_encoder_i2s_hw_params()
199 		dev_err(dai->dev, "setting i2s desc failed\n");  in aiu_encoder_i2s_hw_params()
205 		dev_err(dai->dev, "setting i2s clocks failed\n");  in aiu_encoder_i2s_hw_params()
217 	struct snd_soc_component *component = dai->component;  in aiu_encoder_i2s_hw_free()
226 	struct snd_soc_component *component = dai->component;  in aiu_encoder_i2s_set_fmt()
233 		return -EINVAL;  in aiu_encoder_i2s_set_fmt()
241 	 * so an inversion of the bitclock is required in normal mode  in aiu_encoder_i2s_set_fmt()
258 		return -EINVAL;  in aiu_encoder_i2s_set_fmt()
274 	struct aiu *aiu = snd_soc_component_get_drvdata(dai->component);  in aiu_encoder_i2s_set_sysclk()
278 		return -EINVAL;  in aiu_encoder_i2s_set_sysclk()
283 	ret = clk_set_rate(aiu->i2s.clks[MCLK].clk, freq);  in aiu_encoder_i2s_set_sysclk()
285 		dev_err(dai->dev, "Failed to set sysclk to %uHz", freq);  in aiu_encoder_i2s_set_sysclk()
300 	struct aiu *aiu = snd_soc_component_get_drvdata(dai->component);  in aiu_encoder_i2s_startup()
304 	ret = snd_pcm_hw_constraint_list(substream->runtime, 0,  in aiu_encoder_i2s_startup()
308 		dev_err(dai->dev, "adding channels constraints failed\n");  in aiu_encoder_i2s_startup()
312 	ret = clk_bulk_prepare_enable(aiu->i2s.clk_num, aiu->i2s.clks);  in aiu_encoder_i2s_startup()
314 		dev_err(dai->dev, "failed to enable i2s clocks\n");  in aiu_encoder_i2s_startup()
322 	struct aiu *aiu = snd_soc_component_get_drvdata(dai->component);  in aiu_encoder_i2s_shutdown()
324 	clk_bulk_disable_unprepare(aiu->i2s.clk_num, aiu->i2s.clks);  in aiu_encoder_i2s_shutdown()