Lines Matching defs:afe

10 #include "mt8365-afe-clk.h"
11 #include "mt8365-afe-common.h"
13 #include "../common/mtk-base-afe.h"
34 int mt8365_afe_init_audio_clk(struct mtk_base_afe *afe)
37 	struct mt8365_afe_private *afe_priv = afe->platform_priv;
40 		afe_priv->clocks[i] = devm_clk_get(afe->dev, aud_clks[i]);
42 			dev_err(afe->dev, "%s devm_clk_get %s fail\n",
50 void mt8365_afe_disable_clk(struct mtk_base_afe *afe, struct clk *clk)
55 int mt8365_afe_set_clk_rate(struct mtk_base_afe *afe, struct clk *clk,
63 			dev_err(afe->dev, "Failed to set rate\n");
70 int mt8365_afe_set_clk_parent(struct mtk_base_afe *afe, struct clk *clk,
78 			dev_err(afe->dev, "Failed to set parent\n");
191 int mt8365_afe_enable_top_cg(struct mtk_base_afe *afe, unsigned int cg_type)
193 	struct mt8365_afe_private *afe_priv = afe->platform_priv;
203 		regmap_update_bits(afe->regmap, reg, mask, val);
210 int mt8365_afe_disable_top_cg(struct mtk_base_afe *afe, unsigned int cg_type)
212 	struct mt8365_afe_private *afe_priv = afe->platform_priv;
222 		regmap_update_bits(afe->regmap, reg, mask, val);
231 int mt8365_afe_enable_main_clk(struct mtk_base_afe *afe)
233 	struct mt8365_afe_private *afe_priv = afe->platform_priv;
236 	mt8365_afe_enable_top_cg(afe, MT8365_TOP_CG_AFE);
237 	mt8365_afe_enable_afe_on(afe);
242 int mt8365_afe_disable_main_clk(struct mtk_base_afe *afe)
244 	struct mt8365_afe_private *afe_priv = afe->platform_priv;
246 	mt8365_afe_disable_afe_on(afe);
247 	mt8365_afe_disable_top_cg(afe, MT8365_TOP_CG_AFE);
248 	mt8365_afe_disable_clk(afe, afe_priv->clocks[MT8365_CLK_TOP_AUD_SEL]);
253 int mt8365_afe_emi_clk_on(struct mtk_base_afe *afe)
258 int mt8365_afe_emi_clk_off(struct mtk_base_afe *afe)
263 int mt8365_afe_enable_afe_on(struct mtk_base_afe *afe)
265 	struct mt8365_afe_private *afe_priv = afe->platform_priv;
272 		regmap_update_bits(afe->regmap, AFE_DAC_CON0, 0x1, 0x1);
279 int mt8365_afe_disable_afe_on(struct mtk_base_afe *afe)
281 	struct mt8365_afe_private *afe_priv = afe->platform_priv;
288 		regmap_update_bits(afe->regmap, AFE_DAC_CON0, 0x1, 0x0);
297 static int mt8365_afe_hd_engen_enable(struct mtk_base_afe *afe, bool apll1)
300 		regmap_update_bits(afe->regmap, AFE_HD_ENGEN_ENABLE,
303 		regmap_update_bits(afe->regmap, AFE_HD_ENGEN_ENABLE,
309 static int mt8365_afe_hd_engen_disable(struct mtk_base_afe *afe, bool apll1)
312 		regmap_update_bits(afe->regmap, AFE_HD_ENGEN_ENABLE,
315 		regmap_update_bits(afe->regmap, AFE_HD_ENGEN_ENABLE,
321 int mt8365_afe_enable_apll_tuner_cfg(struct mtk_base_afe *afe, unsigned int apll)
323 	struct mt8365_afe_private *afe_priv = afe->platform_priv;
334 		regmap_update_bits(afe->regmap, AFE_APLL_TUNER_CFG,
336 		regmap_update_bits(afe->regmap, AFE_APLL_TUNER_CFG,
339 		regmap_update_bits(afe->regmap, AFE_APLL_TUNER_CFG1,
341 		regmap_update_bits(afe->regmap, AFE_APLL_TUNER_CFG1,
349 int mt8365_afe_disable_apll_tuner_cfg(struct mtk_base_afe *afe, unsigned int apll)
351 	struct mt8365_afe_private *afe_priv = afe->platform_priv;
358 			regmap_update_bits(afe->regmap, AFE_APLL_TUNER_CFG,
361 			regmap_update_bits(afe->regmap, AFE_APLL_TUNER_CFG1,
372 int mt8365_afe_enable_apll_associated_cfg(struct mtk_base_afe *afe, unsigned int apll)
374 	struct mt8365_afe_private *afe_priv = afe->platform_priv;
378 			dev_info(afe->dev, "%s Failed to enable ENGEN1 clk\n",
382 		mt8365_afe_enable_top_cg(afe, MT8365_TOP_CG_22M);
383 		mt8365_afe_hd_engen_enable(afe, true);
384 		mt8365_afe_enable_top_cg(afe, MT8365_TOP_CG_APLL_TUNER);
385 		mt8365_afe_enable_apll_tuner_cfg(afe, MT8365_AFE_APLL1);
388 			dev_info(afe->dev, "%s Failed to enable ENGEN2 clk\n",
392 		mt8365_afe_enable_top_cg(afe, MT8365_TOP_CG_24M);
393 		mt8365_afe_hd_engen_enable(afe, false);
394 		mt8365_afe_enable_top_cg(afe, MT8365_TOP_CG_APLL2_TUNER);
395 		mt8365_afe_enable_apll_tuner_cfg(afe, MT8365_AFE_APLL2);
401 int mt8365_afe_disable_apll_associated_cfg(struct mtk_base_afe *afe, unsigned int apll)
403 	struct mt8365_afe_private *afe_priv = afe->platform_priv;
406 		mt8365_afe_disable_apll_tuner_cfg(afe, MT8365_AFE_APLL1);
407 		mt8365_afe_disable_top_cg(afe, MT8365_TOP_CG_APLL_TUNER);
408 		mt8365_afe_hd_engen_disable(afe, true);
409 		mt8365_afe_disable_top_cg(afe, MT8365_TOP_CG_22M);
412 		mt8365_afe_disable_apll_tuner_cfg(afe, MT8365_AFE_APLL2);
413 		mt8365_afe_disable_top_cg(afe, MT8365_TOP_CG_APLL2_TUNER);
414 		mt8365_afe_hd_engen_disable(afe, false);
415 		mt8365_afe_disable_top_cg(afe, MT8365_TOP_CG_24M);