56 	union config_status_reg_mrfld csr;  in intel_sst_reset_dsp_mrfld()  local
59 	csr.full = sst_shim_read64(sst_drv_ctx->shim, SST_CSR);  in intel_sst_reset_dsp_mrfld()
61 	dev_dbg(sst_drv_ctx->dev, "value:0x%llx\n", csr.full);  in intel_sst_reset_dsp_mrfld()
63 	csr.full |= 0x7;  in intel_sst_reset_dsp_mrfld()
64 	sst_shim_write64(sst_drv_ctx->shim, SST_CSR, csr.full);  in intel_sst_reset_dsp_mrfld()
65 	csr.full = sst_shim_read64(sst_drv_ctx->shim, SST_CSR);  in intel_sst_reset_dsp_mrfld()
67 	dev_dbg(sst_drv_ctx->dev, "value:0x%llx\n", csr.full);  in intel_sst_reset_dsp_mrfld()
69 	csr.full &= ~(0x1);  in intel_sst_reset_dsp_mrfld()
70 	sst_shim_write64(sst_drv_ctx->shim, SST_CSR, csr.full);  in intel_sst_reset_dsp_mrfld()
72 	csr.full = sst_shim_read64(sst_drv_ctx->shim, SST_CSR);  in intel_sst_reset_dsp_mrfld()
73 	dev_dbg(sst_drv_ctx->dev, "value:0x%llx\n", csr.full);  in intel_sst_reset_dsp_mrfld()
85 	union config_status_reg_mrfld csr;  in sst_start_mrfld()  local
88 	csr.full = sst_shim_read64(sst_drv_ctx->shim, SST_CSR);  in sst_start_mrfld()
89 	dev_dbg(sst_drv_ctx->dev, "value:0x%llx\n", csr.full);  in sst_start_mrfld()
91 	csr.full |= 0x7;  in sst_start_mrfld()
92 	sst_shim_write64(sst_drv_ctx->shim, SST_CSR, csr.full);  in sst_start_mrfld()
94 	csr.full = sst_shim_read64(sst_drv_ctx->shim, SST_CSR);  in sst_start_mrfld()
95 	dev_dbg(sst_drv_ctx->dev, "value:0x%llx\n", csr.full);  in sst_start_mrfld()
97 	csr.part.xt_snoop = 1;  in sst_start_mrfld()
98 	csr.full &= ~(0x5);  in sst_start_mrfld()
99 	sst_shim_write64(sst_drv_ctx->shim, SST_CSR, csr.full);  in sst_start_mrfld()
101 	csr.full = sst_shim_read64(sst_drv_ctx->shim, SST_CSR);  in sst_start_mrfld()
103 			csr.full);  in sst_start_mrfld()