Lines Matching refs:isr_clr
1391 u32 isr, isr_clr = 0, val, i; in irq0_isr() local
1397 isr_clr |= FSL_XCVR_IRQ_NEW_CS; in irq0_isr()
1450 isr_clr |= FSL_XCVR_IRQ_NEW_UD; in irq0_isr()
1454 isr_clr |= FSL_XCVR_IRQ_MUTE; in irq0_isr()
1458 isr_clr |= FSL_XCVR_IRQ_FIFO_UOFL_ERR; in irq0_isr()
1462 isr_clr |= FSL_XCVR_IRQ_ARC_MODE; in irq0_isr()
1466 isr_clr |= FSL_XCVR_IRQ_DMA_RD_REQ; in irq0_isr()
1470 isr_clr |= FSL_XCVR_IRQ_DMA_WR_REQ; in irq0_isr()
1474 isr_clr |= FSL_XCVR_IRQ_CMDC_STATUS_UPD; in irq0_isr()
1478 isr_clr |= FSL_XCVR_IRQ_PREAMBLE_MISMATCH; in irq0_isr()
1482 isr_clr |= FSL_XCVR_IRQ_UNEXP_PRE_REC; in irq0_isr()
1486 isr_clr |= FSL_XCVR_IRQ_M_W_PRE_MISMATCH; in irq0_isr()
1490 isr_clr |= FSL_XCVR_IRQ_B_PRE_MISMATCH; in irq0_isr()
1500 if (isr_clr) { in irq0_isr()
1501 regmap_write(regmap, FSL_XCVR_EXT_ISR_CLR, isr_clr); in irq0_isr()