Lines Matching +full:xcvr +full:- +full:setup
1 // SPDX-License-Identifier: GPL-2.0
19 #include "imx-pcm.h"
73 * HDMI2.1 spec defines 6- and 12-channels layout for one bit audio
110 struct fsl_xcvr *xcvr = snd_soc_dai_get_drvdata(dai);
111 struct soc_enum *e = (struct soc_enum *)kcontrol->private_value;
112 unsigned int *item = ucontrol->value.enumerated.item;
114 xcvr->arc_mode = snd_soc_enum_item_to_val(e, item[0]);
123 struct fsl_xcvr *xcvr = snd_soc_dai_get_drvdata(dai);
125 ucontrol->value.enumerated.item[0] = xcvr->arc_mode;
145 uinfo->type = SNDRV_CTL_ELEM_TYPE_BYTES;
146 uinfo->count = FSL_XCVR_CAPDS_SIZE;
155 struct fsl_xcvr *xcvr = snd_soc_dai_get_drvdata(dai);
157 memcpy(ucontrol->value.bytes.data, xcvr->cap_ds, FSL_XCVR_CAPDS_SIZE);
166 struct fsl_xcvr *xcvr = snd_soc_dai_get_drvdata(dai);
168 memcpy(xcvr->cap_ds, ucontrol->value.bytes.data, FSL_XCVR_CAPDS_SIZE);
185 struct snd_soc_card *card = dai->component->card;
189 lockdep_assert_held(&card->snd_card->controls_rwsem);
193 return -ENOENT;
195 enabled = ((kctl->vd[0].access & SNDRV_CTL_ELEM_ACCESS_WRITE) != 0);
200 kctl->vd[0].access |= SNDRV_CTL_ELEM_ACCESS_WRITE;
202 kctl->vd[0].access &= ~SNDRV_CTL_ELEM_ACCESS_WRITE;
204 snd_ctl_notify(card->snd_card, SNDRV_CTL_EVENT_MASK_INFO, &kctl->id);
213 struct fsl_xcvr *xcvr = snd_soc_dai_get_drvdata(dai);
214 struct soc_enum *e = (struct soc_enum *)kcontrol->private_value;
215 unsigned int *item = ucontrol->value.enumerated.item;
216 struct snd_soc_card *card = dai->component->card;
219 xcvr->mode = snd_soc_enum_item_to_val(e, item[0]);
222 (xcvr->mode == FSL_XCVR_MODE_ARC));
224 (xcvr->mode == FSL_XCVR_MODE_EARC));
226 rtd = snd_soc_get_pcm_runtime(card, card->dai_link);
227 rtd->pcm->streams[SNDRV_PCM_STREAM_PLAYBACK].substream_count =
228 (xcvr->mode == FSL_XCVR_MODE_SPDIF ? 1 : 0);
236 struct fsl_xcvr *xcvr = snd_soc_dai_get_drvdata(dai);
238 ucontrol->value.enumerated.item[0] = xcvr->mode;
247 SOC_ENUM_EXT("XCVR Mode", fsl_xcvr_mode_enum,
251 static int fsl_xcvr_ai_write(struct fsl_xcvr *xcvr, u8 reg, u32 data, bool phy)
253 struct device *dev = &xcvr->pdev->dev;
260 regmap_write(xcvr->regmap, FSL_XCVR_PHY_AI_CTRL_CLR, 0xFF);
261 regmap_write(xcvr->regmap, FSL_XCVR_PHY_AI_CTRL_SET, reg);
262 regmap_write(xcvr->regmap, FSL_XCVR_PHY_AI_WDATA, data);
263 regmap_write(xcvr->regmap, FSL_XCVR_PHY_AI_CTRL_TOG, idx);
265 ret = regmap_read_poll_timeout(xcvr->regmap, FSL_XCVR_PHY_AI_CTRL, val,
274 static int fsl_xcvr_en_phy_pll(struct fsl_xcvr *xcvr, u32 freq, bool tx)
276 struct device *dev = &xcvr->pdev->dev;
280 if (!xcvr->soc_data->use_phy)
291 return -EINVAL;
296 ret = regmap_write(xcvr->regmap, FSL_XCVR_PHY_AI_CTRL_SET,
303 switch (xcvr->soc_data->pll_ver) {
306 fsl_xcvr_ai_write(xcvr, FSL_XCVR_PLL_BANDGAP_SET,
310 fsl_xcvr_ai_write(xcvr, FSL_XCVR_PLL_CTRL0, fsl_xcvr_pll_cfg[i].mfi, 0);
312 fsl_xcvr_ai_write(xcvr, FSL_XCVR_PLL_NUM, fsl_xcvr_pll_cfg[i].mfn, 0);
314 fsl_xcvr_ai_write(xcvr, FSL_XCVR_PLL_DEN, fsl_xcvr_pll_cfg[i].mfd, 0);
316 fsl_xcvr_ai_write(xcvr, FSL_XCVR_PLL_CTRL0_SET,
320 fsl_xcvr_ai_write(xcvr, FSL_XCVR_PLL_CTRL0_CLR,
325 fsl_xcvr_ai_write(xcvr, FSL_XCVR_PLL_PDIV,
328 fsl_xcvr_ai_write(xcvr, FSL_XCVR_PLL_CTRL0_SET,
330 } else if (xcvr->mode == FSL_XCVR_MODE_EARC) { /* eARC RX */
332 fsl_xcvr_ai_write(xcvr, FSL_XCVR_PLL_PDIV,
335 fsl_xcvr_ai_write(xcvr, FSL_XCVR_PLL_CTRL0_SET,
339 fsl_xcvr_ai_write(xcvr, FSL_XCVR_PLL_PDIV,
342 fsl_xcvr_ai_write(xcvr, FSL_XCVR_PLL_CTRL0_SET,
348 fsl_xcvr_ai_write(xcvr, FSL_XCVR_GP_PLL_DIV, val, 0);
350 fsl_xcvr_ai_write(xcvr, FSL_XCVR_GP_PLL_NUMERATOR, val, 0);
351 fsl_xcvr_ai_write(xcvr, FSL_XCVR_GP_PLL_DENOMINATOR,
354 fsl_xcvr_ai_write(xcvr, FSL_XCVR_GP_PLL_CTRL, val, 0);
357 dev_err(dev, "Error for PLL version %d\n", xcvr->soc_data->pll_ver);
358 return -EINVAL;
361 if (xcvr->mode == FSL_XCVR_MODE_EARC) { /* eARC mode */
363 fsl_xcvr_ai_write(xcvr, FSL_XCVR_PHY_CTRL_SET,
367 fsl_xcvr_ai_write(xcvr, FSL_XCVR_PHY_CTRL2_SET,
370 if (xcvr->mode == FSL_XCVR_MODE_SPDIF)
372 fsl_xcvr_ai_write(xcvr, FSL_XCVR_PHY_CTRL_SET,
374 else /* PHY: CTRL_SET: ARC RX setup */
375 fsl_xcvr_ai_write(xcvr, FSL_XCVR_PHY_CTRL_SET,
378 fsl_xcvr_phy_arc_cfg[xcvr->arc_mode], 1);
387 static int fsl_xcvr_en_aud_pll(struct fsl_xcvr *xcvr, u32 freq)
389 struct device *dev = &xcvr->pdev->dev;
392 freq = xcvr->soc_data->spdif_only ? freq / 5 : freq;
393 clk_disable_unprepare(xcvr->phy_clk);
394 fsl_asoc_reparent_pll_clocks(dev, xcvr->phy_clk,
395 xcvr->pll8k_clk, xcvr->pll11k_clk, freq);
396 ret = clk_set_rate(xcvr->phy_clk, freq);
401 ret = clk_prepare_enable(xcvr->phy_clk);
407 if (!xcvr->soc_data->use_phy)
410 ret = regmap_write(xcvr->regmap, FSL_XCVR_PHY_AI_CTRL_SET,
417 if (xcvr->mode == FSL_XCVR_MODE_EARC) { /* eARC mode */
419 fsl_xcvr_ai_write(xcvr, FSL_XCVR_PHY_CTRL_SET,
423 fsl_xcvr_ai_write(xcvr, FSL_XCVR_PHY_CTRL2_SET,
427 fsl_xcvr_ai_write(xcvr, FSL_XCVR_PHY_CTRL_SET,
441 struct fsl_xcvr *xcvr = snd_soc_dai_get_drvdata(dai);
442 bool tx = substream->stream == SNDRV_PCM_STREAM_PLAYBACK;
444 u32 r = substream->runtime->rate, ch = substream->runtime->channels;
448 switch (xcvr->mode) {
450 if (xcvr->soc_data->spdif_only && tx) {
451 ret = regmap_update_bits(xcvr->regmap, FSL_XCVR_TX_DPTH_CTRL_SET,
455 dev_err(dai->dev, "Failed to set bypass fem: %d\n", ret);
462 ret = fsl_xcvr_en_aud_pll(xcvr, fout);
464 dev_err(dai->dev, "Failed to set TX freq %u: %d\n",
469 ret = regmap_write(xcvr->regmap, FSL_XCVR_TX_DPTH_CTRL_SET,
472 dev_err(dai->dev, "Failed to set TX_DPTH: %d\n", ret);
477 * set SPDIF MODE - this flag is used to gate
487 ret = regmap_write(xcvr->regmap, FSL_XCVR_RX_DPTH_CTRL_SET,
493 dev_err(dai->dev, "Failed to set RX_DPTH: %d\n", ret);
497 ret = fsl_xcvr_en_phy_pll(xcvr, FSL_XCVR_SPDIF_RX_FREQ, tx);
499 dev_err(dai->dev, "Failed to set RX freq %u: %d\n",
508 ret = regmap_write(xcvr->regmap, FSL_XCVR_RX_DPTH_CTRL_SET,
512 dev_err(dai->dev, "Failed to set RX_DPTH: %d\n", ret);
517 ret = regmap_write(xcvr->regmap, FSL_XCVR_RX_DPTH_CTRL_CLR,
521 dev_err(dai->dev, "Failed to clr TX_DPTH: %d\n", ret);
534 ret = regmap_update_bits(xcvr->regmap, FSL_XCVR_EXT_CTRL, m_ctl, v_ctl);
536 dev_err(dai->dev, "Error while setting EXT_CTRL: %d\n", ret);
547 struct snd_pcm_runtime *rt = substream->runtime;
566 struct fsl_xcvr *xcvr = snd_soc_dai_get_drvdata(dai);
567 bool tx = substream->stream == SNDRV_PCM_STREAM_PLAYBACK;
570 if (xcvr->streams & BIT(substream->stream)) {
571 dev_err(dai->dev, "%sX busy\n", tx ? "T" : "R");
572 return -EBUSY;
579 if (xcvr->soc_data->use_edma)
580 snd_pcm_hw_constraint_step(substream->runtime, 0,
582 tx ? xcvr->dma_prms_tx.maxburst :
583 xcvr->dma_prms_rx.maxburst);
585 switch (xcvr->mode) {
599 xcvr->streams |= BIT(substream->stream);
601 if (!xcvr->soc_data->spdif_only) {
602 struct snd_soc_card *card = dai->component->card;
604 /* Disable XCVR controls if there is stream started */
605 down_read(&card->snd_card->controls_rwsem);
609 up_read(&card->snd_card->controls_rwsem);
618 struct fsl_xcvr *xcvr = snd_soc_dai_get_drvdata(dai);
619 bool tx = substream->stream == SNDRV_PCM_STREAM_PLAYBACK;
623 xcvr->streams &= ~BIT(substream->stream);
625 /* Enable XCVR controls if there is no stream started */
626 if (!xcvr->streams) {
627 if (!xcvr->soc_data->spdif_only) {
628 struct snd_soc_card *card = dai->component->card;
630 down_read(&card->snd_card->controls_rwsem);
633 (xcvr->mode == FSL_XCVR_MODE_ARC));
635 (xcvr->mode == FSL_XCVR_MODE_EARC));
636 up_read(&card->snd_card->controls_rwsem);
638 ret = regmap_update_bits(xcvr->regmap, FSL_XCVR_EXT_IER0,
641 dev_err(dai->dev, "Failed to set IER0: %d\n", ret);
646 if (xcvr->mode == FSL_XCVR_MODE_SPDIF)
650 if (xcvr->mode == FSL_XCVR_MODE_EARC) {
656 ret = regmap_update_bits(xcvr->regmap, FSL_XCVR_EXT_CTRL, mask, val);
658 dev_err(dai->dev, "Err setting DPATH RESET: %d\n", ret);
666 struct fsl_xcvr *xcvr = snd_soc_dai_get_drvdata(dai);
667 bool tx = substream->stream == SNDRV_PCM_STREAM_PLAYBACK;
671 spin_lock_irqsave(&xcvr->lock, lock_flags);
678 ret = regmap_update_bits(xcvr->regmap, FSL_XCVR_EXT_CTRL,
682 dev_err(dai->dev, "Failed to set DPATH RESET: %d\n", ret);
687 switch (xcvr->mode) {
690 ret = regmap_write(xcvr->regmap,
694 dev_err(dai->dev, "err updating isr %d\n", ret);
699 ret = regmap_write(xcvr->regmap,
703 dev_err(dai->dev, "Failed to start DATA_TX: %d\n", ret);
711 ret = regmap_update_bits(xcvr->regmap, FSL_XCVR_EXT_CTRL,
714 dev_err(dai->dev, "Failed to enable DMA: %d\n", ret);
718 ret = regmap_update_bits(xcvr->regmap, FSL_XCVR_EXT_IER0,
721 dev_err(dai->dev, "Error while setting IER0: %d\n", ret);
726 ret = regmap_update_bits(xcvr->regmap, FSL_XCVR_EXT_CTRL,
730 dev_err(dai->dev, "Failed to clear DPATH RESET: %d\n", ret);
739 ret = regmap_update_bits(xcvr->regmap, FSL_XCVR_EXT_CTRL,
743 dev_err(dai->dev, "Failed to disable DMA: %d\n", ret);
747 ret = regmap_update_bits(xcvr->regmap, FSL_XCVR_EXT_IER0,
750 dev_err(dai->dev, "Failed to clear IER0: %d\n", ret);
755 switch (xcvr->mode) {
757 ret = regmap_write(xcvr->regmap,
761 dev_err(dai->dev, "Failed to stop DATA_TX: %d\n", ret);
764 if (xcvr->soc_data->spdif_only)
770 ret = regmap_write(xcvr->regmap,
774 dev_err(dai->dev,
783 ret = -EINVAL;
788 spin_unlock_irqrestore(&xcvr->lock, lock_flags);
792 static int fsl_xcvr_load_firmware(struct fsl_xcvr *xcvr)
794 struct device *dev = &xcvr->pdev->dev;
799 ret = request_firmware(&fw, xcvr->soc_data->fw_name, dev);
805 rem = fw->size;
811 return -ENOMEM;
815 ret = regmap_update_bits(xcvr->regmap, FSL_XCVR_EXT_CTRL,
829 memcpy_toio(xcvr->ram_addr, fw->data + off, out);
830 rem -= out;
834 memset_io(xcvr->ram_addr + out, 0, size - out);
838 memset_io(xcvr->ram_addr, 0, size);
858 ret = regmap_update_bits(xcvr->regmap, FSL_XCVR_EXT_CTRL, mask, val);
865 memcpy_toio(xcvr->ram_addr + FSL_XCVR_CAP_DATA_STR, xcvr->cap_ds,
873 uinfo->type = SNDRV_CTL_ELEM_TYPE_IEC958;
874 uinfo->count = 1;
882 uinfo->type = SNDRV_CTL_ELEM_TYPE_BYTES;
883 uinfo->count = sizeof_field(struct snd_aes_iec958, status);
892 struct fsl_xcvr *xcvr = snd_soc_dai_get_drvdata(dai);
894 memcpy(ucontrol->value.iec958.status, xcvr->rx_iec958.status, 24);
903 struct fsl_xcvr *xcvr = snd_soc_dai_get_drvdata(dai);
905 memcpy(ucontrol->value.iec958.status, xcvr->tx_iec958.status, 24);
914 struct fsl_xcvr *xcvr = snd_soc_dai_get_drvdata(dai);
916 memcpy(xcvr->tx_iec958.status, ucontrol->value.iec958.status, 24);
963 struct fsl_xcvr *xcvr = snd_soc_dai_get_drvdata(dai);
965 snd_soc_dai_init_dma_data(dai, &xcvr->dma_prms_tx, &xcvr->dma_prms_rx);
967 if (xcvr->soc_data->spdif_only)
968 xcvr->mode = FSL_XCVR_MODE_SPDIF;
992 .stream_name = "CPU-Playback",
1001 .stream_name = "CPU-Capture",
1012 .name = "fsl-xcvr-dai",
1068 struct fsl_xcvr *xcvr = dev_get_drvdata(dev);
1070 if (!xcvr->soc_data->use_phy)
1141 struct fsl_xcvr *xcvr = dev_get_drvdata(dev);
1143 if (!xcvr->soc_data->use_phy)
1211 struct fsl_xcvr *xcvr = container_of(work, struct fsl_xcvr, work_rst);
1212 struct device *dev = &xcvr->pdev->dev;
1217 spin_lock_irqsave(&xcvr->lock, lock_flags);
1218 regmap_read(xcvr->regmap, FSL_XCVR_EXT_CTRL, &ext_ctrl);
1221 regmap_update_bits(xcvr->regmap, FSL_XCVR_EXT_CTRL,
1224 regmap_update_bits(xcvr->regmap, FSL_XCVR_EXT_CTRL,
1227 regmap_update_bits(xcvr->regmap, FSL_XCVR_EXT_CTRL,
1230 regmap_update_bits(xcvr->regmap, FSL_XCVR_EXT_CTRL,
1234 spin_unlock_irqrestore(&xcvr->lock, lock_flags);
1239 struct fsl_xcvr *xcvr = (struct fsl_xcvr *)devid;
1240 struct device *dev = &xcvr->pdev->dev;
1241 struct regmap *regmap = xcvr->regmap;
1250 if (!xcvr->soc_data->spdif_only) {
1252 regmap_update_bits(xcvr->regmap, FSL_XCVR_EXT_CTRL,
1257 reg_ctrl = xcvr->ram_addr + FSL_XCVR_RX_CS_CTRL_0;
1258 reg_buff = xcvr->ram_addr + FSL_XCVR_RX_CS_BUFF_0;
1261 reg_ctrl = xcvr->ram_addr + FSL_XCVR_RX_CS_CTRL_1;
1262 reg_buff = xcvr->ram_addr + FSL_XCVR_RX_CS_BUFF_1;
1268 memcpy_fromio(&xcvr->rx_iec958.status, reg_buff,
1269 sizeof(xcvr->rx_iec958.status));
1271 val = *(u32 *)(xcvr->rx_iec958.status + i*4);
1272 *(u32 *)(xcvr->rx_iec958.status + i*4) =
1329 schedule_work(&xcvr->work_rst);
1341 .fw_name = "imx/xcvr/xcvr-imx8mp.bin",
1359 { .compatible = "fsl,imx8mp-xcvr", .data = &fsl_xcvr_imx8mp_data },
1360 { .compatible = "fsl,imx93-xcvr", .data = &fsl_xcvr_imx93_data},
1361 { .compatible = "fsl,imx95-xcvr", .data = &fsl_xcvr_imx95_data},
1368 struct device *dev = &pdev->dev;
1369 struct fsl_xcvr *xcvr;
1374 xcvr = devm_kzalloc(dev, sizeof(*xcvr), GFP_KERNEL);
1375 if (!xcvr)
1376 return -ENOMEM;
1378 xcvr->pdev = pdev;
1379 xcvr->soc_data = of_device_get_match_data(&pdev->dev);
1381 xcvr->ipg_clk = devm_clk_get(dev, "ipg");
1382 if (IS_ERR(xcvr->ipg_clk)) {
1384 return PTR_ERR(xcvr->ipg_clk);
1387 xcvr->phy_clk = devm_clk_get(dev, "phy");
1388 if (IS_ERR(xcvr->phy_clk)) {
1390 return PTR_ERR(xcvr->phy_clk);
1393 xcvr->spba_clk = devm_clk_get(dev, "spba");
1394 if (IS_ERR(xcvr->spba_clk)) {
1396 return PTR_ERR(xcvr->spba_clk);
1399 xcvr->pll_ipg_clk = devm_clk_get(dev, "pll_ipg");
1400 if (IS_ERR(xcvr->pll_ipg_clk)) {
1402 return PTR_ERR(xcvr->pll_ipg_clk);
1405 fsl_asoc_get_pll_clocks(dev, &xcvr->pll8k_clk,
1406 &xcvr->pll11k_clk);
1408 xcvr->ram_addr = devm_platform_ioremap_resource_byname(pdev, "ram");
1409 if (IS_ERR(xcvr->ram_addr))
1410 return PTR_ERR(xcvr->ram_addr);
1416 xcvr->regmap = devm_regmap_init_mmio_clk(dev, NULL, regs,
1418 if (IS_ERR(xcvr->regmap)) {
1419 dev_err(dev, "failed to init XCVR regmap: %ld\n",
1420 PTR_ERR(xcvr->regmap));
1421 return PTR_ERR(xcvr->regmap);
1424 xcvr->reset = devm_reset_control_get_optional_exclusive(dev, NULL);
1425 if (IS_ERR(xcvr->reset)) {
1426 dev_err(dev, "failed to get XCVR reset control\n");
1427 return PTR_ERR(xcvr->reset);
1435 ret = devm_request_irq(dev, irq, irq0_isr, 0, pdev->name, xcvr);
1445 return -EINVAL;
1447 xcvr->dma_prms_rx.chan_name = "rx";
1448 xcvr->dma_prms_tx.chan_name = "tx";
1449 xcvr->dma_prms_rx.addr = rx_res->start;
1450 xcvr->dma_prms_tx.addr = tx_res->start;
1451 xcvr->dma_prms_rx.maxburst = FSL_XCVR_MAXBURST_RX;
1452 xcvr->dma_prms_tx.maxburst = FSL_XCVR_MAXBURST_TX;
1454 platform_set_drvdata(pdev, xcvr);
1456 regcache_cache_only(xcvr->regmap, true);
1477 INIT_WORK(&xcvr->work_rst, reset_rx_work);
1478 spin_lock_init(&xcvr->lock);
1484 struct fsl_xcvr *xcvr = dev_get_drvdata(&pdev->dev);
1486 cancel_work_sync(&xcvr->work_rst);
1487 pm_runtime_disable(&pdev->dev);
1492 struct fsl_xcvr *xcvr = dev_get_drvdata(dev);
1495 if (!xcvr->soc_data->spdif_only) {
1497 ret = regmap_update_bits(xcvr->regmap, FSL_XCVR_EXT_CTRL,
1504 regcache_cache_only(xcvr->regmap, true);
1506 clk_disable_unprepare(xcvr->spba_clk);
1507 clk_disable_unprepare(xcvr->phy_clk);
1508 clk_disable_unprepare(xcvr->pll_ipg_clk);
1509 clk_disable_unprepare(xcvr->ipg_clk);
1516 struct fsl_xcvr *xcvr = dev_get_drvdata(dev);
1519 ret = reset_control_assert(xcvr->reset);
1525 ret = clk_prepare_enable(xcvr->ipg_clk);
1531 ret = clk_prepare_enable(xcvr->pll_ipg_clk);
1537 ret = clk_prepare_enable(xcvr->phy_clk);
1543 ret = clk_prepare_enable(xcvr->spba_clk);
1549 regcache_cache_only(xcvr->regmap, false);
1550 regcache_mark_dirty(xcvr->regmap);
1551 ret = regcache_sync(xcvr->regmap);
1558 if (xcvr->soc_data->spdif_only)
1561 ret = reset_control_deassert(xcvr->reset);
1567 ret = fsl_xcvr_load_firmware(xcvr);
1574 ret = regmap_update_bits(xcvr->regmap, FSL_XCVR_EXT_CTRL,
1587 clk_disable_unprepare(xcvr->spba_clk);
1589 clk_disable_unprepare(xcvr->phy_clk);
1591 clk_disable_unprepare(xcvr->pll_ipg_clk);
1593 clk_disable_unprepare(xcvr->ipg_clk);
1607 .name = "fsl,imx8mp-audio-xcvr",
1616 MODULE_DESCRIPTION("NXP Audio Transceiver (XCVR) driver");