Lines Matching +full:spdif +full:- +full:2

1 /* SPDX-License-Identifier: GPL-2.0 */
3  * fsl_spdif.h - ALSA S/PDIF interface for the Freescale i.MX SoC
11  * Copyright 2007-2008 Freescale Semiconductor, Inc.
18 #define REG_SPDIF_SCR 			0x0	/* SPDIF Configuration Register */
39 #define REG_SPDIF_SRCCA_31_0		0x60	/* SPDIF receive C channel register, bits 31-0 */
40 #define REG_SPDIF_SRCCA_63_32		0x64	/* SPDIF receive C channel register, bits 63-32 */
41 #define REG_SPDIF_SRCCA_95_64		0x68	/* SPDIF receive C channel register, bits 95-64 */
42 #define REG_SPDIF_SRCCA_127_96		0x6C	/* SPDIF receive C channel register, bits 127-96 */
43 #define REG_SPDIF_SRCCA_159_128		0x70	/* SPDIF receive C channel register, bits 159-128 */
44 #define REG_SPDIF_SRCCA_191_160		0x74	/* SPDIF receive C channel register, bits 191-160 */
45 #define REG_SPDIF_STCCA_31_0		0x78	/* SPDIF transmit C channel register, bits 31-0 */
46 #define REG_SPDIF_STCCA_63_32		0x7C	/* SPDIF transmit C channel register, bits 63-32 */
47 #define REG_SPDIF_STCCA_95_64		0x80	/* SPDIF transmit C channel register, bits 95-64 */
48 #define REG_SPDIF_STCCA_127_96		0x84	/* SPDIF transmit C channel register, bits 127-96 */
49 #define REG_SPDIF_STCCA_159_128		0x88	/* SPDIF transmit C channel register, bits 159-128 */
50 #define REG_SPDIF_STCCA_191_160		0x8C	/* SPDIF transmit C channel register, bits 191-160 */
52 /* SPDIF Configuration register */
97 #define SCR_TXSEL_OFFSET		2
110 /* SPDIF CDText control */
114 /* SPDIF Phase Configuration register */
120 #define SRPC_CLKSRC_SEL_LOCKED_OFFSET2	2
139 /* SPDIF interrupt mask define */
155 #define INT_LOSS_LOCK			(1 << 2)
159 /* SPDIF Clock register */
162 #define STC_SYSCLK_DF(x)		((((x) - 1) << STC_SYSCLK_DF_OFFSET) & STC_SYSCLK_DF_MASK)
171 #define STC_TXCLK_DF(x)		((((x) - 1) << STC_TXCLK_DF_OFFSET) & STC_TXCLK_DF_MASK)
176 /* SPDIF tx rate */