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1 /* SPDX-License-Identifier: GPL-2.0 */
3 * Copyright 2012-2013 Freescale Semiconductor, Inc.
9 #include <linux/dma/imx-dma.h>
49 #define FSL_SAI_TBCTN 0x78 /* SAI Transmit Bit Counter Register */
76 #define FSL_SAI_RBCTN 0xf8 /* SAI Receive Bit Counter Register */
93 #define FSL_SAI_CSR_TERE BIT(31)
94 #define FSL_SAI_CSR_SE BIT(30)
95 #define FSL_SAI_CSR_BCE BIT(28)
96 #define FSL_SAI_CSR_FR BIT(25)
97 #define FSL_SAI_CSR_SR BIT(24)
102 #define FSL_SAI_CSR_WSF BIT(20)
103 #define FSL_SAI_CSR_SEF BIT(19)
104 #define FSL_SAI_CSR_FEF BIT(18)
105 #define FSL_SAI_CSR_FWF BIT(17)
106 #define FSL_SAI_CSR_FRF BIT(16)
109 #define FSL_SAI_CSR_WSIE BIT(12)
110 #define FSL_SAI_CSR_SEIE BIT(11)
111 #define FSL_SAI_CSR_FEIE BIT(10)
112 #define FSL_SAI_CSR_FWIE BIT(9)
113 #define FSL_SAI_CSR_FRIE BIT(8)
114 #define FSL_SAI_CSR_FRDE BIT(0)
117 #define FSL_SAI_CR1_RFW_MASK(x) ((x) - 1)
120 #define FSL_SAI_CR2_SYNC BIT(30)
121 #define FSL_SAI_CR2_BCI BIT(28)
124 #define FSL_SAI_CR2_MSEL_MCLK1 BIT(26)
125 #define FSL_SAI_CR2_MSEL_MCLK2 BIT(27)
126 #define FSL_SAI_CR2_MSEL_MCLK3 (BIT(26) | BIT(27))
128 #define FSL_SAI_CR2_BCP BIT(25)
129 #define FSL_SAI_CR2_BCD_MSTR BIT(24)
130 #define FSL_SAI_CR2_BYP BIT(23) /* BCLK bypass */
141 #define FSL_SAI_CR4_FCONT_MASK BIT(28)
142 #define FSL_SAI_CR4_FCONT BIT(28)
143 #define FSL_SAI_CR4_FCOMB_SHIFT BIT(26)
144 #define FSL_SAI_CR4_FCOMB_SOFT BIT(27)
146 #define FSL_SAI_CR4_FPACK_8 (0x2 << 24)
147 #define FSL_SAI_CR4_FPACK_16 (0x3 << 24)
148 #define FSL_SAI_CR4_FRSZ(x) (((x) - 1) << 16)
150 #define FSL_SAI_CR4_SYWD(x) (((x) - 1) << 8)
152 #define FSL_SAI_CR4_CHMOD BIT(5)
153 #define FSL_SAI_CR4_CHMOD_MASK BIT(5)
154 #define FSL_SAI_CR4_MF BIT(4)
155 #define FSL_SAI_CR4_FSE BIT(3)
156 #define FSL_SAI_CR4_FSP BIT(1)
157 #define FSL_SAI_CR4_FSD_MSTR BIT(0)
160 #define FSL_SAI_CR5_WNW(x) (((x) - 1) << 24)
161 #define FSL_SAI_CR5_WNW_MASK (0x1f << 24)
162 #define FSL_SAI_CR5_W0W(x) (((x) - 1) << 16)
168 #define FSL_SAI_MCTL_MCLK_EN BIT(30) /* MCLK Enable */
169 #define FSL_SAI_MCTL_MSEL_MASK (0x3 << 24)
170 #define FSL_SAI_MCTL_MSEL(ID) ((ID) << 24)
172 #define FSL_SAI_MCTL_MSEL_MCLK1 BIT(24)
173 #define FSL_SAI_MCTL_MSEL_MCLK2 BIT(25)
174 #define FSL_SAI_MCTL_MSEL_MCLK3 (BIT(24) | BIT(25))
175 #define FSL_SAI_MCTL_DIV_EN BIT(23)
179 #define FSL_SAI_VERID_MAJOR_SHIFT 24
180 #define FSL_SAI_VERID_MAJOR_MASK GENMASK(31, 24)
185 #define FSL_SAI_VERID_EFIFO_EN BIT(0)
186 #define FSL_SAI_VERID_TSTMP_EN BIT(1)
199 #define FSL_SAI_xTCTL_TSEN BIT(0)
200 #define FSL_SAI_xTCTL_TSINC BIT(1)
201 #define FSL_SAI_xTCTL_RTSC BIT(8)
202 #define FSL_SAI_xTCTL_RBC BIT(9)
205 #define FSL_SAI_DMA BIT(0)
206 #define FSL_SAI_USE_AC97 BIT(1)
207 #define FSL_SAI_NET BIT(2)
208 #define FSL_SAI_TRA_SYN BIT(3)
209 #define FSL_SAI_REC_SYN BIT(4)
210 #define FSL_SAI_USE_I2S_SLAVE BIT(5)
224 #define PMQOS_CPU_LATENCY BIT(0)
230 #define FSL_SAI_DL_I2S BIT(0)
231 #define FSL_SAI_DL_PDM BIT(1)
247 * struct fsl_sai_verid - version id data
250 * 0000000000000000b - Standard feature set
251 * 0000000000000000b - Standard feature set
259 * struct fsl_sai_param - parameter data