Lines Matching +full:te +full:- +full:source
1 // SPDX-License-Identifier: GPL-2.0+
5 // Copyright 2012-2015 Freescale Semiconductor, Inc.
22 #include <linux/mfd/syscon/imx6q-iomuxc-gpr.h>
26 #include "imx-pcm.h"
44 * fsl_sai_dir_is_synced - Check if stream is synced by the opposite stream
58 return !sai->synchronous[dir] && sai->synchronous[adir];
65 if (sai->is_pdm_mode) {
68 state = pinctrl_lookup_state(sai->pinctrl, "dsd512");
72 state = pinctrl_lookup_state(sai->pinctrl, "dsd");
76 state = pinctrl_lookup_state(sai->pinctrl, "pcm_b2m");
81 state = pinctrl_lookup_state(sai->pinctrl, "default");
89 unsigned int ofs = sai->soc_data->reg_offset;
90 struct device *dev = &sai->pdev->dev;
102 regmap_read(sai->regmap, FSL_SAI_TCSR(ofs), &xcsr);
129 regmap_write(sai->regmap, FSL_SAI_TCSR(ofs), flags | xcsr);
133 regmap_read(sai->regmap, FSL_SAI_RCSR(ofs), &xcsr);
160 regmap_write(sai->regmap, FSL_SAI_RCSR(ofs), flags | xcsr);
172 sai->slots[tx] = slots;
173 sai->slot_width[tx] = slot_width;
184 sai->slots[tx] = slots;
185 sai->slot_width[tx] = slot_width;
214 sai->bclk_ratio = ratio;
223 unsigned int ofs = sai->soc_data->reg_offset;
240 return -EINVAL;
243 regmap_update_bits(sai->regmap, FSL_SAI_xCR2(tx, ofs),
254 fsl_asoc_reparent_pll_clocks(dai->dev, sai->mclk_clk[clk_id],
255 sai->pll8k_clk, sai->pll11k_clk, freq);
257 ret = clk_set_rate(sai->mclk_clk[clk_id], freq);
259 dev_err(dai->dev, "failed to set clock rate (%u): %d\n", freq, ret);
274 dev_err(cpu_dai->dev, "Unknown clock id: %d\n", clk_id);
275 return -EINVAL;
278 if (IS_ERR_OR_NULL(sai->mclk_clk[clk_id])) {
279 dev_err(cpu_dai->dev, "Unassigned clock: %d\n", clk_id);
280 return -EINVAL;
283 if (sai->mclk_streams == 0 && freq > 0) {
293 dev_err(cpu_dai->dev, "Cannot set tx sysclk: %d\n", ret);
299 dev_err(cpu_dai->dev, "Cannot set rx sysclk: %d\n", ret);
308 unsigned int ofs = sai->soc_data->reg_offset;
311 if (!sai->is_lsb_first)
314 sai->is_pdm_mode = false;
315 sai->is_dsp_mode[tx] = false;
344 sai->is_dsp_mode[tx] = true;
352 sai->is_dsp_mode[tx] = true;
357 sai->is_pdm_mode = true;
362 return -EINVAL;
384 return -EINVAL;
392 sai->is_consumer_mode[tx] = false;
395 sai->is_consumer_mode[tx] = true;
399 sai->is_consumer_mode[tx] = false;
403 sai->is_consumer_mode[tx] = true;
406 return -EINVAL;
409 regmap_update_bits(sai->regmap, FSL_SAI_xCR2(tx, ofs),
411 regmap_update_bits(sai->regmap, FSL_SAI_xCR4(tx, ofs),
424 dev_err(cpu_dai->dev, "Cannot set tx format: %d\n", ret);
430 dev_err(cpu_dai->dev, "Cannot set rx format: %d\n", ret);
448 unsigned int reg, ofs = sai->soc_data->reg_offset;
454 bool support_1_1_ratio = sai->verid.version >= 0x0301;
457 if (sai->is_consumer_mode[tx])
465 id = sai->soc_data->mclk0_is_mclk1 ? 1 : 0;
470 clk_rate = clk_get_rate(sai->mclk_clk[id]);
482 diff = abs((long)clk_rate - ratio * freq);
485 * Drop the source that can not be
491 dev_dbg(dai->dev,
498 sai->mclk_id[tx] = id;
507 dev_err(dai->dev, "failed to derive required %cx rate: %d\n",
509 return -EINVAL;
512 dev_dbg(dai->dev, "best fit: clock id=%d, div=%d, deviation =%d\n",
513 sai->mclk_id[tx], savediv, bestdiff);
527 else if (!sai->synchronous[dir])
532 regmap_update_bits(sai->regmap, reg, FSL_SAI_CR2_MSEL_MASK,
533 FSL_SAI_CR2_MSEL(sai->mclk_id[tx]));
536 regmap_update_bits(sai->regmap, reg,
540 regmap_update_bits(sai->regmap, FSL_SAI_xCR2(tx, ofs),
543 regmap_update_bits(sai->regmap, FSL_SAI_xCR2(tx, ofs),
546 regmap_update_bits(sai->regmap, reg,
548 savediv / 2 - 1);
559 unsigned int ofs = sai->soc_data->reg_offset;
560 bool tx = substream->stream == SNDRV_PCM_STREAM_PLAYBACK;
563 struct fsl_sai_dl_cfg *dl_cfg = sai->dl_cfg;
566 int dl_cfg_cnt = sai->dl_cfg_cnt;
576 if (sai->slot_width[tx])
577 slot_width = sai->slot_width[tx];
579 if (sai->slots[tx])
580 slots = sai->slots[tx];
581 else if (sai->bclk_ratio)
582 slots = sai->bclk_ratio / slot_width;
590 if (sai->is_pdm_mode) {
603 dev_err(cpu_dai->dev, "channel not supported\n");
604 return -EINVAL;
607 bclk = params_rate(params) * (sai->bclk_ratio ? sai->bclk_ratio : slots * slot_width);
609 if (!IS_ERR_OR_NULL(sai->pinctrl)) {
610 sai->pins_state = fsl_sai_get_pins_state(sai, bclk);
611 if (!IS_ERR_OR_NULL(sai->pins_state)) {
612 ret = pinctrl_select_state(sai->pinctrl, sai->pins_state);
614 dev_err(cpu_dai->dev, "failed to set proper pins state: %d\n", ret);
620 if (!sai->is_consumer_mode[tx]) {
626 if (!(sai->mclk_streams & BIT(substream->stream))) {
627 ret = clk_prepare_enable(sai->mclk_clk[sai->mclk_id[tx]]);
631 sai->mclk_streams |= BIT(substream->stream);
635 if (!sai->is_dsp_mode[tx] && !sai->is_pdm_mode)
641 if (sai->is_lsb_first || sai->is_pdm_mode)
644 val_cr5 |= FSL_SAI_CR5_FBT(word_width - 1);
651 /* Set to output mode to avoid tri-stated data pins */
661 if (!sai->is_consumer_mode[tx] && fsl_sai_dir_is_synced(sai, adir)) {
662 regmap_update_bits(sai->regmap, FSL_SAI_xCR4(!tx, ofs),
666 regmap_update_bits(sai->regmap, FSL_SAI_xCR5(!tx, ofs),
673 * - Can't used for singel dataline/FIFO case except the FIFO0
674 * - Can't used for multi dataline/FIFO case except the enabled FIFOs
679 if (hweight8(dl_cfg[dl_cfg_idx].mask[tx]) <= 1 || sai->is_multi_fifo_dma)
680 regmap_update_bits(sai->regmap, FSL_SAI_xCR4(tx, ofs),
683 regmap_update_bits(sai->regmap, FSL_SAI_xCR4(tx, ofs),
686 dma_params = tx ? &sai->dma_params_tx : &sai->dma_params_rx;
687 dma_params->addr = sai->res->start + FSL_SAI_xDR0(tx) +
690 if (sai->is_multi_fifo_dma) {
691 sai->audio_config[tx].words_per_fifo = min(slots, channels);
693 sai->audio_config[tx].n_fifos_dst = pins;
694 sai->audio_config[tx].stride_fifos_dst = dl_cfg[dl_cfg_idx].next_off[tx];
696 sai->audio_config[tx].n_fifos_src = pins;
697 sai->audio_config[tx].stride_fifos_src = dl_cfg[dl_cfg_idx].next_off[tx];
699 dma_params->maxburst = sai->audio_config[tx].words_per_fifo * pins;
700 dma_params->peripheral_config = &sai->audio_config[tx];
701 dma_params->peripheral_size = sizeof(sai->audio_config[tx]);
703 watermark = tx ? (sai->soc_data->fifo_depth - dma_params->maxburst) :
704 (dma_params->maxburst - 1);
705 regmap_update_bits(sai->regmap, FSL_SAI_xCR1(tx, ofs),
706 FSL_SAI_CR1_RFW_MASK(sai->soc_data->fifo_depth),
711 for (i = 0; i < sai->soc_data->pins; i++) {
712 trce_mask = (1 << (i + 1)) - 1;
717 regmap_update_bits(sai->regmap, FSL_SAI_xCR3(tx, ofs),
730 if (sai->soc_data->mclk_with_tere && sai->mclk_direction_output &&
731 !sai->is_consumer_mode[tx])
732 regmap_update_bits(sai->regmap, FSL_SAI_xCR4(tx, ofs),
735 regmap_update_bits(sai->regmap, FSL_SAI_xCR4(tx, ofs),
739 regmap_update_bits(sai->regmap, FSL_SAI_xCR5(tx, ofs),
744 if (sai->soc_data->mclk_with_tere && sai->mclk_direction_output &&
745 !sai->is_consumer_mode[tx])
746 regmap_update_bits(sai->regmap, FSL_SAI_xCR4(tx, ofs),
749 regmap_write(sai->regmap, FSL_SAI_xMR(tx),
750 ~0UL - ((1 << min(channels, slots)) - 1));
759 bool tx = substream->stream == SNDRV_PCM_STREAM_PLAYBACK;
760 unsigned int ofs = sai->soc_data->reg_offset;
763 regmap_write(sai->regmap, FSL_SAI_xMR(tx), 0);
765 regmap_update_bits(sai->regmap, FSL_SAI_xCR3(tx, ofs),
768 if (!sai->is_consumer_mode[tx] &&
769 sai->mclk_streams & BIT(substream->stream)) {
770 clk_disable_unprepare(sai->mclk_clk[sai->mclk_id[tx]]);
771 sai->mclk_streams &= ~BIT(substream->stream);
779 unsigned int ofs = sai->soc_data->reg_offset;
783 if (sai->soc_data->mclk_with_tere && sai->mclk_direction_output)
788 regmap_update_bits(sai->regmap, FSL_SAI_xCSR(tx, ofs),
794 regmap_read(sai->regmap, FSL_SAI_xCSR(tx, ofs), &xcsr);
795 } while (--count && xcsr & FSL_SAI_CSR_TERE);
797 regmap_update_bits(sai->regmap, FSL_SAI_xCSR(tx, ofs),
812 regmap_update_bits(sai->regmap, FSL_SAI_xCSR(tx, ofs), FSL_SAI_CSR_SR, FSL_SAI_CSR_SR);
814 regmap_update_bits(sai->regmap, FSL_SAI_xCSR(tx, ofs), FSL_SAI_CSR_SR, 0);
821 unsigned int ofs = sai->soc_data->reg_offset;
823 bool tx = substream->stream == SNDRV_PCM_STREAM_PLAYBACK;
833 regmap_update_bits(sai->regmap, FSL_SAI_TCR2(ofs), FSL_SAI_CR2_SYNC,
834 sai->synchronous[TX] ? FSL_SAI_CR2_SYNC : 0);
835 regmap_update_bits(sai->regmap, FSL_SAI_RCR2(ofs), FSL_SAI_CR2_SYNC,
836 sai->synchronous[RX] ? FSL_SAI_CR2_SYNC : 0);
846 regmap_update_bits(sai->regmap, FSL_SAI_xCSR(tx, ofs),
849 regmap_update_bits(sai->regmap, FSL_SAI_xCSR(tx, ofs),
853 * 1. Tx sync with Rx: only set RE for Rx; set TE & RE for Tx
854 * 2. Rx sync with Tx: only set TE for Tx; set RE & TE for Rx
856 * RM recommends to enable RE after TE for case 1 and to enable
857 * TE after RE for case 2, but we here may not always guarantee
859 * TE after RE, which is against what RM recommends but should
863 regmap_update_bits(sai->regmap, FSL_SAI_xCSR((!tx), ofs),
866 regmap_update_bits(sai->regmap, FSL_SAI_xCSR(tx, ofs),
872 regmap_update_bits(sai->regmap, FSL_SAI_xCSR(tx, ofs),
874 regmap_update_bits(sai->regmap, FSL_SAI_xCSR(tx, ofs),
878 regmap_read(sai->regmap, FSL_SAI_xCSR(!tx, ofs), &xcsr);
898 return -EINVAL;
908 bool tx = substream->stream == SNDRV_PCM_STREAM_PLAYBACK;
915 if (sai->soc_data->use_edma)
916 snd_pcm_hw_constraint_step(substream->runtime, 0,
918 tx ? sai->dma_params_tx.maxburst :
919 sai->dma_params_rx.maxburst);
921 ret = snd_pcm_hw_constraint_list(substream->runtime, 0,
922 SNDRV_PCM_HW_PARAM_RATE, &sai->constraint_rates);
929 struct fsl_sai *sai = dev_get_drvdata(cpu_dai->dev);
930 unsigned int ofs = sai->soc_data->reg_offset;
933 regmap_update_bits(sai->regmap, FSL_SAI_TCSR(ofs), FSL_SAI_CSR_SR, FSL_SAI_CSR_SR);
934 regmap_update_bits(sai->regmap, FSL_SAI_RCSR(ofs), FSL_SAI_CSR_SR, FSL_SAI_CSR_SR);
936 regmap_update_bits(sai->regmap, FSL_SAI_TCSR(ofs), FSL_SAI_CSR_SR, 0);
937 regmap_update_bits(sai->regmap, FSL_SAI_RCSR(ofs), FSL_SAI_CSR_SR, 0);
939 regmap_update_bits(sai->regmap, FSL_SAI_TCR1(ofs),
940 FSL_SAI_CR1_RFW_MASK(sai->soc_data->fifo_depth),
941 sai->soc_data->fifo_depth - sai->dma_params_tx.maxburst);
942 regmap_update_bits(sai->regmap, FSL_SAI_RCR1(ofs),
943 FSL_SAI_CR1_RFW_MASK(sai->soc_data->fifo_depth),
944 sai->dma_params_rx.maxburst - 1);
946 snd_soc_dai_init_dma_data(cpu_dai, &sai->dma_params_tx,
947 &sai->dma_params_rx);
993 struct device *dev = &sai->pdev->dev;
996 if (!IS_ERR_OR_NULL(sai->pinctrl) && !IS_ERR_OR_NULL(sai->pins_state)) {
997 ret = pinctrl_select_state(sai->pinctrl, sai->pins_state);
1009 .name = "sai-tx-rx",
1011 .stream_name = "CPU-Playback",
1020 .stream_name = "CPU-Capture",
1031 .name = "sai-tx",
1033 .stream_name = "SAI-Playback",
1044 .name = "sai-rx",
1046 .stream_name = "SAI-Capture",
1059 .name = "fsl-sai",
1115 unsigned int ofs = sai->soc_data->reg_offset;
1171 unsigned int ofs = sai->soc_data->reg_offset;
1214 unsigned int ofs = sai->soc_data->reg_offset;
1260 unsigned char ofs = sai->soc_data->reg_offset;
1267 ret = regmap_read(sai->regmap, FSL_SAI_VERID, &val);
1273 sai->verid.version = val &
1275 sai->verid.version >>= FSL_SAI_VERID_MINOR_SHIFT;
1276 sai->verid.feature = val & FSL_SAI_VERID_FEATURE_MASK;
1278 ret = regmap_read(sai->regmap, FSL_SAI_PARAM, &val);
1285 sai->param.slot_num = 1 <<
1289 sai->param.fifo_depth = 1 <<
1293 sai->param.dataline = val & FSL_SAI_PARAM_DLN_MASK;
1308 offset = nbidx - fbidx - 1;
1310 return (offset < 0 || offset >= (FSL_SAI_DL_NUM - 1) ? 0 : offset);
1327 struct platform_device *pdev = sai->pdev;
1328 struct device_node *np = pdev->dev.of_node;
1329 struct device *dev = &pdev->dev;
1343 return -EINVAL;
1348 cfg = devm_kcalloc(&pdev->dev, num_cfg + 1, sizeof(*cfg), GFP_KERNEL);
1350 return -ENOMEM;
1353 soc_dl = BIT(sai->soc_data->pins) - 1;
1355 cfg[0].pins[0] = sai->soc_data->pins;
1360 cfg[0].pins[1] = sai->soc_data->pins;
1373 return -EINVAL;
1377 return -EINVAL;
1381 return -EINVAL;
1385 return -EINVAL;
1405 sai->dl_cfg = cfg;
1406 sai->dl_cfg_cnt = num_cfg + 1;
1415 struct device_node *np = pdev->dev.of_node;
1416 struct device *dev = &pdev->dev;
1427 return -ENOMEM;
1429 sai->pdev = pdev;
1430 sai->soc_data = of_device_get_match_data(dev);
1432 sai->is_lsb_first = of_property_read_bool(np, "lsb-first");
1434 base = devm_platform_get_and_ioremap_resource(pdev, 0, &sai->res);
1438 if (sai->soc_data->reg_offset == 8) {
1445 sai->regmap = devm_regmap_init_mmio(dev, base, &fsl_sai_regmap_config);
1446 if (IS_ERR(sai->regmap)) {
1448 return PTR_ERR(sai->regmap);
1451 sai->bus_clk = devm_clk_get(dev, "bus");
1453 if (IS_ERR(sai->bus_clk) && PTR_ERR(sai->bus_clk) != -EPROBE_DEFER)
1454 sai->bus_clk = devm_clk_get(dev, "sai");
1455 if (IS_ERR(sai->bus_clk)) {
1457 PTR_ERR(sai->bus_clk));
1458 /* -EPROBE_DEFER */
1459 return PTR_ERR(sai->bus_clk);
1464 sai->mclk_clk[i] = devm_clk_get(dev, tmp);
1465 if (IS_ERR(sai->mclk_clk[i])) {
1467 i, PTR_ERR(sai->mclk_clk[i]));
1468 sai->mclk_clk[i] = NULL;
1472 if (sai->soc_data->mclk0_is_mclk1)
1473 sai->mclk_clk[0] = sai->mclk_clk[1];
1475 sai->mclk_clk[0] = sai->bus_clk;
1477 fsl_asoc_get_pll_clocks(&pdev->dev, &sai->pll8k_clk,
1478 &sai->pll11k_clk);
1480 fsl_asoc_constrain_rates(&sai->constraint_rates,
1482 sai->pll8k_clk, sai->pll11k_clk, NULL,
1483 sai->constraint_rates_list);
1487 if (!sai->soc_data->use_edma && !ret && dmas[2] == IMX_DMATYPE_MULTI_SAI)
1488 sai->is_multi_fifo_dma = true;
1502 np->name, sai);
1508 memcpy(&sai->cpu_dai_drv, fsl_sai_dai_template,
1512 sai->synchronous[RX] = true;
1513 sai->synchronous[TX] = false;
1514 sai->cpu_dai_drv[0].symmetric_rate = 1;
1515 sai->cpu_dai_drv[0].symmetric_channels = 1;
1516 sai->cpu_dai_drv[0].symmetric_sample_bits = 1;
1518 if (of_property_read_bool(np, "fsl,sai-synchronous-rx") &&
1519 of_property_read_bool(np, "fsl,sai-asynchronous")) {
1522 return -EINVAL;
1525 if (of_property_read_bool(np, "fsl,sai-synchronous-rx")) {
1527 sai->synchronous[RX] = false;
1528 sai->synchronous[TX] = true;
1529 } else if (of_property_read_bool(np, "fsl,sai-asynchronous")) {
1531 sai->synchronous[RX] = false;
1532 sai->synchronous[TX] = false;
1533 sai->cpu_dai_drv[0].symmetric_rate = 0;
1534 sai->cpu_dai_drv[0].symmetric_channels = 0;
1535 sai->cpu_dai_drv[0].symmetric_sample_bits = 0;
1538 sai->mclk_direction_output = of_property_read_bool(np, "fsl,sai-mclk-direction-output");
1540 if (sai->mclk_direction_output &&
1541 of_device_is_compatible(np, "fsl,imx6ul-sai")) {
1542 gpr = syscon_regmap_lookup_by_compatible("fsl,imx6ul-iomuxc-gpr");
1556 sai->dma_params_rx.addr = sai->res->start + FSL_SAI_RDR0;
1557 sai->dma_params_tx.addr = sai->res->start + FSL_SAI_TDR0;
1558 sai->dma_params_rx.maxburst =
1559 sai->soc_data->max_burst[RX] ? sai->soc_data->max_burst[RX] : FSL_SAI_MAXBURST_RX;
1560 sai->dma_params_tx.maxburst =
1561 sai->soc_data->max_burst[TX] ? sai->soc_data->max_burst[TX] : FSL_SAI_MAXBURST_TX;
1563 sai->pinctrl = devm_pinctrl_get(&pdev->dev);
1583 if (sai->mclk_direction_output &&
1584 sai->soc_data->max_register >= FSL_SAI_MCTL) {
1585 regmap_update_bits(sai->regmap, FSL_SAI_MCTL,
1590 if (ret < 0 && ret != -ENOSYS)
1597 if (sai->soc_data->use_imx_pcm) {
1602 dev_err(dev, "Error: You must enable the imx-pcm-dma support!\n");
1614 sai->cpu_dai_drv, ARRAY_SIZE(fsl_sai_dai_template));
1631 pm_runtime_disable(&pdev->dev);
1632 if (!pm_runtime_status_suspended(&pdev->dev))
1633 fsl_sai_runtime_suspend(&pdev->dev);
1761 { .compatible = "fsl,vf610-sai", .data = &fsl_sai_vf610_data },
1762 { .compatible = "fsl,imx6sx-sai", .data = &fsl_sai_imx6sx_data },
1763 { .compatible = "fsl,imx6ul-sai", .data = &fsl_sai_imx6sx_data },
1764 { .compatible = "fsl,imx7ulp-sai", .data = &fsl_sai_imx7ulp_data },
1765 { .compatible = "fsl,imx8mq-sai", .data = &fsl_sai_imx8mq_data },
1766 { .compatible = "fsl,imx8qm-sai", .data = &fsl_sai_imx8qm_data },
1767 { .compatible = "fsl,imx8mm-sai", .data = &fsl_sai_imx8mm_data },
1768 { .compatible = "fsl,imx8mp-sai", .data = &fsl_sai_imx8mp_data },
1769 { .compatible = "fsl,imx8ulp-sai", .data = &fsl_sai_imx8ulp_data },
1770 { .compatible = "fsl,imx8mn-sai", .data = &fsl_sai_imx8mn_data },
1771 { .compatible = "fsl,imx93-sai", .data = &fsl_sai_imx93_data },
1772 { .compatible = "fsl,imx95-sai", .data = &fsl_sai_imx95_data },
1781 if (sai->mclk_streams & BIT(SNDRV_PCM_STREAM_CAPTURE))
1782 clk_disable_unprepare(sai->mclk_clk[sai->mclk_id[0]]);
1784 if (sai->mclk_streams & BIT(SNDRV_PCM_STREAM_PLAYBACK))
1785 clk_disable_unprepare(sai->mclk_clk[sai->mclk_id[1]]);
1787 clk_disable_unprepare(sai->bus_clk);
1789 if (sai->soc_data->flags & PMQOS_CPU_LATENCY)
1790 cpu_latency_qos_remove_request(&sai->pm_qos_req);
1792 regcache_cache_only(sai->regmap, true);
1800 unsigned int ofs = sai->soc_data->reg_offset;
1803 ret = clk_prepare_enable(sai->bus_clk);
1809 if (sai->mclk_streams & BIT(SNDRV_PCM_STREAM_PLAYBACK)) {
1810 ret = clk_prepare_enable(sai->mclk_clk[sai->mclk_id[1]]);
1815 if (sai->mclk_streams & BIT(SNDRV_PCM_STREAM_CAPTURE)) {
1816 ret = clk_prepare_enable(sai->mclk_clk[sai->mclk_id[0]]);
1821 if (sai->soc_data->flags & PMQOS_CPU_LATENCY)
1822 cpu_latency_qos_add_request(&sai->pm_qos_req, 0);
1824 regcache_cache_only(sai->regmap, false);
1825 regcache_mark_dirty(sai->regmap);
1826 regmap_update_bits(sai->regmap, FSL_SAI_TCSR(ofs), FSL_SAI_CSR_SR, FSL_SAI_CSR_SR);
1827 regmap_update_bits(sai->regmap, FSL_SAI_RCSR(ofs), FSL_SAI_CSR_SR, FSL_SAI_CSR_SR);
1829 regmap_update_bits(sai->regmap, FSL_SAI_TCSR(ofs), FSL_SAI_CSR_SR, 0);
1830 regmap_update_bits(sai->regmap, FSL_SAI_RCSR(ofs), FSL_SAI_CSR_SR, 0);
1832 ret = regcache_sync(sai->regmap);
1836 if (sai->soc_data->mclk_with_tere && sai->mclk_direction_output)
1837 regmap_update_bits(sai->regmap, FSL_SAI_TCSR(ofs),
1843 if (sai->mclk_streams & BIT(SNDRV_PCM_STREAM_CAPTURE))
1844 clk_disable_unprepare(sai->mclk_clk[sai->mclk_id[0]]);
1846 if (sai->mclk_streams & BIT(SNDRV_PCM_STREAM_PLAYBACK))
1847 clk_disable_unprepare(sai->mclk_clk[sai->mclk_id[1]]);
1849 clk_disable_unprepare(sai->bus_clk);
1863 .name = "fsl-sai",
1872 MODULE_ALIAS("platform:fsl-sai");