55 	int adir = (dir == TX) ? RX : TX;  in fsl_sai_dir_is_synced()
101 	/* Tx IRQ */  in fsl_sai_isr()
111 		dev_dbg(dev, "isr: Start of Tx word detected\n");  in fsl_sai_isr()
114 		dev_dbg(dev, "isr: Tx Frame sync error detected\n");  in fsl_sai_isr()
188 		int clk_id, unsigned int freq, bool tx)  in fsl_sai_set_dai_sysclk_tr()  argument
211 	regmap_update_bits(sai->regmap, FSL_SAI_xCR2(tx, ofs),  in fsl_sai_set_dai_sysclk_tr()
261 		dev_err(cpu_dai->dev, "Cannot set tx sysclk: %d\n", ret);  in fsl_sai_set_dai_sysclk()
273 				unsigned int fmt, bool tx)  in fsl_sai_set_dai_fmt_tr()  argument
360 		sai->is_consumer_mode[tx] = false;  in fsl_sai_set_dai_fmt_tr()
363 		sai->is_consumer_mode[tx] = true;  in fsl_sai_set_dai_fmt_tr()
367 		sai->is_consumer_mode[tx] = false;  in fsl_sai_set_dai_fmt_tr()
371 		sai->is_consumer_mode[tx] = true;  in fsl_sai_set_dai_fmt_tr()
377 	regmap_update_bits(sai->regmap, FSL_SAI_xCR2(tx, ofs),  in fsl_sai_set_dai_fmt_tr()
379 	regmap_update_bits(sai->regmap, FSL_SAI_xCR4(tx, ofs),  in fsl_sai_set_dai_fmt_tr()
392 		dev_err(cpu_dai->dev, "Cannot set tx format: %d\n", ret);  in fsl_sai_set_dai_fmt()
413 static int fsl_sai_set_bclk(struct snd_soc_dai *dai, bool tx, u32 freq)  in fsl_sai_set_bclk()  argument
419 	int adir = tx ? RX : TX;  in fsl_sai_set_bclk()
420 	int dir = tx ? TX : RX;  in fsl_sai_set_bclk()
425 	if (sai->is_consumer_mode[tx])  in fsl_sai_set_bclk()
466 			sai->mclk_id[tx] = id;  in fsl_sai_set_bclk()
476 				tx ? 'T' : 'R', freq);  in fsl_sai_set_bclk()
481 			sai->mclk_id[tx], savediv, bestdiff);  in fsl_sai_set_bclk()
486 	 * 2) For Tx sync with Rx clock, we must set RCR2 register for playback  in fsl_sai_set_bclk()
488 	 * 3) For Rx sync with Tx clock, we must set TCR2 register for playback  in fsl_sai_set_bclk()
490 	 * 4) For Tx and Rx are both Synchronous with another SAI, we just  in fsl_sai_set_bclk()
494 		reg = FSL_SAI_xCR2(!tx, ofs);  in fsl_sai_set_bclk()
496 		reg = FSL_SAI_xCR2(tx, ofs);  in fsl_sai_set_bclk()
501 			   FSL_SAI_CR2_MSEL(sai->mclk_id[tx]));  in fsl_sai_set_bclk()
508 			regmap_update_bits(sai->regmap, FSL_SAI_xCR2(tx, ofs),  in fsl_sai_set_bclk()
511 			regmap_update_bits(sai->regmap, FSL_SAI_xCR2(tx, ofs),  in fsl_sai_set_bclk()
528 	bool tx = substream->stream == SNDRV_PCM_STREAM_PLAYBACK;  in fsl_sai_hw_params()  local
539 	int adir = tx ? RX : TX;  in fsl_sai_hw_params()
564 		if (dl_cfg[i].type == dl_type && dl_cfg[i].pins[tx] == pins) {  in fsl_sai_hw_params()
570 	if (hweight8(dl_cfg[dl_cfg_idx].mask[tx]) < pins) {  in fsl_sai_hw_params()
588 	if (!sai->is_consumer_mode[tx]) {  in fsl_sai_hw_params()
589 		ret = fsl_sai_set_bclk(cpu_dai, tx, bclk);  in fsl_sai_hw_params()
595 			ret = clk_prepare_enable(sai->mclk_clk[sai->mclk_id[tx]]);  in fsl_sai_hw_params()
620 	if (tx)  in fsl_sai_hw_params()
624 	 * For SAI provider mode, when Tx(Rx) sync with Rx(Tx) clock, Rx(Tx) will  in fsl_sai_hw_params()
625 	 * generate bclk and frame clock for Tx(Rx), we should set RCR4(TCR4),  in fsl_sai_hw_params()
629 	if (!sai->is_consumer_mode[tx] && fsl_sai_dir_is_synced(sai, adir)) {  in fsl_sai_hw_params()
630 		regmap_update_bits(sai->regmap, FSL_SAI_xCR4(!tx, ofs),  in fsl_sai_hw_params()
634 		regmap_update_bits(sai->regmap, FSL_SAI_xCR5(!tx, ofs),  in fsl_sai_hw_params()
647 	if (hweight8(dl_cfg[dl_cfg_idx].mask[tx]) <= 1 || sai->is_multi_fifo_dma)  in fsl_sai_hw_params()
648 		regmap_update_bits(sai->regmap, FSL_SAI_xCR4(tx, ofs),  in fsl_sai_hw_params()
651 		regmap_update_bits(sai->regmap, FSL_SAI_xCR4(tx, ofs),  in fsl_sai_hw_params()
654 	dma_params = tx ? &sai->dma_params_tx : &sai->dma_params_rx;  in fsl_sai_hw_params()
655 	dma_params->addr = sai->res->start + FSL_SAI_xDR0(tx) +  in fsl_sai_hw_params()
656 			   dl_cfg[dl_cfg_idx].start_off[tx] * 0x4;  in fsl_sai_hw_params()
659 		sai->audio_config[tx].words_per_fifo = min(slots, channels);  in fsl_sai_hw_params()
660 		if (tx) {  in fsl_sai_hw_params()
661 			sai->audio_config[tx].n_fifos_dst = pins;  in fsl_sai_hw_params()
662 			sai->audio_config[tx].stride_fifos_dst = dl_cfg[dl_cfg_idx].next_off[tx];  in fsl_sai_hw_params()
664 			sai->audio_config[tx].n_fifos_src = pins;  in fsl_sai_hw_params()
665 			sai->audio_config[tx].stride_fifos_src = dl_cfg[dl_cfg_idx].next_off[tx];  in fsl_sai_hw_params()
667 		dma_params->maxburst = sai->audio_config[tx].words_per_fifo * pins;  in fsl_sai_hw_params()
668 		dma_params->peripheral_config = &sai->audio_config[tx];  in fsl_sai_hw_params()
669 		dma_params->peripheral_size = sizeof(sai->audio_config[tx]);  in fsl_sai_hw_params()
671 		watermark = tx ? (sai->soc_data->fifo_depth - dma_params->maxburst) :  in fsl_sai_hw_params()
673 		regmap_update_bits(sai->regmap, FSL_SAI_xCR1(tx, ofs),  in fsl_sai_hw_params()
681 		if (hweight8(dl_cfg[dl_cfg_idx].mask[tx] & trce_mask) == pins)  in fsl_sai_hw_params()
685 	regmap_update_bits(sai->regmap, FSL_SAI_xCR3(tx, ofs),  in fsl_sai_hw_params()
687 			   FSL_SAI_CR3_TRCE((dl_cfg[dl_cfg_idx].mask[tx] & trce_mask)));  in fsl_sai_hw_params()
699 	    !sai->is_consumer_mode[tx])  in fsl_sai_hw_params()
700 		regmap_update_bits(sai->regmap, FSL_SAI_xCR4(tx, ofs),  in fsl_sai_hw_params()
703 	regmap_update_bits(sai->regmap, FSL_SAI_xCR4(tx, ofs),  in fsl_sai_hw_params()
707 	regmap_update_bits(sai->regmap, FSL_SAI_xCR5(tx, ofs),  in fsl_sai_hw_params()
713 	    !sai->is_consumer_mode[tx])  in fsl_sai_hw_params()
714 		regmap_update_bits(sai->regmap, FSL_SAI_xCR4(tx, ofs),  in fsl_sai_hw_params()
717 	regmap_write(sai->regmap, FSL_SAI_xMR(tx),  in fsl_sai_hw_params()
727 	bool tx = substream->stream == SNDRV_PCM_STREAM_PLAYBACK;  in fsl_sai_hw_free()  local
731 	regmap_write(sai->regmap, FSL_SAI_xMR(tx), 0);  in fsl_sai_hw_free()
733 	regmap_update_bits(sai->regmap, FSL_SAI_xCR3(tx, ofs),  in fsl_sai_hw_free()
736 	if (!sai->is_consumer_mode[tx] &&  in fsl_sai_hw_free()
738 		clk_disable_unprepare(sai->mclk_clk[sai->mclk_id[tx]]);  in fsl_sai_hw_free()
748 	bool tx = dir == TX;  in fsl_sai_config_disable()  local
756 	regmap_update_bits(sai->regmap, FSL_SAI_xCSR(tx, ofs),  in fsl_sai_config_disable()
762 		regmap_read(sai->regmap, FSL_SAI_xCSR(tx, ofs), &xcsr);  in fsl_sai_config_disable()
765 	regmap_update_bits(sai->regmap, FSL_SAI_xCSR(tx, ofs),  in fsl_sai_config_disable()
775 	if (!sai->is_consumer_mode[tx]) {  in fsl_sai_config_disable()
777 		regmap_write(sai->regmap, FSL_SAI_xCSR(tx, ofs), FSL_SAI_CSR_SR);  in fsl_sai_config_disable()
779 		regmap_write(sai->regmap, FSL_SAI_xCSR(tx, ofs), 0);  in fsl_sai_config_disable()
789 	bool tx = substream->stream == SNDRV_PCM_STREAM_PLAYBACK;  in fsl_sai_trigger()  local
790 	int adir = tx ? RX : TX;  in fsl_sai_trigger()
791 	int dir = tx ? TX : RX;  in fsl_sai_trigger()
795 	 * Asynchronous mode: Clear SYNC for both Tx and Rx.  in fsl_sai_trigger()
796 	 * Rx sync with Tx clocks: Clear SYNC for Tx, set it for Rx.  in fsl_sai_trigger()
797 	 * Tx sync with Rx clocks: Clear SYNC for Rx, set it for Tx.  in fsl_sai_trigger()
800 			   sai->synchronous[TX] ? FSL_SAI_CR2_SYNC : 0);  in fsl_sai_trigger()
812 		regmap_update_bits(sai->regmap, FSL_SAI_xCSR(tx, ofs),  in fsl_sai_trigger()
815 		regmap_update_bits(sai->regmap, FSL_SAI_xCSR(tx, ofs),  in fsl_sai_trigger()
819 		 * 1. Tx sync with Rx: only set RE for Rx; set TE & RE for Tx  in fsl_sai_trigger()
820 		 * 2. Rx sync with Tx: only set TE for Tx; set RE & TE for Rx  in fsl_sai_trigger()
829 			regmap_update_bits(sai->regmap, FSL_SAI_xCSR((!tx), ofs),  in fsl_sai_trigger()
832 		regmap_update_bits(sai->regmap, FSL_SAI_xCSR(tx, ofs),  in fsl_sai_trigger()
838 		regmap_update_bits(sai->regmap, FSL_SAI_xCSR(tx, ofs),  in fsl_sai_trigger()
840 		regmap_update_bits(sai->regmap, FSL_SAI_xCSR(tx, ofs),  in fsl_sai_trigger()
844 		regmap_read(sai->regmap, FSL_SAI_xCSR(!tx, ofs), &xcsr);  in fsl_sai_trigger()
874 	bool tx = substream->stream == SNDRV_PCM_STREAM_PLAYBACK;  in fsl_sai_startup()  local
879 	 * tx/rx maxburst  in fsl_sai_startup()
884 					   tx ? sai->dma_params_tx.maxburst :  in fsl_sai_startup()
898 	/* Software Reset for both Tx and Rx */  in fsl_sai_dai_probe()
973 		.name = "sai-tx-rx",
995 		.name = "sai-tx",
1282  * dataline mask for 'tx'. for example
1286  * It means I2S type rx mask is 0xff, tx mask is 0xff, PDM type
1287  * rx mask is 0xff, tx mask is 0x11 (dataline 1 and 4 enabled).
1300 	u32 rx, tx, type;  in fsl_sai_read_dlcfg()  local
1344 		ret = of_property_read_u32_index(np, propname, index++, &tx);  in fsl_sai_read_dlcfg()
1348 		if ((rx & ~soc_dl) || (tx & ~soc_dl)) {  in fsl_sai_read_dlcfg()
1354 		tx = tx & soc_dl;  in fsl_sai_read_dlcfg()
1363 		cfg[i].pins[1] = hweight8(tx);  in fsl_sai_read_dlcfg()
1364 		cfg[i].mask[1] = tx;  in fsl_sai_read_dlcfg()
1365 		dl_mask = tx;  in fsl_sai_read_dlcfg()
1367 		cfg[i].next_off[1] = fsl_sai_calc_dl_off(tx);  in fsl_sai_read_dlcfg()
1455 	/* read dataline mask for rx and tx*/  in fsl_sai_probe()
1476 	/* Sync Tx with Rx as default by following old DT binding */  in fsl_sai_probe()
1478 	sai->synchronous[TX] = false;  in fsl_sai_probe()
1491 		/* Sync Rx with Tx */  in fsl_sai_probe()
1493 		sai->synchronous[TX] = true;  in fsl_sai_probe()
1497 		sai->synchronous[TX] = false;  in fsl_sai_probe()
1526 		sai->soc_data->max_burst[TX] ? sai->soc_data->max_burst[TX] : FSL_SAI_MAXBURST_TX;  in fsl_sai_probe()