1 // SPDX-License-Identifier: GPL-2.0
5 // Copyright (C) 2014-2015 Freescale Semiconductor, Inc.
13 #include <linux/mfd/syscon/imx6q-iomuxc-gpr.h>
39  * struct fsl_mqs_soc_data - soc specific data
70 	struct clk *mclk;  member
86 	    mqs_priv->soc->ctrl_off == reg)  in fsl_mqs_sm_read()
87 		return scmi_imx_misc_ctrl_get(mqs_priv->soc->sm_index, &num, val);  in fsl_mqs_sm_read()
89 	return -EINVAL;  in fsl_mqs_sm_read()
97 	    mqs_priv->soc->ctrl_off == reg)  in fsl_mqs_sm_write()
98 		return scmi_imx_misc_ctrl_set(mqs_priv->soc->sm_index, val);  in fsl_mqs_sm_write()
100 	return -EINVAL;  in fsl_mqs_sm_write()
107 	struct snd_soc_component *component = dai->component;  in fsl_mqs_hw_params()
110 	int div, res;  in fsl_mqs_hw_params()  local
113 	mclk_rate = clk_get_rate(mqs_priv->mclk);  in fsl_mqs_hw_params()
121 	div = mclk_rate / (32 * lrclk * 2 * 8);  in fsl_mqs_hw_params()
124 	if (res == 0 && div > 0 && div <= 256) {  in fsl_mqs_hw_params()
125 		regmap_update_bits(mqs_priv->regmap, mqs_priv->soc->ctrl_off,  in fsl_mqs_hw_params()
126 				   mqs_priv->soc->div_mask,  in fsl_mqs_hw_params()
127 				   (div - 1) << mqs_priv->soc->div_shift);  in fsl_mqs_hw_params()
128 		regmap_update_bits(mqs_priv->regmap, mqs_priv->soc->ctrl_off,  in fsl_mqs_hw_params()
129 				   mqs_priv->soc->osr_mask, 0);  in fsl_mqs_hw_params()
131 		dev_err(component->dev, "can't get proper divider\n");  in fsl_mqs_hw_params()
144 		return -EINVAL;  in fsl_mqs_set_dai_fmt()
151 		return -EINVAL;  in fsl_mqs_set_dai_fmt()
158 		return -EINVAL;  in fsl_mqs_set_dai_fmt()
167 	struct snd_soc_component *component = dai->component;  in fsl_mqs_startup()
170 	regmap_update_bits(mqs_priv->regmap, mqs_priv->soc->ctrl_off,  in fsl_mqs_startup()
171 			   mqs_priv->soc->en_mask,  in fsl_mqs_startup()
172 			   1 << mqs_priv->soc->en_shift);  in fsl_mqs_startup()
179 	struct snd_soc_component *component = dai->component;  in fsl_mqs_shutdown()
182 	regmap_update_bits(mqs_priv->regmap, mqs_priv->soc->ctrl_off,  in fsl_mqs_shutdown()
183 			   mqs_priv->soc->en_mask, 0);  in fsl_mqs_shutdown()
198 	.name		= "fsl-mqs-dai",
226 	struct device_node *np = pdev->dev.of_node;  in fsl_mqs_probe()
232 	mqs_priv = devm_kzalloc(&pdev->dev, sizeof(*mqs_priv), GFP_KERNEL);  in fsl_mqs_probe()
234 		return -ENOMEM;  in fsl_mqs_probe()
240 	mqs_priv->soc = of_device_get_match_data(&pdev->dev);  in fsl_mqs_probe()
242 	if (mqs_priv->soc->type == TYPE_REG_GPR) {  in fsl_mqs_probe()
245 			dev_err(&pdev->dev, "failed to get gpr node by phandle\n");  in fsl_mqs_probe()
246 			return -EINVAL;  in fsl_mqs_probe()
249 		mqs_priv->regmap = syscon_node_to_regmap(gpr_np);  in fsl_mqs_probe()
251 		if (IS_ERR(mqs_priv->regmap)) {  in fsl_mqs_probe()
252 			dev_err(&pdev->dev, "failed to get gpr regmap\n");  in fsl_mqs_probe()
253 			return PTR_ERR(mqs_priv->regmap);  in fsl_mqs_probe()
255 	} else if (mqs_priv->soc->type == TYPE_REG_SM) {  in fsl_mqs_probe()
256 		mqs_priv->regmap = devm_regmap_init(&pdev->dev,  in fsl_mqs_probe()
260 		if (IS_ERR(mqs_priv->regmap)) {  in fsl_mqs_probe()
261 			dev_err(&pdev->dev, "failed to init regmap: %ld\n",  in fsl_mqs_probe()
262 				PTR_ERR(mqs_priv->regmap));  in fsl_mqs_probe()
263 			return PTR_ERR(mqs_priv->regmap);  in fsl_mqs_probe()
270 		mqs_priv->regmap = devm_regmap_init_mmio_clk(&pdev->dev,  in fsl_mqs_probe()
274 		if (IS_ERR(mqs_priv->regmap)) {  in fsl_mqs_probe()
275 			dev_err(&pdev->dev, "failed to init regmap: %ld\n",  in fsl_mqs_probe()
276 				PTR_ERR(mqs_priv->regmap));  in fsl_mqs_probe()
277 			return PTR_ERR(mqs_priv->regmap);  in fsl_mqs_probe()
280 		mqs_priv->ipg = devm_clk_get(&pdev->dev, "core");  in fsl_mqs_probe()
281 		if (IS_ERR(mqs_priv->ipg)) {  in fsl_mqs_probe()
282 			dev_err(&pdev->dev, "failed to get the clock: %ld\n",  in fsl_mqs_probe()
283 				PTR_ERR(mqs_priv->ipg));  in fsl_mqs_probe()
284 			return PTR_ERR(mqs_priv->ipg);  in fsl_mqs_probe()
288 	mqs_priv->mclk = devm_clk_get(&pdev->dev, "mclk");  in fsl_mqs_probe()
289 	if (IS_ERR(mqs_priv->mclk)) {  in fsl_mqs_probe()
290 		dev_err(&pdev->dev, "failed to get the clock: %ld\n",  in fsl_mqs_probe()
291 			PTR_ERR(mqs_priv->mclk));  in fsl_mqs_probe()
292 		return PTR_ERR(mqs_priv->mclk);  in fsl_mqs_probe()
295 	dev_set_drvdata(&pdev->dev, mqs_priv);  in fsl_mqs_probe()
296 	pm_runtime_enable(&pdev->dev);  in fsl_mqs_probe()
298 	ret = devm_snd_soc_register_component(&pdev->dev, &soc_codec_fsl_mqs,  in fsl_mqs_probe()
308 	pm_runtime_disable(&pdev->dev);  in fsl_mqs_remove()
316 	ret = clk_prepare_enable(mqs_priv->ipg);  in fsl_mqs_runtime_resume()
322 	ret = clk_prepare_enable(mqs_priv->mclk);  in fsl_mqs_runtime_resume()
324 		dev_err(dev, "failed to enable mclk clock\n");  in fsl_mqs_runtime_resume()
325 		clk_disable_unprepare(mqs_priv->ipg);  in fsl_mqs_runtime_resume()
329 	regmap_write(mqs_priv->regmap, mqs_priv->soc->ctrl_off, mqs_priv->reg_mqs_ctrl);  in fsl_mqs_runtime_resume()
337 	regmap_read(mqs_priv->regmap, mqs_priv->soc->ctrl_off, &mqs_priv->reg_mqs_ctrl);  in fsl_mqs_runtime_suspend()
339 	clk_disable_unprepare(mqs_priv->mclk);  in fsl_mqs_runtime_suspend()
340 	clk_disable_unprepare(mqs_priv->ipg);  in fsl_mqs_runtime_suspend()
445 	{ .compatible = "fsl,imx8qm-mqs", .data = &fsl_mqs_imx8qm_data },
446 	{ .compatible = "fsl,imx6sx-mqs", .data = &fsl_mqs_imx6sx_data },
447 	{ .compatible = "fsl,imx93-mqs", .data = &fsl_mqs_imx93_data },
448 	{ .compatible = "fsl,imx95-aonmix-mqs", .data = &fsl_mqs_imx95_aon_data },
449 	{ .compatible = "fsl,imx95-netcmix-mqs", .data = &fsl_mqs_imx95_netc_data },
450 	{ .compatible = "fsl,imx943-aonmix-mqs", .data = &fsl_mqs_imx943_aon_data },
451 	{ .compatible = "fsl,imx943-wakeupmix-mqs", .data = &fsl_mqs_imx943_wakeup_data },
460 		.name	= "fsl-mqs",
471 MODULE_ALIAS("platform:fsl-mqs");