1 // SPDX-License-Identifier: GPL-2.0
17 #include "imx-pcm.h"
25  * struct fsl_esai_soc_data - soc specific data
33  * struct fsl_esai - ESAI private data
45  * @fifo_depth: depth of tx/rx FIFO
48  * @tx_mask: slot mask for TX
50  * @channels: channel num for tx or rx
56  * @synchronous: if using tx/rx synchronous mode
101 	struct platform_device *pdev = esai_priv->pdev;  in esai_isr()
105 	regmap_read(esai_priv->regmap, REG_ESAI_ESR, &esr);  in esai_isr()
106 	regmap_read(esai_priv->regmap, REG_ESAI_SAISR, &saisr);  in esai_isr()
109 	    esai_priv->soc->reset_at_xrun) {  in esai_isr()
110 		dev_dbg(&pdev->dev, "reset module for xrun\n");  in esai_isr()
111 		regmap_update_bits(esai_priv->regmap, REG_ESAI_TCR,  in esai_isr()
113 		regmap_update_bits(esai_priv->regmap, REG_ESAI_RCR,  in esai_isr()
115 		schedule_work(&esai_priv->work);  in esai_isr()
119 		dev_dbg(&pdev->dev, "isr: Transmission Initialized\n");  in esai_isr()
122 		dev_dbg(&pdev->dev, "isr: Receiving overrun\n");  in esai_isr()
125 		dev_dbg(&pdev->dev, "isr: Transmission underrun\n");  in esai_isr()
128 		dev_dbg(&pdev->dev, "isr: Just transmitted the last slot\n");  in esai_isr()
131 		dev_dbg(&pdev->dev, "isr: Transmission data exception\n");  in esai_isr()
134 		dev_dbg(&pdev->dev, "isr: Transmitting even slots\n");  in esai_isr()
137 		dev_dbg(&pdev->dev, "isr: Transmitting data\n");  in esai_isr()
140 		dev_dbg(&pdev->dev, "isr: Just received the last slot\n");  in esai_isr()
143 		dev_dbg(&pdev->dev, "isr: Receiving data exception\n");  in esai_isr()
146 		dev_dbg(&pdev->dev, "isr: Receiving even slots\n");  in esai_isr()
149 		dev_dbg(&pdev->dev, "isr: Receiving data\n");  in esai_isr()
155  * fsl_esai_divisor_cal - This function is used to calculate the
160  * @tx: current setting is for playback or capture
165 static int fsl_esai_divisor_cal(struct snd_soc_dai *dai, bool tx, u32 ratio,  in fsl_esai_divisor_cal()  argument
177 		dev_err(dai->dev, "the ratio is out of range (2 ~ %d)\n",  in fsl_esai_divisor_cal()
179 		return -EINVAL;  in fsl_esai_divisor_cal()
181 		dev_err(dai->dev, "the raio must be even if using upper divider\n");  in fsl_esai_divisor_cal()
182 		return -EINVAL;  in fsl_esai_divisor_cal()
189 	/* Do not loop-search if PM (1 ~ 256) alone can serve the ratio */  in fsl_esai_divisor_cal()
196 	/* Set the max fluctuation -- 0.1% of the max devisor */  in fsl_esai_divisor_cal()
208 				sub = prod - ratio;  in fsl_esai_divisor_cal()
210 				sub = ratio - prod;  in fsl_esai_divisor_cal()
229 		dev_err(dai->dev, "failed to calculate proper divisors\n");  in fsl_esai_divisor_cal()
230 		return -EINVAL;  in fsl_esai_divisor_cal()
234 	regmap_update_bits(esai_priv->regmap, REG_ESAI_xCCR(tx),  in fsl_esai_divisor_cal()
243 	regmap_update_bits(esai_priv->regmap, REG_ESAI_xCCR(tx),  in fsl_esai_divisor_cal()
250  * fsl_esai_set_dai_sysclk - configure the clock frequency of MCLK (HCKT/HCKR)
254  * @freq: The required clock rate of HCKT/HCKR
260 				   unsigned int freq, int dir)  in fsl_esai_set_dai_sysclk()  argument
263 	struct clk *clksrc = esai_priv->extalclk;  in fsl_esai_set_dai_sysclk()
264 	bool tx = (clk_id <= ESAI_HCKT_EXTAL || esai_priv->synchronous);  in fsl_esai_set_dai_sysclk()  local
270 	if (freq == 0) {  in fsl_esai_set_dai_sysclk()
271 		dev_err(dai->dev, "%sput freq of HCK%c should not be 0Hz\n",  in fsl_esai_set_dai_sysclk()
272 			in ? "in" : "out", tx ? 'T' : 'R');  in fsl_esai_set_dai_sysclk()
273 		return -EINVAL;  in fsl_esai_set_dai_sysclk()
277 	if (freq == esai_priv->hck_rate[tx] && dir == esai_priv->hck_dir[tx])  in fsl_esai_set_dai_sysclk()
281 	esai_priv->sck_div[tx] = true;  in fsl_esai_set_dai_sysclk()
284 	regmap_update_bits(esai_priv->regmap, REG_ESAI_xCCR(tx),  in fsl_esai_set_dai_sysclk()
293 		clksrc = esai_priv->fsysclk;  in fsl_esai_set_dai_sysclk()
299 		ecr |= esai_priv->synchronous ? ESAI_ECR_ETI : ESAI_ECR_ERI;  in fsl_esai_set_dai_sysclk()
302 		return -EINVAL;  in fsl_esai_set_dai_sysclk()
306 		dev_err(dai->dev, "no assigned %s clock\n",  in fsl_esai_set_dai_sysclk()
312 	ratio = clk_rate / freq;  in fsl_esai_set_dai_sysclk()
313 	if (ratio * freq > clk_rate)  in fsl_esai_set_dai_sysclk()
314 		ret = ratio * freq - clk_rate;  in fsl_esai_set_dai_sysclk()
315 	else if (ratio * freq < clk_rate)  in fsl_esai_set_dai_sysclk()
316 		ret = clk_rate - ratio * freq;  in fsl_esai_set_dai_sysclk()
322 		dev_err(dai->dev, "failed to derive required HCK%c rate\n",  in fsl_esai_set_dai_sysclk()
323 				tx ? 'T' : 'R');  in fsl_esai_set_dai_sysclk()
324 		return -EINVAL;  in fsl_esai_set_dai_sysclk()
328 	if (ratio == 1 && clksrc == esai_priv->extalclk) {  in fsl_esai_set_dai_sysclk()
330 		ecr |= tx ? ESAI_ECR_ETO : ESAI_ECR_ERO;  in fsl_esai_set_dai_sysclk()
334 		dev_err(dai->dev, "failed to derive required HCK%c rate\n",  in fsl_esai_set_dai_sysclk()
335 				tx ? 'T' : 'R');  in fsl_esai_set_dai_sysclk()
336 		return -EINVAL;  in fsl_esai_set_dai_sysclk()
339 	ret = fsl_esai_divisor_cal(dai, tx, ratio, false, 0);  in fsl_esai_set_dai_sysclk()
343 	esai_priv->sck_div[tx] = false;  in fsl_esai_set_dai_sysclk()
346 	esai_priv->hck_dir[tx] = dir;  in fsl_esai_set_dai_sysclk()
347 	esai_priv->hck_rate[tx] = freq;  in fsl_esai_set_dai_sysclk()
349 	regmap_update_bits(esai_priv->regmap, REG_ESAI_ECR,  in fsl_esai_set_dai_sysclk()
350 			   tx ? ESAI_ECR_ETI | ESAI_ECR_ETO :  in fsl_esai_set_dai_sysclk()
357  * fsl_esai_set_bclk - configure the related dividers according to the bclk rate
359  * @tx: direction boolean
360  * @freq: bclk freq
362 static int fsl_esai_set_bclk(struct snd_soc_dai *dai, bool tx, u32 freq)  in fsl_esai_set_bclk()  argument
365 	u32 hck_rate = esai_priv->hck_rate[tx];  in fsl_esai_set_bclk()
366 	u32 sub, ratio = hck_rate / freq;  in fsl_esai_set_bclk()
370 	if (esai_priv->consumer_mode || esai_priv->sck_rate[tx] == freq)  in fsl_esai_set_bclk()
373 	if (ratio * freq > hck_rate)  in fsl_esai_set_bclk()
374 		sub = ratio * freq - hck_rate;  in fsl_esai_set_bclk()
375 	else if (ratio * freq < hck_rate)  in fsl_esai_set_bclk()
376 		sub = hck_rate - ratio * freq;  in fsl_esai_set_bclk()
382 		dev_err(dai->dev, "failed to derive required SCK%c rate\n",  in fsl_esai_set_bclk()
383 				tx ? 'T' : 'R');  in fsl_esai_set_bclk()
384 		return -EINVAL;  in fsl_esai_set_bclk()
388 	if (!esai_priv->sck_div[tx] && (ratio > 16 || ratio == 0)) {  in fsl_esai_set_bclk()
389 		dev_err(dai->dev, "the ratio is out of range (1 ~ 16)\n");  in fsl_esai_set_bclk()
390 		return -EINVAL;  in fsl_esai_set_bclk()
393 	ret = fsl_esai_divisor_cal(dai, tx, ratio, true,  in fsl_esai_set_bclk()
394 			esai_priv->sck_div[tx] ? 0 : ratio);  in fsl_esai_set_bclk()
399 	esai_priv->sck_rate[tx] = freq;  in fsl_esai_set_bclk()
409 	regmap_update_bits(esai_priv->regmap, REG_ESAI_TCCR,  in fsl_esai_set_dai_tdm_slot()
412 	regmap_update_bits(esai_priv->regmap, REG_ESAI_RCCR,  in fsl_esai_set_dai_tdm_slot()
415 	esai_priv->slot_width = slot_width;  in fsl_esai_set_dai_tdm_slot()
416 	esai_priv->slots = slots;  in fsl_esai_set_dai_tdm_slot()
417 	esai_priv->tx_mask = tx_mask;  in fsl_esai_set_dai_tdm_slot()
418 	esai_priv->rx_mask = rx_mask;  in fsl_esai_set_dai_tdm_slot()
455 		return -EINVAL;  in fsl_esai_set_dai_fmt()
476 		return -EINVAL;  in fsl_esai_set_dai_fmt()
479 	esai_priv->consumer_mode = false;  in fsl_esai_set_dai_fmt()
484 		esai_priv->consumer_mode = true;  in fsl_esai_set_dai_fmt()
496 		return -EINVAL;  in fsl_esai_set_dai_fmt()
500 	regmap_update_bits(esai_priv->regmap, REG_ESAI_TCR, mask, xcr);  in fsl_esai_set_dai_fmt()
501 	regmap_update_bits(esai_priv->regmap, REG_ESAI_RCR, mask, xcr);  in fsl_esai_set_dai_fmt()
505 	regmap_update_bits(esai_priv->regmap, REG_ESAI_TCCR, mask, xccr);  in fsl_esai_set_dai_fmt()
506 	regmap_update_bits(esai_priv->regmap, REG_ESAI_RCCR, mask, xccr);  in fsl_esai_set_dai_fmt()
518 		regmap_update_bits(esai_priv->regmap, REG_ESAI_SAICR,  in fsl_esai_startup()
519 				   ESAI_SAICR_SYNC, esai_priv->synchronous ?  in fsl_esai_startup()
523 		regmap_update_bits(esai_priv->regmap, REG_ESAI_TCCR,  in fsl_esai_startup()
525 				   ESAI_xCCR_xDC(esai_priv->slots));  in fsl_esai_startup()
526 		regmap_update_bits(esai_priv->regmap, REG_ESAI_RCCR,  in fsl_esai_startup()
528 				   ESAI_xCCR_xDC(esai_priv->slots));  in fsl_esai_startup()
540 	bool tx = substream->stream == SNDRV_PCM_STREAM_PLAYBACK;  in fsl_esai_hw_params()  local
543 	u32 pins = DIV_ROUND_UP(channels, esai_priv->slots);  in fsl_esai_hw_params()
549 	if (esai_priv->slot_width)  in fsl_esai_hw_params()
550 		slot_width = esai_priv->slot_width;  in fsl_esai_hw_params()
552 	bclk = params_rate(params) * slot_width * esai_priv->slots;  in fsl_esai_hw_params()
554 	ret = fsl_esai_set_bclk(dai, esai_priv->synchronous || tx, bclk);  in fsl_esai_hw_params()
561 	regmap_update_bits(esai_priv->regmap, REG_ESAI_xCR(tx), mask, val);  in fsl_esai_hw_params()
563 	if (!tx && esai_priv->synchronous)  in fsl_esai_hw_params()
564 		regmap_update_bits(esai_priv->regmap, REG_ESAI_TCR, mask, val);  in fsl_esai_hw_params()
567 	regmap_update_bits(esai_priv->regmap, REG_ESAI_xCR(tx),  in fsl_esai_hw_params()
571 	regmap_update_bits(esai_priv->regmap, REG_ESAI_xFCR(tx),  in fsl_esai_hw_params()
575 	      (tx ? ESAI_xFCR_TE_MASK | ESAI_xFCR_TIEN : ESAI_xFCR_RE_MASK);  in fsl_esai_hw_params()
576 	val = ESAI_xFCR_xWA(width) | ESAI_xFCR_xFWM(esai_priv->fifo_depth) |  in fsl_esai_hw_params()
577 	     (tx ? ESAI_xFCR_TE(pins) | ESAI_xFCR_TIEN : ESAI_xFCR_RE(pins));  in fsl_esai_hw_params()
579 	regmap_update_bits(esai_priv->regmap, REG_ESAI_xFCR(tx), mask, val);  in fsl_esai_hw_params()
581 	if (tx)  in fsl_esai_hw_params()
582 		regmap_update_bits(esai_priv->regmap, REG_ESAI_TCR,  in fsl_esai_hw_params()
586 	regmap_update_bits(esai_priv->regmap, REG_ESAI_PRRC,  in fsl_esai_hw_params()
588 	regmap_update_bits(esai_priv->regmap, REG_ESAI_PCRC,  in fsl_esai_hw_params()
595 	struct platform_device *pdev = esai_priv->pdev;  in fsl_esai_hw_init()
599 	ret = regmap_update_bits(esai_priv->regmap, REG_ESAI_ECR,  in fsl_esai_hw_init()
603 		dev_err(&pdev->dev, "failed to reset ESAI: %d\n", ret);  in fsl_esai_hw_init()
611 	ret = regmap_update_bits(esai_priv->regmap, REG_ESAI_ECR,  in fsl_esai_hw_init()
615 		dev_err(&pdev->dev, "failed to enable ESAI: %d\n", ret);  in fsl_esai_hw_init()
619 	regmap_update_bits(esai_priv->regmap, REG_ESAI_PRRC,  in fsl_esai_hw_init()
621 	regmap_update_bits(esai_priv->regmap, REG_ESAI_PCRC,  in fsl_esai_hw_init()
632 	regmap_update_bits(esai_priv->regmap, REG_ESAI_TFCR,  in fsl_esai_register_restore()
634 	regmap_update_bits(esai_priv->regmap, REG_ESAI_RFCR,  in fsl_esai_register_restore()
637 	regcache_mark_dirty(esai_priv->regmap);  in fsl_esai_register_restore()
638 	ret = regcache_sync(esai_priv->regmap);  in fsl_esai_register_restore()
643 	regmap_update_bits(esai_priv->regmap, REG_ESAI_TFCR, ESAI_xFCR_xFR, 0);  in fsl_esai_register_restore()
644 	regmap_update_bits(esai_priv->regmap, REG_ESAI_RFCR, ESAI_xFCR_xFR, 0);  in fsl_esai_register_restore()
649 static void fsl_esai_trigger_start(struct fsl_esai *esai_priv, bool tx)  in fsl_esai_trigger_start()  argument
651 	u8 i, channels = esai_priv->channels[tx];  in fsl_esai_trigger_start()
652 	u32 pins = DIV_ROUND_UP(channels, esai_priv->slots);  in fsl_esai_trigger_start()
655 	regmap_update_bits(esai_priv->regmap, REG_ESAI_xFCR(tx),  in fsl_esai_trigger_start()
659 	for (i = 0; tx && i < channels; i++)  in fsl_esai_trigger_start()
660 		regmap_write(esai_priv->regmap, REG_ESAI_ETDR, 0x0);  in fsl_esai_trigger_start()
674 	regmap_update_bits(esai_priv->regmap, REG_ESAI_xCR(tx),  in fsl_esai_trigger_start()
675 			   tx ? ESAI_xCR_TE_MASK : ESAI_xCR_RE_MASK,  in fsl_esai_trigger_start()
676 			   tx ? ESAI_xCR_TE(pins) : ESAI_xCR_RE(pins));  in fsl_esai_trigger_start()
677 	mask = tx ? esai_priv->tx_mask : esai_priv->rx_mask;  in fsl_esai_trigger_start()
679 	regmap_update_bits(esai_priv->regmap, REG_ESAI_xSMB(tx),  in fsl_esai_trigger_start()
681 	regmap_update_bits(esai_priv->regmap, REG_ESAI_xSMA(tx),  in fsl_esai_trigger_start()
685 	regmap_update_bits(esai_priv->regmap, REG_ESAI_xCR(tx),  in fsl_esai_trigger_start()
689 static void fsl_esai_trigger_stop(struct fsl_esai *esai_priv, bool tx)  in fsl_esai_trigger_stop()  argument
691 	regmap_update_bits(esai_priv->regmap, REG_ESAI_xCR(tx),  in fsl_esai_trigger_stop()
694 	regmap_update_bits(esai_priv->regmap, REG_ESAI_xCR(tx),  in fsl_esai_trigger_stop()
695 			   tx ? ESAI_xCR_TE_MASK : ESAI_xCR_RE_MASK, 0);  in fsl_esai_trigger_stop()
696 	regmap_update_bits(esai_priv->regmap, REG_ESAI_xSMA(tx),  in fsl_esai_trigger_stop()
698 	regmap_update_bits(esai_priv->regmap, REG_ESAI_xSMB(tx),  in fsl_esai_trigger_stop()
702 	regmap_update_bits(esai_priv->regmap, REG_ESAI_xFCR(tx),  in fsl_esai_trigger_stop()
704 	regmap_update_bits(esai_priv->regmap, REG_ESAI_xFCR(tx),  in fsl_esai_trigger_stop()
711 	bool tx = true, rx = false, enabled[2];  in fsl_esai_hw_reset()  local
715 	spin_lock_irqsave(&esai_priv->lock, lock_flags);  in fsl_esai_hw_reset()
717 	regmap_read(esai_priv->regmap, REG_ESAI_TFCR, &tfcr);  in fsl_esai_hw_reset()
718 	regmap_read(esai_priv->regmap, REG_ESAI_RFCR, &rfcr);  in fsl_esai_hw_reset()
719 	enabled[tx] = tfcr & ESAI_xFCR_xFEN;  in fsl_esai_hw_reset()
722 	/* Stop the tx & rx */  in fsl_esai_hw_reset()
723 	fsl_esai_trigger_stop(esai_priv, tx);  in fsl_esai_hw_reset()
729 	/* Enforce ESAI personal resets for both TX and RX */  in fsl_esai_hw_reset()
730 	regmap_update_bits(esai_priv->regmap, REG_ESAI_TCR,  in fsl_esai_hw_reset()
732 	regmap_update_bits(esai_priv->regmap, REG_ESAI_RCR,  in fsl_esai_hw_reset()
739 	regmap_update_bits(esai_priv->regmap, REG_ESAI_TCR,  in fsl_esai_hw_reset()
741 	regmap_update_bits(esai_priv->regmap, REG_ESAI_RCR,  in fsl_esai_hw_reset()
743 	regmap_update_bits(esai_priv->regmap, REG_ESAI_PRRC,  in fsl_esai_hw_reset()
745 	regmap_update_bits(esai_priv->regmap, REG_ESAI_PCRC,  in fsl_esai_hw_reset()
748 	/* Restart tx / rx, if they already enabled */  in fsl_esai_hw_reset()
749 	if (enabled[tx])  in fsl_esai_hw_reset()
750 		fsl_esai_trigger_start(esai_priv, tx);  in fsl_esai_hw_reset()
754 	spin_unlock_irqrestore(&esai_priv->lock, lock_flags);  in fsl_esai_hw_reset()
761 	bool tx = substream->stream == SNDRV_PCM_STREAM_PLAYBACK;  in fsl_esai_trigger()  local
764 	esai_priv->channels[tx] = substream->runtime->channels;  in fsl_esai_trigger()
770 		spin_lock_irqsave(&esai_priv->lock, lock_flags);  in fsl_esai_trigger()
771 		fsl_esai_trigger_start(esai_priv, tx);  in fsl_esai_trigger()
772 		spin_unlock_irqrestore(&esai_priv->lock, lock_flags);  in fsl_esai_trigger()
777 		spin_lock_irqsave(&esai_priv->lock, lock_flags);  in fsl_esai_trigger()
778 		fsl_esai_trigger_stop(esai_priv, tx);  in fsl_esai_trigger()
779 		spin_unlock_irqrestore(&esai_priv->lock, lock_flags);  in fsl_esai_trigger()
782 		return -EINVAL;  in fsl_esai_trigger()
792 	snd_soc_dai_init_dma_data(dai, &esai_priv->dma_params_tx,  in fsl_esai_dai_probe()
793 				  &esai_priv->dma_params_rx);  in fsl_esai_dai_probe()
810 		.stream_name = "CPU-Playback",
817 		.stream_name = "CPU-Capture",
827 	.name			= "fsl-esai",
956 	struct device_node *np = pdev->dev.of_node;  in fsl_esai_probe()
963 	esai_priv = devm_kzalloc(&pdev->dev, sizeof(*esai_priv), GFP_KERNEL);  in fsl_esai_probe()
965 		return -ENOMEM;  in fsl_esai_probe()
967 	esai_priv->pdev = pdev;  in fsl_esai_probe()
968 	snprintf(esai_priv->name, sizeof(esai_priv->name), "%pOFn", np);  in fsl_esai_probe()
970 	esai_priv->soc = of_device_get_match_data(&pdev->dev);  in fsl_esai_probe()
977 	esai_priv->regmap = devm_regmap_init_mmio(&pdev->dev, regs, &fsl_esai_regmap_config);  in fsl_esai_probe()
978 	if (IS_ERR(esai_priv->regmap)) {  in fsl_esai_probe()
979 		dev_err(&pdev->dev, "failed to init regmap: %ld\n",  in fsl_esai_probe()
980 				PTR_ERR(esai_priv->regmap));  in fsl_esai_probe()
981 		return PTR_ERR(esai_priv->regmap);  in fsl_esai_probe()
984 	esai_priv->coreclk = devm_clk_get(&pdev->dev, "core");  in fsl_esai_probe()
985 	if (IS_ERR(esai_priv->coreclk)) {  in fsl_esai_probe()
986 		dev_err(&pdev->dev, "failed to get core clock: %ld\n",  in fsl_esai_probe()
987 				PTR_ERR(esai_priv->coreclk));  in fsl_esai_probe()
988 		return PTR_ERR(esai_priv->coreclk);  in fsl_esai_probe()
991 	esai_priv->extalclk = devm_clk_get(&pdev->dev, "extal");  in fsl_esai_probe()
992 	if (IS_ERR(esai_priv->extalclk))  in fsl_esai_probe()
993 		dev_warn(&pdev->dev, "failed to get extal clock: %ld\n",  in fsl_esai_probe()
994 				PTR_ERR(esai_priv->extalclk));  in fsl_esai_probe()
996 	esai_priv->fsysclk = devm_clk_get(&pdev->dev, "fsys");  in fsl_esai_probe()
997 	if (IS_ERR(esai_priv->fsysclk))  in fsl_esai_probe()
998 		dev_warn(&pdev->dev, "failed to get fsys clock: %ld\n",  in fsl_esai_probe()
999 				PTR_ERR(esai_priv->fsysclk));  in fsl_esai_probe()
1001 	esai_priv->spbaclk = devm_clk_get(&pdev->dev, "spba");  in fsl_esai_probe()
1002 	if (IS_ERR(esai_priv->spbaclk))  in fsl_esai_probe()
1003 		dev_warn(&pdev->dev, "failed to get spba clock: %ld\n",  in fsl_esai_probe()
1004 				PTR_ERR(esai_priv->spbaclk));  in fsl_esai_probe()
1010 	ret = devm_request_irq(&pdev->dev, irq, esai_isr, IRQF_SHARED,  in fsl_esai_probe()
1011 			       esai_priv->name, esai_priv);  in fsl_esai_probe()
1013 		dev_err(&pdev->dev, "failed to claim irq %u\n", irq);  in fsl_esai_probe()
1018 	esai_priv->slots = 2;  in fsl_esai_probe()
1021 	esai_priv->consumer_mode = true;  in fsl_esai_probe()
1024 	iprop = of_get_property(np, "fsl,fifo-depth", NULL);  in fsl_esai_probe()
1026 		esai_priv->fifo_depth = be32_to_cpup(iprop);  in fsl_esai_probe()
1028 		esai_priv->fifo_depth = 64;  in fsl_esai_probe()
1030 	esai_priv->dma_params_tx.maxburst = 16;  in fsl_esai_probe()
1031 	esai_priv->dma_params_rx.maxburst = 16;  in fsl_esai_probe()
1032 	esai_priv->dma_params_tx.addr = res->start + REG_ESAI_ETDR;  in fsl_esai_probe()
1033 	esai_priv->dma_params_rx.addr = res->start + REG_ESAI_ERDR;  in fsl_esai_probe()
1035 	esai_priv->synchronous =  in fsl_esai_probe()
1036 		of_property_read_bool(np, "fsl,esai-synchronous");  in fsl_esai_probe()
1039 	if (esai_priv->synchronous) {  in fsl_esai_probe()
1045 	dev_set_drvdata(&pdev->dev, esai_priv);  in fsl_esai_probe()
1046 	spin_lock_init(&esai_priv->lock);  in fsl_esai_probe()
1047 	pm_runtime_enable(&pdev->dev);  in fsl_esai_probe()
1048 	if (!pm_runtime_enabled(&pdev->dev)) {  in fsl_esai_probe()
1049 		ret = fsl_esai_runtime_resume(&pdev->dev);  in fsl_esai_probe()
1054 	ret = pm_runtime_resume_and_get(&pdev->dev);  in fsl_esai_probe()
1062 	esai_priv->tx_mask = 0xFFFFFFFF;  in fsl_esai_probe()
1063 	esai_priv->rx_mask = 0xFFFFFFFF;  in fsl_esai_probe()
1066 	regmap_write(esai_priv->regmap, REG_ESAI_TSMA, 0);  in fsl_esai_probe()
1067 	regmap_write(esai_priv->regmap, REG_ESAI_TSMB, 0);  in fsl_esai_probe()
1068 	regmap_write(esai_priv->regmap, REG_ESAI_RSMA, 0);  in fsl_esai_probe()
1069 	regmap_write(esai_priv->regmap, REG_ESAI_RSMB, 0);  in fsl_esai_probe()
1071 	ret = pm_runtime_put_sync(&pdev->dev);  in fsl_esai_probe()
1072 	if (ret < 0 && ret != -ENOSYS)  in fsl_esai_probe()
1081 		dev_err(&pdev->dev, "failed to init imx pcm dma: %d\n", ret);  in fsl_esai_probe()
1085 	ret = devm_snd_soc_register_component(&pdev->dev, &fsl_esai_component,  in fsl_esai_probe()
1088 		dev_err(&pdev->dev, "failed to register DAI: %d\n", ret);  in fsl_esai_probe()
1092 	INIT_WORK(&esai_priv->work, fsl_esai_hw_reset);  in fsl_esai_probe()
1097 	if (!pm_runtime_status_suspended(&pdev->dev))  in fsl_esai_probe()
1098 		fsl_esai_runtime_suspend(&pdev->dev);  in fsl_esai_probe()
1100 	pm_runtime_disable(&pdev->dev);  in fsl_esai_probe()
1108 	pm_runtime_disable(&pdev->dev);  in fsl_esai_remove()
1109 	if (!pm_runtime_status_suspended(&pdev->dev))  in fsl_esai_remove()
1110 		fsl_esai_runtime_suspend(&pdev->dev);  in fsl_esai_remove()
1112 	cancel_work_sync(&esai_priv->work);  in fsl_esai_remove()
1116 	{ .compatible = "fsl,imx35-esai", .data = &fsl_esai_imx35 },
1117 	{ .compatible = "fsl,vf610-esai", .data = &fsl_esai_vf610 },
1118 	{ .compatible = "fsl,imx6ull-esai", .data = &fsl_esai_imx6ull },
1132 	ret = clk_prepare_enable(esai->coreclk);  in fsl_esai_runtime_resume()
1135 	if (!IS_ERR(esai->spbaclk)) {  in fsl_esai_runtime_resume()
1136 		ret = clk_prepare_enable(esai->spbaclk);  in fsl_esai_runtime_resume()
1140 	if (!IS_ERR(esai->extalclk)) {  in fsl_esai_runtime_resume()
1141 		ret = clk_prepare_enable(esai->extalclk);  in fsl_esai_runtime_resume()
1145 	if (!IS_ERR(esai->fsysclk)) {  in fsl_esai_runtime_resume()
1146 		ret = clk_prepare_enable(esai->fsysclk);  in fsl_esai_runtime_resume()
1151 	regcache_cache_only(esai->regmap, false);  in fsl_esai_runtime_resume()
1160 	if (!IS_ERR(esai->fsysclk))  in fsl_esai_runtime_resume()
1161 		clk_disable_unprepare(esai->fsysclk);  in fsl_esai_runtime_resume()
1163 	if (!IS_ERR(esai->extalclk))  in fsl_esai_runtime_resume()
1164 		clk_disable_unprepare(esai->extalclk);  in fsl_esai_runtime_resume()
1166 	if (!IS_ERR(esai->spbaclk))  in fsl_esai_runtime_resume()
1167 		clk_disable_unprepare(esai->spbaclk);  in fsl_esai_runtime_resume()
1169 	clk_disable_unprepare(esai->coreclk);  in fsl_esai_runtime_resume()
1178 	regcache_cache_only(esai->regmap, true);  in fsl_esai_runtime_suspend()
1180 	if (!IS_ERR(esai->fsysclk))  in fsl_esai_runtime_suspend()
1181 		clk_disable_unprepare(esai->fsysclk);  in fsl_esai_runtime_suspend()
1182 	if (!IS_ERR(esai->extalclk))  in fsl_esai_runtime_suspend()
1183 		clk_disable_unprepare(esai->extalclk);  in fsl_esai_runtime_suspend()
1184 	if (!IS_ERR(esai->spbaclk))  in fsl_esai_runtime_suspend()
1185 		clk_disable_unprepare(esai->spbaclk);  in fsl_esai_runtime_suspend()
1186 	clk_disable_unprepare(esai->coreclk);  in fsl_esai_runtime_suspend()
1203 		.name = "fsl-esai-dai",
1214 MODULE_ALIAS("platform:fsl-esai-dai");