Lines Matching +full:easrc +full:- +full:imx8mn
1 // SPDX-License-Identifier: GPL-2.0
7 #include <linux/dma-mapping.h>
32 #include "imx-pcm.h"
50 struct fsl_asrc *easrc = snd_soc_component_get_drvdata(comp); in fsl_easrc_iec958_put_bits() local
51 struct fsl_easrc_priv *easrc_priv = easrc->private; in fsl_easrc_iec958_put_bits()
53 (struct soc_mreg_control *)kcontrol->private_value; in fsl_easrc_iec958_put_bits()
54 unsigned int regval = ucontrol->value.integer.value[0]; in fsl_easrc_iec958_put_bits()
56 easrc_priv->bps_iec958[mc->regbase] = regval; in fsl_easrc_iec958_put_bits()
65 struct fsl_asrc *easrc = snd_soc_component_get_drvdata(comp); in fsl_easrc_iec958_get_bits() local
66 struct fsl_easrc_priv *easrc_priv = easrc->private; in fsl_easrc_iec958_get_bits()
68 (struct soc_mreg_control *)kcontrol->private_value; in fsl_easrc_iec958_get_bits()
70 ucontrol->value.enumerated.item[0] = easrc_priv->bps_iec958[mc->regbase]; in fsl_easrc_iec958_get_bits()
80 (struct soc_mreg_control *)kcontrol->private_value; in fsl_easrc_get_reg()
83 regval = snd_soc_component_read(component, mc->regbase); in fsl_easrc_get_reg()
85 ucontrol->value.integer.value[0] = regval; in fsl_easrc_get_reg()
95 (struct soc_mreg_control *)kcontrol->private_value; in fsl_easrc_set_reg()
96 unsigned int regval = ucontrol->value.integer.value[0]; in fsl_easrc_set_reg()
99 ret = snd_soc_component_write(component, mc->regbase, regval); in fsl_easrc_set_reg()
174 struct fsl_asrc *easrc = ctx->asrc; in fsl_easrc_set_rs_ratio() local
175 struct fsl_easrc_priv *easrc_priv = easrc->private; in fsl_easrc_set_rs_ratio()
176 struct fsl_easrc_ctx_priv *ctx_priv = ctx->private; in fsl_easrc_set_rs_ratio()
177 unsigned int in_rate = ctx_priv->in_params.norm_rate; in fsl_easrc_set_rs_ratio()
178 unsigned int out_rate = ctx_priv->out_params.norm_rate; in fsl_easrc_set_rs_ratio()
183 switch (easrc_priv->rs_num_taps) { in fsl_easrc_set_rs_ratio()
197 return -EINVAL; in fsl_easrc_set_rs_ratio()
205 dev_err(&easrc->pdev->dev, "ratio exceed range\n"); in fsl_easrc_set_rs_ratio()
206 return -EINVAL; in fsl_easrc_set_rs_ratio()
209 regmap_write(easrc->regmap, REG_EASRC_RRL(ctx->index), in fsl_easrc_set_rs_ratio()
211 regmap_write(easrc->regmap, REG_EASRC_RRH(ctx->index), in fsl_easrc_set_rs_ratio()
226 ctx_priv = ctx->private; in fsl_easrc_normalize_rates()
228 a = ctx_priv->in_params.sample_rate; in fsl_easrc_normalize_rates()
229 b = ctx_priv->out_params.sample_rate; in fsl_easrc_normalize_rates()
234 ctx_priv->in_params.norm_rate = ctx_priv->in_params.sample_rate / a; in fsl_easrc_normalize_rates()
235 ctx_priv->out_params.norm_rate = ctx_priv->out_params.sample_rate / a; in fsl_easrc_normalize_rates()
239 static int fsl_easrc_coeff_mem_ptr_reset(struct fsl_asrc *easrc, in fsl_easrc_coeff_mem_ptr_reset() argument
245 if (!easrc) in fsl_easrc_coeff_mem_ptr_reset()
246 return -ENODEV; in fsl_easrc_coeff_mem_ptr_reset()
248 dev = &easrc->pdev->dev; in fsl_easrc_coeff_mem_ptr_reset()
255 return -EINVAL; in fsl_easrc_coeff_mem_ptr_reset()
270 return -EINVAL; in fsl_easrc_coeff_mem_ptr_reset()
278 regmap_update_bits(easrc->regmap, reg, mask, 0); in fsl_easrc_coeff_mem_ptr_reset()
279 regmap_update_bits(easrc->regmap, reg, mask, val); in fsl_easrc_coeff_mem_ptr_reset()
280 regmap_update_bits(easrc->regmap, reg, mask, 0); in fsl_easrc_coeff_mem_ptr_reset()
299 static int fsl_easrc_resampler_config(struct fsl_asrc *easrc) in fsl_easrc_resampler_config() argument
301 struct device *dev = &easrc->pdev->dev; in fsl_easrc_resampler_config()
302 struct fsl_easrc_priv *easrc_priv = easrc->private; in fsl_easrc_resampler_config()
303 struct asrc_firmware_hdr *hdr = easrc_priv->firmware_hdr; in fsl_easrc_resampler_config()
304 struct interp_params *interp = easrc_priv->interp; in fsl_easrc_resampler_config()
314 return -ENODEV; in fsl_easrc_resampler_config()
317 for (i = 0; i < hdr->interp_scen; i++) { in fsl_easrc_resampler_config()
318 if ((interp[i].num_taps - 1) != in fsl_easrc_resampler_config()
319 bits_taps_to_val(easrc_priv->rs_num_taps)) in fsl_easrc_resampler_config()
324 dev_dbg(dev, "Selected interp_filter: %u taps - %u phases\n", in fsl_easrc_resampler_config()
325 selected_interp->num_taps, in fsl_easrc_resampler_config()
326 selected_interp->num_phases); in fsl_easrc_resampler_config()
332 return -EINVAL; in fsl_easrc_resampler_config()
336 * RS_LOW - first half of center tap of the sinc function in fsl_easrc_resampler_config()
337 * RS_HIGH - second half of center tap of the sinc function in fsl_easrc_resampler_config()
339 * symetrical - i.e. odd number of taps in fsl_easrc_resampler_config()
341 r = (uint32_t *)&selected_interp->center_tap; in fsl_easrc_resampler_config()
342 regmap_write(easrc->regmap, REG_EASRC_RCTCL, EASRC_RCTCL_RS_CL(r[0])); in fsl_easrc_resampler_config()
343 regmap_write(easrc->regmap, REG_EASRC_RCTCH, EASRC_RCTCH_RS_CH(r[1])); in fsl_easrc_resampler_config()
347 * 00b - 32-Tap Resampling Filter in fsl_easrc_resampler_config()
348 * 01b - 64-Tap Resampling Filter in fsl_easrc_resampler_config()
349 * 10b - 128-Tap Resampling Filter in fsl_easrc_resampler_config()
350 * 11b - N/A in fsl_easrc_resampler_config()
352 regmap_update_bits(easrc->regmap, REG_EASRC_CRCC, in fsl_easrc_resampler_config()
354 EASRC_CRCC_RS_TAPS(easrc_priv->rs_num_taps)); in fsl_easrc_resampler_config()
357 ret = fsl_easrc_coeff_mem_ptr_reset(easrc, 0, EASRC_RS_COEFF_MEM); in fsl_easrc_resampler_config()
363 * 32-tap mode, 16-taps, 128-phases 4-coefficients per phase in fsl_easrc_resampler_config()
364 * 64-tap mode, 32-taps, 64-phases 4-coefficients per phase in fsl_easrc_resampler_config()
365 * 128-tap mode, 64-taps, 32-phases 4-coefficients per phase in fsl_easrc_resampler_config()
373 regmap_write(easrc->regmap, REG_EASRC_CRCM, in fsl_easrc_resampler_config()
375 regmap_write(easrc->regmap, REG_EASRC_CRCM, in fsl_easrc_resampler_config()
383 * fsl_easrc_normalize_filter - Scale filter coefficients (64 bits float)
384 * For input float32 normalized range (1.0,-1.0) -> output int[16,24,32]:
386 * For input int[16, 24, 32] -> output float32
387 * scale it by multiplying filter coefficients by 2^-15, 2^-23, 2^-31
389 * @easrc: Structure pointer of fsl_asrc
390 * @infilter : Pointer to non-scaled input filter
395 static int fsl_easrc_normalize_filter(struct fsl_asrc *easrc, in fsl_easrc_normalize_filter() argument
400 struct device *dev = &easrc->pdev->dev; in fsl_easrc_normalize_filter()
419 return -EINVAL; in fsl_easrc_normalize_filter()
428 static int fsl_easrc_write_pf_coeff_mem(struct fsl_asrc *easrc, int ctx_id, in fsl_easrc_write_pf_coeff_mem() argument
431 struct device *dev = &easrc->pdev->dev; in fsl_easrc_write_pf_coeff_mem()
443 return -EINVAL; in fsl_easrc_write_pf_coeff_mem()
450 ret = fsl_easrc_coeff_mem_ptr_reset(easrc, ctx_id, EASRC_PF_COEFF_MEM); in fsl_easrc_write_pf_coeff_mem()
455 ret = fsl_easrc_normalize_filter(easrc, &coef[i], &tmp, shift); in fsl_easrc_write_pf_coeff_mem()
460 regmap_write(easrc->regmap, REG_EASRC_PCF(ctx_id), in fsl_easrc_write_pf_coeff_mem()
462 regmap_write(easrc->regmap, REG_EASRC_PCF(ctx_id), in fsl_easrc_write_pf_coeff_mem()
469 static int fsl_easrc_prefilter_config(struct fsl_asrc *easrc, in fsl_easrc_prefilter_config() argument
483 if (!easrc) in fsl_easrc_prefilter_config()
484 return -ENODEV; in fsl_easrc_prefilter_config()
486 dev = &easrc->pdev->dev; in fsl_easrc_prefilter_config()
490 return -EINVAL; in fsl_easrc_prefilter_config()
493 easrc_priv = easrc->private; in fsl_easrc_prefilter_config()
495 ctx = easrc->pair[ctx_id]; in fsl_easrc_prefilter_config()
496 ctx_priv = ctx->private; in fsl_easrc_prefilter_config()
498 in_s_rate = ctx_priv->in_params.sample_rate; in fsl_easrc_prefilter_config()
499 out_s_rate = ctx_priv->out_params.sample_rate; in fsl_easrc_prefilter_config()
500 in_s_fmt = ctx_priv->in_params.sample_format; in fsl_easrc_prefilter_config()
501 out_s_fmt = ctx_priv->out_params.sample_format; in fsl_easrc_prefilter_config()
503 ctx_priv->in_filled_sample = bits_taps_to_val(easrc_priv->rs_num_taps) / 2; in fsl_easrc_prefilter_config()
504 ctx_priv->out_missed_sample = ctx_priv->in_filled_sample * out_s_rate / in_s_rate; in fsl_easrc_prefilter_config()
506 ctx_priv->st1_num_taps = 0; in fsl_easrc_prefilter_config()
507 ctx_priv->st2_num_taps = 0; in fsl_easrc_prefilter_config()
509 regmap_write(easrc->regmap, REG_EASRC_CCE1(ctx_id), 0); in fsl_easrc_prefilter_config()
510 regmap_write(easrc->regmap, REG_EASRC_CCE2(ctx_id), 0); in fsl_easrc_prefilter_config()
513 * The audio float point data range is (-1, 1), the asrc would output in fsl_easrc_prefilter_config()
538 * 1. Create a 1 tap filter with center tap (only tap) of 2^-31 in fsl_easrc_prefilter_config()
553 regmap_update_bits(easrc->regmap, in fsl_easrc_prefilter_config()
558 ctx_priv->st1_num_taps = 1; in fsl_easrc_prefilter_config()
559 ctx_priv->st1_coeff = &easrc_priv->const_coeff; in fsl_easrc_prefilter_config()
560 ctx_priv->st1_num_exp = 1; in fsl_easrc_prefilter_config()
561 ctx_priv->st2_num_taps = 0; in fsl_easrc_prefilter_config()
565 ctx_priv->st1_addexp = 31; in fsl_easrc_prefilter_config()
568 ctx_priv->st1_addexp -= ctx_priv->in_params.fmt.addexp; in fsl_easrc_prefilter_config()
570 inrate = ctx_priv->in_params.norm_rate; in fsl_easrc_prefilter_config()
571 outrate = ctx_priv->out_params.norm_rate; in fsl_easrc_prefilter_config()
573 hdr = easrc_priv->firmware_hdr; in fsl_easrc_prefilter_config()
574 prefil = easrc_priv->prefil; in fsl_easrc_prefilter_config()
576 for (i = 0; i < hdr->prefil_scen; i++) { in fsl_easrc_prefilter_config()
581 selected_prefil->insr, in fsl_easrc_prefilter_config()
582 selected_prefil->outsr, in fsl_easrc_prefilter_config()
583 selected_prefil->st1_taps, in fsl_easrc_prefilter_config()
584 selected_prefil->st2_taps); in fsl_easrc_prefilter_config()
593 return -EINVAL; in fsl_easrc_prefilter_config()
601 ctx_priv->st1_num_taps = selected_prefil->st1_taps; in fsl_easrc_prefilter_config()
602 ctx_priv->st1_coeff = selected_prefil->coeff; in fsl_easrc_prefilter_config()
603 ctx_priv->st1_num_exp = selected_prefil->st1_exp; in fsl_easrc_prefilter_config()
605 offset = ((selected_prefil->st1_taps + 1) / 2); in fsl_easrc_prefilter_config()
606 ctx_priv->st2_num_taps = selected_prefil->st2_taps; in fsl_easrc_prefilter_config()
607 ctx_priv->st2_coeff = selected_prefil->coeff + offset; in fsl_easrc_prefilter_config()
612 if (ctx_priv->st2_num_taps > 0) in fsl_easrc_prefilter_config()
613 ctx_priv->st2_addexp = 31; in fsl_easrc_prefilter_config()
615 ctx_priv->st1_addexp = 31; in fsl_easrc_prefilter_config()
618 if (ctx_priv->st2_num_taps > 0) in fsl_easrc_prefilter_config()
619 ctx_priv->st2_addexp -= ctx_priv->in_params.fmt.addexp; in fsl_easrc_prefilter_config()
621 ctx_priv->st1_addexp -= ctx_priv->in_params.fmt.addexp; in fsl_easrc_prefilter_config()
625 ctx_priv->in_filled_sample += (ctx_priv->st1_num_taps / 2) * ctx_priv->st1_num_exp + in fsl_easrc_prefilter_config()
626 ctx_priv->st2_num_taps / 2; in fsl_easrc_prefilter_config()
627 ctx_priv->out_missed_sample = ctx_priv->in_filled_sample * out_s_rate / in_s_rate; in fsl_easrc_prefilter_config()
629 if (ctx_priv->in_filled_sample * out_s_rate % in_s_rate != 0) in fsl_easrc_prefilter_config()
630 ctx_priv->out_missed_sample += 1; in fsl_easrc_prefilter_config()
636 regmap_update_bits(easrc->regmap, REG_EASRC_CC(ctx_id), in fsl_easrc_prefilter_config()
639 if (ctx_priv->st1_num_taps > EASRC_MAX_PF_TAPS) { in fsl_easrc_prefilter_config()
641 ctx_priv->st1_num_taps, EASRC_MAX_PF_TAPS); in fsl_easrc_prefilter_config()
642 ret = -EINVAL; in fsl_easrc_prefilter_config()
647 regmap_update_bits(easrc->regmap, REG_EASRC_CCE2(ctx_id), in fsl_easrc_prefilter_config()
649 EASRC_CCE2_ST1_TAPS(ctx_priv->st1_num_taps - 1)); in fsl_easrc_prefilter_config()
652 regmap_update_bits(easrc->regmap, REG_EASRC_CCE1(ctx_id), in fsl_easrc_prefilter_config()
656 ret = fsl_easrc_write_pf_coeff_mem(easrc, ctx_id, in fsl_easrc_prefilter_config()
657 ctx_priv->st1_coeff, in fsl_easrc_prefilter_config()
658 ctx_priv->st1_num_taps, in fsl_easrc_prefilter_config()
659 ctx_priv->st1_addexp); in fsl_easrc_prefilter_config()
663 if (ctx_priv->st2_num_taps > 0) { in fsl_easrc_prefilter_config()
664 if (ctx_priv->st2_num_taps + ctx_priv->st1_num_taps > EASRC_MAX_PF_TAPS) { in fsl_easrc_prefilter_config()
666 ctx_priv->st2_num_taps, EASRC_MAX_PF_TAPS); in fsl_easrc_prefilter_config()
667 ret = -EINVAL; in fsl_easrc_prefilter_config()
671 regmap_update_bits(easrc->regmap, REG_EASRC_CCE1(ctx_id), in fsl_easrc_prefilter_config()
678 regmap_update_bits(easrc->regmap, REG_EASRC_CCE1(ctx_id), in fsl_easrc_prefilter_config()
682 regmap_update_bits(easrc->regmap, REG_EASRC_CCE1(ctx_id), in fsl_easrc_prefilter_config()
684 EASRC_CCE1_PF_EXP(ctx_priv->st1_num_exp - 1)); in fsl_easrc_prefilter_config()
687 regmap_update_bits(easrc->regmap, REG_EASRC_CCE2(ctx_id), in fsl_easrc_prefilter_config()
689 EASRC_CCE2_ST2_TAPS(ctx_priv->st2_num_taps - 1)); in fsl_easrc_prefilter_config()
692 regmap_update_bits(easrc->regmap, REG_EASRC_CCE1(ctx_id), in fsl_easrc_prefilter_config()
696 ret = fsl_easrc_write_pf_coeff_mem(easrc, ctx_id, in fsl_easrc_prefilter_config()
697 ctx_priv->st2_coeff, in fsl_easrc_prefilter_config()
698 ctx_priv->st2_num_taps, in fsl_easrc_prefilter_config()
699 ctx_priv->st2_addexp); in fsl_easrc_prefilter_config()
713 struct fsl_easrc_ctx_priv *ctx_priv = ctx->private; in fsl_easrc_max_ch_for_slot()
716 int max_channels = 8 - slot->num_channel; in fsl_easrc_max_ch_for_slot()
719 if (ctx_priv->st1_num_taps > 0) { in fsl_easrc_max_ch_for_slot()
720 if (ctx_priv->st2_num_taps > 0) in fsl_easrc_max_ch_for_slot()
722 (ctx_priv->st1_num_taps - 1) * ctx_priv->st1_num_exp + 1; in fsl_easrc_max_ch_for_slot()
724 st1_mem_alloc = ctx_priv->st1_num_taps; in fsl_easrc_max_ch_for_slot()
727 if (ctx_priv->st2_num_taps > 0) in fsl_easrc_max_ch_for_slot()
728 st2_mem_alloc = ctx_priv->st2_num_taps; in fsl_easrc_max_ch_for_slot()
733 channels = (6144 - slot->pf_mem_used) / pf_mem_alloc; in fsl_easrc_max_ch_for_slot()
750 struct fsl_asrc *easrc = ctx->asrc; in fsl_easrc_config_one_slot() local
751 struct fsl_easrc_ctx_priv *ctx_priv = ctx->private; in fsl_easrc_config_one_slot()
756 if (slot->slot_index == 0) { in fsl_easrc_config_one_slot()
769 slot->num_channel = *req_channels; in fsl_easrc_config_one_slot()
772 slot->num_channel = *avail_channel; in fsl_easrc_config_one_slot()
773 *req_channels -= *avail_channel; in fsl_easrc_config_one_slot()
776 slot->min_channel = *start_channel; in fsl_easrc_config_one_slot()
777 slot->max_channel = *start_channel + slot->num_channel - 1; in fsl_easrc_config_one_slot()
778 slot->ctx_index = ctx->index; in fsl_easrc_config_one_slot()
779 slot->busy = true; in fsl_easrc_config_one_slot()
780 *start_channel += slot->num_channel; in fsl_easrc_config_one_slot()
782 regmap_update_bits(easrc->regmap, reg0, in fsl_easrc_config_one_slot()
784 EASRC_DPCS0R0_MAXCH(slot->max_channel)); in fsl_easrc_config_one_slot()
786 regmap_update_bits(easrc->regmap, reg0, in fsl_easrc_config_one_slot()
788 EASRC_DPCS0R0_MINCH(slot->min_channel)); in fsl_easrc_config_one_slot()
790 regmap_update_bits(easrc->regmap, reg0, in fsl_easrc_config_one_slot()
792 EASRC_DPCS0R0_NUMCH(slot->num_channel - 1)); in fsl_easrc_config_one_slot()
794 regmap_update_bits(easrc->regmap, reg0, in fsl_easrc_config_one_slot()
796 EASRC_DPCS0R0_CTXNUM(slot->ctx_index)); in fsl_easrc_config_one_slot()
798 if (ctx_priv->st1_num_taps > 0) { in fsl_easrc_config_one_slot()
799 if (ctx_priv->st2_num_taps > 0) in fsl_easrc_config_one_slot()
801 (ctx_priv->st1_num_taps - 1) * slot->num_channel * in fsl_easrc_config_one_slot()
802 ctx_priv->st1_num_exp + slot->num_channel; in fsl_easrc_config_one_slot()
804 st1_mem_alloc = ctx_priv->st1_num_taps * slot->num_channel; in fsl_easrc_config_one_slot()
806 slot->pf_mem_used = st1_mem_alloc; in fsl_easrc_config_one_slot()
807 regmap_update_bits(easrc->regmap, reg2, in fsl_easrc_config_one_slot()
811 if (slot->slot_index == 1) in fsl_easrc_config_one_slot()
812 addr = PREFILTER_MEM_LEN - st1_mem_alloc; in fsl_easrc_config_one_slot()
816 regmap_update_bits(easrc->regmap, reg2, in fsl_easrc_config_one_slot()
821 if (ctx_priv->st2_num_taps > 0) { in fsl_easrc_config_one_slot()
822 st1_chanxexp = slot->num_channel * (ctx_priv->st1_num_exp - 1); in fsl_easrc_config_one_slot()
824 regmap_update_bits(easrc->regmap, reg1, in fsl_easrc_config_one_slot()
828 st2_mem_alloc = slot->num_channel * ctx_priv->st2_num_taps; in fsl_easrc_config_one_slot()
829 slot->pf_mem_used += st2_mem_alloc; in fsl_easrc_config_one_slot()
830 regmap_update_bits(easrc->regmap, reg3, in fsl_easrc_config_one_slot()
834 if (slot->slot_index == 1) in fsl_easrc_config_one_slot()
835 addr = PREFILTER_MEM_LEN - st1_mem_alloc - st2_mem_alloc; in fsl_easrc_config_one_slot()
839 regmap_update_bits(easrc->regmap, reg3, in fsl_easrc_config_one_slot()
844 regmap_update_bits(easrc->regmap, reg0, in fsl_easrc_config_one_slot()
861 static int fsl_easrc_config_slot(struct fsl_asrc *easrc, unsigned int ctx_id) in fsl_easrc_config_slot() argument
863 struct fsl_easrc_priv *easrc_priv = easrc->private; in fsl_easrc_config_slot()
864 struct fsl_asrc_pair *ctx = easrc->pair[ctx_id]; in fsl_easrc_config_slot()
865 int req_channels = ctx->channels; in fsl_easrc_config_slot()
872 return -EINVAL; in fsl_easrc_config_slot()
875 slot0 = &easrc_priv->slot[i][0]; in fsl_easrc_config_slot()
876 slot1 = &easrc_priv->slot[i][1]; in fsl_easrc_config_slot()
878 if (slot0->busy && slot1->busy) { in fsl_easrc_config_slot()
880 } else if ((slot0->busy && slot0->ctx_index == ctx->index) || in fsl_easrc_config_slot()
881 (slot1->busy && slot1->ctx_index == ctx->index)) { in fsl_easrc_config_slot()
883 } else if (!slot0->busy) { in fsl_easrc_config_slot()
886 slota->slot_index = 0; in fsl_easrc_config_slot()
887 } else if (!slot1->busy) { in fsl_easrc_config_slot()
890 slota->slot_index = 1; in fsl_easrc_config_slot()
912 dev_err(&easrc->pdev->dev, "no avail slot.\n"); in fsl_easrc_config_slot()
913 return -EINVAL; in fsl_easrc_config_slot()
924 static int fsl_easrc_release_slot(struct fsl_asrc *easrc, unsigned int ctx_id) in fsl_easrc_release_slot() argument
926 struct fsl_easrc_priv *easrc_priv = easrc->private; in fsl_easrc_release_slot()
927 struct fsl_asrc_pair *ctx = easrc->pair[ctx_id]; in fsl_easrc_release_slot()
931 if (easrc_priv->slot[i][0].busy && in fsl_easrc_release_slot()
932 easrc_priv->slot[i][0].ctx_index == ctx->index) { in fsl_easrc_release_slot()
933 easrc_priv->slot[i][0].busy = false; in fsl_easrc_release_slot()
934 easrc_priv->slot[i][0].num_channel = 0; in fsl_easrc_release_slot()
935 easrc_priv->slot[i][0].pf_mem_used = 0; in fsl_easrc_release_slot()
937 regmap_write(easrc->regmap, REG_EASRC_DPCS0R0(i), 0); in fsl_easrc_release_slot()
938 regmap_write(easrc->regmap, REG_EASRC_DPCS0R1(i), 0); in fsl_easrc_release_slot()
939 regmap_write(easrc->regmap, REG_EASRC_DPCS0R2(i), 0); in fsl_easrc_release_slot()
940 regmap_write(easrc->regmap, REG_EASRC_DPCS0R3(i), 0); in fsl_easrc_release_slot()
943 if (easrc_priv->slot[i][1].busy && in fsl_easrc_release_slot()
944 easrc_priv->slot[i][1].ctx_index == ctx->index) { in fsl_easrc_release_slot()
945 easrc_priv->slot[i][1].busy = false; in fsl_easrc_release_slot()
946 easrc_priv->slot[i][1].num_channel = 0; in fsl_easrc_release_slot()
947 easrc_priv->slot[i][1].pf_mem_used = 0; in fsl_easrc_release_slot()
949 regmap_write(easrc->regmap, REG_EASRC_DPCS1R0(i), 0); in fsl_easrc_release_slot()
950 regmap_write(easrc->regmap, REG_EASRC_DPCS1R1(i), 0); in fsl_easrc_release_slot()
951 regmap_write(easrc->regmap, REG_EASRC_DPCS1R2(i), 0); in fsl_easrc_release_slot()
952 regmap_write(easrc->regmap, REG_EASRC_DPCS1R3(i), 0); in fsl_easrc_release_slot()
964 static int fsl_easrc_config_context(struct fsl_asrc *easrc, unsigned int ctx_id) in fsl_easrc_config_context() argument
972 if (!easrc) in fsl_easrc_config_context()
973 return -ENODEV; in fsl_easrc_config_context()
975 dev = &easrc->pdev->dev; in fsl_easrc_config_context()
979 return -EINVAL; in fsl_easrc_config_context()
982 ctx = easrc->pair[ctx_id]; in fsl_easrc_config_context()
984 ctx_priv = ctx->private; in fsl_easrc_config_context()
993 ret = fsl_easrc_prefilter_config(easrc, ctx->index); in fsl_easrc_config_context()
997 spin_lock_irqsave(&easrc->lock, lock_flags); in fsl_easrc_config_context()
998 ret = fsl_easrc_config_slot(easrc, ctx->index); in fsl_easrc_config_context()
999 spin_unlock_irqrestore(&easrc->lock, lock_flags); in fsl_easrc_config_context()
1006 * 2 - zero-fil mode in fsl_easrc_config_context()
1007 * 1 - replication mode in fsl_easrc_config_context()
1008 * 0 - software control in fsl_easrc_config_context()
1010 regmap_update_bits(easrc->regmap, REG_EASRC_CCE1(ctx_id), in fsl_easrc_config_context()
1012 EASRC_CCE1_RS_INIT(ctx_priv->rs_init_mode)); in fsl_easrc_config_context()
1014 regmap_update_bits(easrc->regmap, REG_EASRC_CCE1(ctx_id), in fsl_easrc_config_context()
1016 EASRC_CCE1_PF_INIT(ctx_priv->pf_init_mode)); in fsl_easrc_config_context()
1022 regmap_update_bits(easrc->regmap, REG_EASRC_CC(ctx_id), in fsl_easrc_config_context()
1024 EASRC_CC_FIFO_WTMK(ctx_priv->in_params.fifo_wtmk)); in fsl_easrc_config_context()
1029 * So we set fifo_wtmk -1 to register. in fsl_easrc_config_context()
1031 regmap_update_bits(easrc->regmap, REG_EASRC_COC(ctx_id), in fsl_easrc_config_context()
1033 EASRC_COC_FIFO_WTMK(ctx_priv->out_params.fifo_wtmk - 1)); in fsl_easrc_config_context()
1036 regmap_update_bits(easrc->regmap, REG_EASRC_CC(ctx_id), in fsl_easrc_config_context()
1038 EASRC_CC_CHEN(ctx->channels - 1)); in fsl_easrc_config_context()
1046 struct fsl_asrc *easrc = ctx->asrc; in fsl_easrc_process_format() local
1047 struct fsl_easrc_priv *easrc_priv = easrc->private; in fsl_easrc_process_format()
1051 return -EINVAL; in fsl_easrc_process_format()
1055 * 0 - Integer Format in fsl_easrc_process_format()
1056 * 1 - Single Precision FP Format in fsl_easrc_process_format()
1058 fmt->floating_point = !snd_pcm_format_linear(raw_fmt); in fsl_easrc_process_format()
1059 fmt->sample_pos = 0; in fsl_easrc_process_format()
1060 fmt->iec958 = 0; in fsl_easrc_process_format()
1065 fmt->width = EASRC_WIDTH_16_BIT; in fsl_easrc_process_format()
1066 fmt->addexp = 15; in fsl_easrc_process_format()
1069 fmt->width = EASRC_WIDTH_20_BIT; in fsl_easrc_process_format()
1070 fmt->addexp = 19; in fsl_easrc_process_format()
1073 fmt->width = EASRC_WIDTH_24_BIT; in fsl_easrc_process_format()
1074 fmt->addexp = 23; in fsl_easrc_process_format()
1077 fmt->width = EASRC_WIDTH_32_BIT; in fsl_easrc_process_format()
1078 fmt->addexp = 31; in fsl_easrc_process_format()
1081 return -EINVAL; in fsl_easrc_process_format()
1086 fmt->width = easrc_priv->bps_iec958[ctx->index]; in fsl_easrc_process_format()
1087 fmt->iec958 = 1; in fsl_easrc_process_format()
1088 fmt->floating_point = 0; in fsl_easrc_process_format()
1089 if (fmt->width == EASRC_WIDTH_16_BIT) { in fsl_easrc_process_format()
1090 fmt->sample_pos = 12; in fsl_easrc_process_format()
1091 fmt->addexp = 15; in fsl_easrc_process_format()
1092 } else if (fmt->width == EASRC_WIDTH_20_BIT) { in fsl_easrc_process_format()
1093 fmt->sample_pos = 8; in fsl_easrc_process_format()
1094 fmt->addexp = 19; in fsl_easrc_process_format()
1095 } else if (fmt->width == EASRC_WIDTH_24_BIT) { in fsl_easrc_process_format()
1096 fmt->sample_pos = 4; in fsl_easrc_process_format()
1097 fmt->addexp = 23; in fsl_easrc_process_format()
1106 * 0 - Little-Endian in fsl_easrc_process_format()
1107 * 1 - Big-Endian in fsl_easrc_process_format()
1113 fmt->endianness = ret; in fsl_easrc_process_format()
1117 * 0b - Signed Format in fsl_easrc_process_format()
1118 * 1b - Unsigned Format in fsl_easrc_process_format()
1120 fmt->unsign = snd_pcm_format_unsigned(raw_fmt) > 0 ? 1 : 0; in fsl_easrc_process_format()
1129 struct fsl_asrc *easrc = ctx->asrc; in fsl_easrc_set_ctx_format() local
1130 struct fsl_easrc_ctx_priv *ctx_priv = ctx->private; in fsl_easrc_set_ctx_format()
1131 struct fsl_easrc_data_fmt *in_fmt = &ctx_priv->in_params.fmt; in fsl_easrc_set_ctx_format()
1132 struct fsl_easrc_data_fmt *out_fmt = &ctx_priv->out_params.fmt; in fsl_easrc_set_ctx_format()
1142 regmap_update_bits(easrc->regmap, REG_EASRC_CC(ctx->index), in fsl_easrc_set_ctx_format()
1144 EASRC_CC_BPS(in_fmt->width)); in fsl_easrc_set_ctx_format()
1145 regmap_update_bits(easrc->regmap, REG_EASRC_CC(ctx->index), in fsl_easrc_set_ctx_format()
1147 in_fmt->endianness << EASRC_CC_ENDIANNESS_SHIFT); in fsl_easrc_set_ctx_format()
1148 regmap_update_bits(easrc->regmap, REG_EASRC_CC(ctx->index), in fsl_easrc_set_ctx_format()
1150 in_fmt->floating_point << EASRC_CC_FMT_SHIFT); in fsl_easrc_set_ctx_format()
1151 regmap_update_bits(easrc->regmap, REG_EASRC_CC(ctx->index), in fsl_easrc_set_ctx_format()
1153 in_fmt->unsign << EASRC_CC_INSIGN_SHIFT); in fsl_easrc_set_ctx_format()
1156 regmap_update_bits(easrc->regmap, REG_EASRC_CC(ctx->index), in fsl_easrc_set_ctx_format()
1158 EASRC_CC_SAMPLE_POS(in_fmt->sample_pos)); in fsl_easrc_set_ctx_format()
1167 regmap_update_bits(easrc->regmap, REG_EASRC_COC(ctx->index), in fsl_easrc_set_ctx_format()
1169 EASRC_COC_BPS(out_fmt->width)); in fsl_easrc_set_ctx_format()
1170 regmap_update_bits(easrc->regmap, REG_EASRC_COC(ctx->index), in fsl_easrc_set_ctx_format()
1172 out_fmt->endianness << EASRC_COC_ENDIANNESS_SHIFT); in fsl_easrc_set_ctx_format()
1173 regmap_update_bits(easrc->regmap, REG_EASRC_COC(ctx->index), in fsl_easrc_set_ctx_format()
1175 out_fmt->floating_point << EASRC_COC_FMT_SHIFT); in fsl_easrc_set_ctx_format()
1176 regmap_update_bits(easrc->regmap, REG_EASRC_COC(ctx->index), in fsl_easrc_set_ctx_format()
1178 out_fmt->unsign << EASRC_COC_OUTSIGN_SHIFT); in fsl_easrc_set_ctx_format()
1181 regmap_update_bits(easrc->regmap, REG_EASRC_COC(ctx->index), in fsl_easrc_set_ctx_format()
1183 EASRC_COC_SAMPLE_POS(out_fmt->sample_pos)); in fsl_easrc_set_ctx_format()
1185 regmap_update_bits(easrc->regmap, REG_EASRC_COC(ctx->index), in fsl_easrc_set_ctx_format()
1187 out_fmt->iec958 << EASRC_COC_IEC_EN_SHIFT); in fsl_easrc_set_ctx_format()
1201 struct fsl_asrc *easrc; in fsl_easrc_set_ctx_organziation() local
1204 return -ENODEV; in fsl_easrc_set_ctx_organziation()
1206 easrc = ctx->asrc; in fsl_easrc_set_ctx_organziation()
1207 ctx_priv = ctx->private; in fsl_easrc_set_ctx_organziation()
1210 regmap_update_bits(easrc->regmap, REG_EASRC_CIA(ctx->index), in fsl_easrc_set_ctx_organziation()
1212 EASRC_CIA_ITER(ctx_priv->in_params.iterations)); in fsl_easrc_set_ctx_organziation()
1213 regmap_update_bits(easrc->regmap, REG_EASRC_CIA(ctx->index), in fsl_easrc_set_ctx_organziation()
1215 EASRC_CIA_GRLEN(ctx_priv->in_params.group_len)); in fsl_easrc_set_ctx_organziation()
1216 regmap_update_bits(easrc->regmap, REG_EASRC_CIA(ctx->index), in fsl_easrc_set_ctx_organziation()
1218 EASRC_CIA_ACCLEN(ctx_priv->in_params.access_len)); in fsl_easrc_set_ctx_organziation()
1221 regmap_update_bits(easrc->regmap, REG_EASRC_COA(ctx->index), in fsl_easrc_set_ctx_organziation()
1223 EASRC_COA_ITER(ctx_priv->out_params.iterations)); in fsl_easrc_set_ctx_organziation()
1224 regmap_update_bits(easrc->regmap, REG_EASRC_COA(ctx->index), in fsl_easrc_set_ctx_organziation()
1226 EASRC_COA_GRLEN(ctx_priv->out_params.group_len)); in fsl_easrc_set_ctx_organziation()
1227 regmap_update_bits(easrc->regmap, REG_EASRC_COA(ctx->index), in fsl_easrc_set_ctx_organziation()
1229 EASRC_COA_ACCLEN(ctx_priv->out_params.access_len)); in fsl_easrc_set_ctx_organziation()
1243 struct fsl_asrc *easrc = ctx->asrc; in fsl_easrc_request_context() local
1249 dev = &easrc->pdev->dev; in fsl_easrc_request_context()
1251 spin_lock_irqsave(&easrc->lock, lock_flags); in fsl_easrc_request_context()
1254 if (easrc->pair[i]) in fsl_easrc_request_context()
1263 ret = -EBUSY; in fsl_easrc_request_context()
1264 } else if (channels > easrc->channel_avail) { in fsl_easrc_request_context()
1267 ret = -EINVAL; in fsl_easrc_request_context()
1269 ctx->index = index; in fsl_easrc_request_context()
1270 ctx->channels = channels; in fsl_easrc_request_context()
1271 easrc->pair[index] = ctx; in fsl_easrc_request_context()
1272 easrc->channel_avail -= channels; in fsl_easrc_request_context()
1275 spin_unlock_irqrestore(&easrc->lock, lock_flags); in fsl_easrc_request_context()
1288 struct fsl_asrc *easrc; in fsl_easrc_release_context() local
1293 easrc = ctx->asrc; in fsl_easrc_release_context()
1295 spin_lock_irqsave(&easrc->lock, lock_flags); in fsl_easrc_release_context()
1297 fsl_easrc_release_slot(easrc, ctx->index); in fsl_easrc_release_context()
1299 easrc->channel_avail += ctx->channels; in fsl_easrc_release_context()
1300 easrc->pair[ctx->index] = NULL; in fsl_easrc_release_context()
1302 spin_unlock_irqrestore(&easrc->lock, lock_flags); in fsl_easrc_release_context()
1312 struct fsl_asrc *easrc = ctx->asrc; in fsl_easrc_start_context() local
1314 regmap_update_bits(easrc->regmap, REG_EASRC_CC(ctx->index), in fsl_easrc_start_context()
1316 regmap_update_bits(easrc->regmap, REG_EASRC_COC(ctx->index), in fsl_easrc_start_context()
1318 regmap_update_bits(easrc->regmap, REG_EASRC_CC(ctx->index), in fsl_easrc_start_context()
1330 struct fsl_asrc *easrc = ctx->asrc; in fsl_easrc_stop_context() local
1335 regmap_read(easrc->regmap, REG_EASRC_CC(ctx->index), &val); in fsl_easrc_stop_context()
1338 regmap_update_bits(easrc->regmap, in fsl_easrc_stop_context()
1339 REG_EASRC_CC(ctx->index), in fsl_easrc_stop_context()
1342 regmap_read(easrc->regmap, REG_EASRC_SFS(ctx->index), &val); in fsl_easrc_stop_context()
1347 for (i = 0; i < size * ctx->channels; i++) in fsl_easrc_stop_context()
1348 regmap_read(easrc->regmap, REG_EASRC_RDFIFO(ctx->index), &val); in fsl_easrc_stop_context()
1350 regmap_read(easrc->regmap, REG_EASRC_IRQF, &val); in fsl_easrc_stop_context()
1351 if (val & EASRC_IRQF_RSD(1 << ctx->index)) { in fsl_easrc_stop_context()
1353 regmap_write_bits(easrc->regmap, in fsl_easrc_stop_context()
1355 EASRC_IRQF_RSD(1 << ctx->index), in fsl_easrc_stop_context()
1356 EASRC_IRQF_RSD(1 << ctx->index)); in fsl_easrc_stop_context()
1360 } while (--retry); in fsl_easrc_stop_context()
1363 dev_warn(&easrc->pdev->dev, "RUN STOP fail\n"); in fsl_easrc_stop_context()
1366 regmap_update_bits(easrc->regmap, REG_EASRC_CC(ctx->index), in fsl_easrc_stop_context()
1368 regmap_update_bits(easrc->regmap, REG_EASRC_CC(ctx->index), in fsl_easrc_stop_context()
1370 regmap_update_bits(easrc->regmap, REG_EASRC_COC(ctx->index), in fsl_easrc_stop_context()
1378 struct fsl_asrc *easrc = ctx->asrc; in fsl_easrc_get_dma_channel() local
1379 enum asrc_pair_index index = ctx->index; in fsl_easrc_get_dma_channel()
1385 return dma_request_slave_channel(&easrc->pdev->dev, name); in fsl_easrc_get_dma_channel()
1404 return snd_pcm_hw_constraint_list(substream->runtime, 0, in fsl_easrc_startup()
1412 struct snd_pcm_runtime *runtime = substream->runtime; in fsl_easrc_trigger()
1413 struct fsl_asrc_pair *ctx = runtime->private_data; in fsl_easrc_trigger()
1432 return -EINVAL; in fsl_easrc_trigger()
1442 struct fsl_asrc *easrc = snd_soc_dai_get_drvdata(dai); in fsl_easrc_hw_params() local
1443 struct snd_pcm_runtime *runtime = substream->runtime; in fsl_easrc_hw_params()
1444 struct device *dev = &easrc->pdev->dev; in fsl_easrc_hw_params()
1445 struct fsl_asrc_pair *ctx = runtime->private_data; in fsl_easrc_hw_params()
1446 struct fsl_easrc_ctx_priv *ctx_priv = ctx->private; in fsl_easrc_hw_params()
1458 ctx_priv->ctx_streams |= BIT(substream->stream); in fsl_easrc_hw_params()
1464 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) { in fsl_easrc_hw_params()
1465 ctx_priv->in_params.sample_rate = rate; in fsl_easrc_hw_params()
1466 ctx_priv->in_params.sample_format = format; in fsl_easrc_hw_params()
1467 ctx_priv->out_params.sample_rate = easrc->asrc_rate; in fsl_easrc_hw_params()
1468 ctx_priv->out_params.sample_format = easrc->asrc_format; in fsl_easrc_hw_params()
1470 ctx_priv->out_params.sample_rate = rate; in fsl_easrc_hw_params()
1471 ctx_priv->out_params.sample_format = format; in fsl_easrc_hw_params()
1472 ctx_priv->in_params.sample_rate = easrc->asrc_rate; in fsl_easrc_hw_params()
1473 ctx_priv->in_params.sample_format = easrc->asrc_format; in fsl_easrc_hw_params()
1476 ctx->channels = channels; in fsl_easrc_hw_params()
1477 ctx_priv->in_params.fifo_wtmk = 0x20; in fsl_easrc_hw_params()
1478 ctx_priv->out_params.fifo_wtmk = 0x20; in fsl_easrc_hw_params()
1485 &ctx_priv->in_params.sample_format, in fsl_easrc_hw_params()
1486 &ctx_priv->out_params.sample_format); in fsl_easrc_hw_params()
1492 ret = fsl_easrc_config_context(easrc, ctx->index); in fsl_easrc_hw_params()
1498 ctx_priv->in_params.iterations = 1; in fsl_easrc_hw_params()
1499 ctx_priv->in_params.group_len = ctx->channels; in fsl_easrc_hw_params()
1500 ctx_priv->in_params.access_len = ctx->channels; in fsl_easrc_hw_params()
1501 ctx_priv->out_params.iterations = 1; in fsl_easrc_hw_params()
1502 ctx_priv->out_params.group_len = ctx->channels; in fsl_easrc_hw_params()
1503 ctx_priv->out_params.access_len = ctx->channels; in fsl_easrc_hw_params()
1517 struct snd_pcm_runtime *runtime = substream->runtime; in fsl_easrc_hw_free()
1518 struct fsl_asrc_pair *ctx = runtime->private_data; in fsl_easrc_hw_free()
1522 return -EINVAL; in fsl_easrc_hw_free()
1524 ctx_priv = ctx->private; in fsl_easrc_hw_free()
1526 if (ctx_priv->ctx_streams & BIT(substream->stream)) { in fsl_easrc_hw_free()
1527 ctx_priv->ctx_streams &= ~BIT(substream->stream); in fsl_easrc_hw_free()
1536 struct fsl_asrc *easrc = dev_get_drvdata(cpu_dai->dev); in fsl_easrc_dai_probe() local
1539 &easrc->dma_params_tx, in fsl_easrc_dai_probe()
1540 &easrc->dma_params_rx); in fsl_easrc_dai_probe()
1554 .stream_name = "ASRC-Playback",
1563 .stream_name = "ASRC-Capture",
1576 .name = "fsl-easrc-dai",
1755 static void fsl_easrc_dump_firmware(struct fsl_asrc *easrc) in fsl_easrc_dump_firmware() argument
1757 struct fsl_easrc_priv *easrc_priv = easrc->private; in fsl_easrc_dump_firmware()
1758 struct asrc_firmware_hdr *firm = easrc_priv->firmware_hdr; in fsl_easrc_dump_firmware()
1759 struct interp_params *interp = easrc_priv->interp; in fsl_easrc_dump_firmware()
1760 struct prefil_params *prefil = easrc_priv->prefil; in fsl_easrc_dump_firmware()
1761 struct device *dev = &easrc->pdev->dev; in fsl_easrc_dump_firmware()
1764 if (firm->magic != FIRMWARE_MAGIC) { in fsl_easrc_dump_firmware()
1769 dev_dbg(dev, "Firmware v%u dump:\n", firm->firmware_version); in fsl_easrc_dump_firmware()
1770 dev_dbg(dev, "Num prefilter scenarios: %u\n", firm->prefil_scen); in fsl_easrc_dump_firmware()
1771 dev_dbg(dev, "Num interpolation scenarios: %u\n", firm->interp_scen); in fsl_easrc_dump_firmware()
1774 for (i = 0; i < firm->interp_scen; i++) { in fsl_easrc_dump_firmware()
1785 for (i = 0; i < firm->prefil_scen; i++) { in fsl_easrc_dump_firmware()
1800 static int fsl_easrc_get_firmware(struct fsl_asrc *easrc) in fsl_easrc_get_firmware() argument
1808 if (!easrc) in fsl_easrc_get_firmware()
1809 return -EINVAL; in fsl_easrc_get_firmware()
1811 easrc_priv = easrc->private; in fsl_easrc_get_firmware()
1812 fw_p = &easrc_priv->fw; in fsl_easrc_get_firmware()
1814 ret = request_firmware(fw_p, easrc_priv->fw_name, &easrc->pdev->dev); in fsl_easrc_get_firmware()
1818 data = easrc_priv->fw->data; in fsl_easrc_get_firmware()
1820 easrc_priv->firmware_hdr = (struct asrc_firmware_hdr *)data; in fsl_easrc_get_firmware()
1821 pnum = easrc_priv->firmware_hdr->prefil_scen; in fsl_easrc_get_firmware()
1822 inum = easrc_priv->firmware_hdr->interp_scen; in fsl_easrc_get_firmware()
1826 easrc_priv->interp = (struct interp_params *)(data + offset); in fsl_easrc_get_firmware()
1832 easrc_priv->prefil = (struct prefil_params *)(data + offset); in fsl_easrc_get_firmware()
1836 fsl_easrc_dump_firmware(easrc); in fsl_easrc_get_firmware()
1844 struct fsl_asrc *easrc = (struct fsl_asrc *)dev_id; in fsl_easrc_isr() local
1845 struct device *dev = &easrc->pdev->dev; in fsl_easrc_isr()
1848 regmap_read(easrc->regmap, REG_EASRC_IRQF, &val); in fsl_easrc_isr()
1865 { .compatible = "fsl,imx8mn-easrc",},
1873 struct device *dev = &pdev->dev; in fsl_easrc_probe()
1874 struct fsl_asrc *easrc; in fsl_easrc_probe() local
1881 easrc = devm_kzalloc(dev, sizeof(*easrc), GFP_KERNEL); in fsl_easrc_probe()
1882 if (!easrc) in fsl_easrc_probe()
1883 return -ENOMEM; in fsl_easrc_probe()
1887 return -ENOMEM; in fsl_easrc_probe()
1889 easrc->pdev = pdev; in fsl_easrc_probe()
1890 easrc->private = easrc_priv; in fsl_easrc_probe()
1891 np = dev->of_node; in fsl_easrc_probe()
1897 easrc->paddr = res->start; in fsl_easrc_probe()
1899 easrc->regmap = devm_regmap_init_mmio(dev, regs, &fsl_easrc_regmap_config); in fsl_easrc_probe()
1900 if (IS_ERR(easrc->regmap)) { in fsl_easrc_probe()
1902 return PTR_ERR(easrc->regmap); in fsl_easrc_probe()
1909 ret = devm_request_irq(&pdev->dev, irq, fsl_easrc_isr, 0, in fsl_easrc_probe()
1910 dev_name(dev), easrc); in fsl_easrc_probe()
1916 easrc->mem_clk = devm_clk_get(dev, "mem"); in fsl_easrc_probe()
1917 if (IS_ERR(easrc->mem_clk)) { in fsl_easrc_probe()
1919 return PTR_ERR(easrc->mem_clk); in fsl_easrc_probe()
1923 easrc->channel_avail = 32; in fsl_easrc_probe()
1924 easrc->get_dma_channel = fsl_easrc_get_dma_channel; in fsl_easrc_probe()
1925 easrc->request_pair = fsl_easrc_request_context; in fsl_easrc_probe()
1926 easrc->release_pair = fsl_easrc_release_context; in fsl_easrc_probe()
1927 easrc->get_fifo_addr = fsl_easrc_get_fifo_addr; in fsl_easrc_probe()
1928 easrc->pair_priv_size = sizeof(struct fsl_easrc_ctx_priv); in fsl_easrc_probe()
1930 easrc_priv->rs_num_taps = EASRC_RS_32_TAPS; in fsl_easrc_probe()
1931 easrc_priv->const_coeff = 0x3FF0000000000000; in fsl_easrc_probe()
1933 ret = of_property_read_u32(np, "fsl,asrc-rate", &easrc->asrc_rate); in fsl_easrc_probe()
1939 ret = of_property_read_u32(np, "fsl,asrc-format", &asrc_fmt); in fsl_easrc_probe()
1940 easrc->asrc_format = (__force snd_pcm_format_t)asrc_fmt; in fsl_easrc_probe()
1946 if (!(FSL_EASRC_FORMATS & (pcm_format_to_bits(easrc->asrc_format)))) { in fsl_easrc_probe()
1948 easrc->asrc_format = SNDRV_PCM_FORMAT_S24_LE; in fsl_easrc_probe()
1951 ret = of_property_read_string(np, "firmware-name", in fsl_easrc_probe()
1952 &easrc_priv->fw_name); in fsl_easrc_probe()
1958 platform_set_drvdata(pdev, easrc); in fsl_easrc_probe()
1961 spin_lock_init(&easrc->lock); in fsl_easrc_probe()
1963 regcache_cache_only(easrc->regmap, true); in fsl_easrc_probe()
1975 dev_err(&pdev->dev, "failed to register ASoC platform\n"); in fsl_easrc_probe()
1982 pm_runtime_disable(&pdev->dev); in fsl_easrc_probe()
1988 pm_runtime_disable(&pdev->dev); in fsl_easrc_remove()
1993 struct fsl_asrc *easrc = dev_get_drvdata(dev); in fsl_easrc_runtime_suspend() local
1994 struct fsl_easrc_priv *easrc_priv = easrc->private; in fsl_easrc_runtime_suspend()
1997 regcache_cache_only(easrc->regmap, true); in fsl_easrc_runtime_suspend()
1999 clk_disable_unprepare(easrc->mem_clk); in fsl_easrc_runtime_suspend()
2001 spin_lock_irqsave(&easrc->lock, lock_flags); in fsl_easrc_runtime_suspend()
2002 easrc_priv->firmware_loaded = 0; in fsl_easrc_runtime_suspend()
2003 spin_unlock_irqrestore(&easrc->lock, lock_flags); in fsl_easrc_runtime_suspend()
2010 struct fsl_asrc *easrc = dev_get_drvdata(dev); in fsl_easrc_runtime_resume() local
2011 struct fsl_easrc_priv *easrc_priv = easrc->private; in fsl_easrc_runtime_resume()
2018 ret = clk_prepare_enable(easrc->mem_clk); in fsl_easrc_runtime_resume()
2022 regcache_cache_only(easrc->regmap, false); in fsl_easrc_runtime_resume()
2023 regcache_mark_dirty(easrc->regmap); in fsl_easrc_runtime_resume()
2024 regcache_sync(easrc->regmap); in fsl_easrc_runtime_resume()
2026 spin_lock_irqsave(&easrc->lock, lock_flags); in fsl_easrc_runtime_resume()
2027 if (easrc_priv->firmware_loaded) { in fsl_easrc_runtime_resume()
2028 spin_unlock_irqrestore(&easrc->lock, lock_flags); in fsl_easrc_runtime_resume()
2031 easrc_priv->firmware_loaded = 1; in fsl_easrc_runtime_resume()
2032 spin_unlock_irqrestore(&easrc->lock, lock_flags); in fsl_easrc_runtime_resume()
2034 ret = fsl_easrc_get_firmware(easrc); in fsl_easrc_runtime_resume()
2045 ret = fsl_easrc_resampler_config(easrc); in fsl_easrc_runtime_resume()
2052 ctx = easrc->pair[i]; in fsl_easrc_runtime_resume()
2056 ctx_priv = ctx->private; in fsl_easrc_runtime_resume()
2058 ctx_priv->out_missed_sample = ctx_priv->in_filled_sample * in fsl_easrc_runtime_resume()
2059 ctx_priv->out_params.sample_rate / in fsl_easrc_runtime_resume()
2060 ctx_priv->in_params.sample_rate; in fsl_easrc_runtime_resume()
2061 if (ctx_priv->in_filled_sample * ctx_priv->out_params.sample_rate in fsl_easrc_runtime_resume()
2062 % ctx_priv->in_params.sample_rate != 0) in fsl_easrc_runtime_resume()
2063 ctx_priv->out_missed_sample += 1; in fsl_easrc_runtime_resume()
2065 ret = fsl_easrc_write_pf_coeff_mem(easrc, i, in fsl_easrc_runtime_resume()
2066 ctx_priv->st1_coeff, in fsl_easrc_runtime_resume()
2067 ctx_priv->st1_num_taps, in fsl_easrc_runtime_resume()
2068 ctx_priv->st1_addexp); in fsl_easrc_runtime_resume()
2072 ret = fsl_easrc_write_pf_coeff_mem(easrc, i, in fsl_easrc_runtime_resume()
2073 ctx_priv->st2_coeff, in fsl_easrc_runtime_resume()
2074 ctx_priv->st2_num_taps, in fsl_easrc_runtime_resume()
2075 ctx_priv->st2_addexp); in fsl_easrc_runtime_resume()
2084 clk_disable_unprepare(easrc->mem_clk); in fsl_easrc_runtime_resume()
2098 .name = "fsl-easrc",
2105 MODULE_DESCRIPTION("NXP Enhanced Asynchronous Sample Rate (eASRC) driver");