2  * ALSA SoC Synopsys I2S Audio Layer
47 			i2s_write_reg(dev->i2s_base, TER(i), 0);  in i2s_disable_channels()
50 			i2s_write_reg(dev->i2s_base, RER(i), 0);  in i2s_disable_channels()
60 			i2s_read_reg(dev->i2s_base, TOR(i));  in i2s_clear_irqs()
63 			i2s_read_reg(dev->i2s_base, ROR(i));  in i2s_clear_irqs()
74 			irq = i2s_read_reg(dev->i2s_base, IMR(i));  in i2s_disable_irqs()
75 			i2s_write_reg(dev->i2s_base, IMR(i), irq | 0x30);  in i2s_disable_irqs()
79 			irq = i2s_read_reg(dev->i2s_base, IMR(i));  in i2s_disable_irqs()
80 			i2s_write_reg(dev->i2s_base, IMR(i), irq | 0x03);  in i2s_disable_irqs()
92 			irq = i2s_read_reg(dev->i2s_base, IMR(i));  in i2s_enable_irqs()
93 			i2s_write_reg(dev->i2s_base, IMR(i), irq & ~0x30);  in i2s_enable_irqs()
97 			irq = i2s_read_reg(dev->i2s_base, IMR(i));  in i2s_enable_irqs()
98 			i2s_write_reg(dev->i2s_base, IMR(i), irq & ~0x03);  in i2s_enable_irqs()
111 		isr[i] = i2s_read_reg(dev->i2s_base, ISR(i));  in i2s_irq_handler()
121 		if ((isr[i] & ISR_TXFE) && (i == 0) && dev->use_pio) {  in i2s_irq_handler()
130 		if ((isr[i] & ISR_RXDA) && (i == 0) && dev->use_pio) {  in i2s_irq_handler()
137 			dev_err_ratelimited(dev->dev, "TX overrun (ch_id=%d)\n", i);  in i2s_irq_handler()
143 			dev_err_ratelimited(dev->dev, "RX overrun (ch_id=%d)\n", i);  in i2s_irq_handler()
156 	u32 dma_reg = i2s_read_reg(dev->i2s_base, I2S_DMACR);  in i2s_enable_dma()
164 	i2s_write_reg(dev->i2s_base, I2S_DMACR, dma_reg);  in i2s_enable_dma()
169 	u32 dma_reg = i2s_read_reg(dev->i2s_base, I2S_DMACR);  in i2s_disable_dma()
174 		i2s_write_reg(dev->i2s_base, I2S_RTXDMA, 1);  in i2s_disable_dma()
177 		i2s_write_reg(dev->i2s_base, I2S_RRXDMA, 1);  in i2s_disable_dma()
179 	i2s_write_reg(dev->i2s_base, I2S_DMACR, dma_reg);  in i2s_disable_dma()
185 	struct i2s_clk_config_data *config = &dev->config;  in i2s_start()
189 	if (dev->tdm_slots) {  in i2s_start()
190 		reg |= (dev->tdm_slots - 1) << IER_TDM_SLOTS_SHIFT;  in i2s_start()
192 		reg |= dev->frame_offset << IER_FRAME_OFF_SHIFT;  in i2s_start()
195 	i2s_write_reg(dev->i2s_base, IER, reg);  in i2s_start()
197 	if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)  in i2s_start()
198 		i2s_write_reg(dev->i2s_base, ITER, 1);  in i2s_start()
200 		i2s_write_reg(dev->i2s_base, IRER, 1);  in i2s_start()
202 	/* I2S needs to enable IRQ to make a handshake with DMAC on the JH7110 SoC */  in i2s_start()
203 	if (dev->use_pio || dev->is_jh7110)  in i2s_start()
204 		i2s_enable_irqs(dev, substream->stream, config->chan_nr);  in i2s_start()
206 		i2s_enable_dma(dev, substream->stream);  in i2s_start()
208 	i2s_write_reg(dev->i2s_base, CER, 1);  in i2s_start()
215 	i2s_clear_irqs(dev, substream->stream);  in i2s_stop()
216 	if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)  in i2s_stop()
217 		i2s_write_reg(dev->i2s_base, ITER, 0);  in i2s_stop()
219 		i2s_write_reg(dev->i2s_base, IRER, 0);  in i2s_stop()
221 	if (dev->use_pio || dev->is_jh7110)  in i2s_stop()
222 		i2s_disable_irqs(dev, substream->stream, 8);  in i2s_stop()
224 		i2s_disable_dma(dev, substream->stream);  in i2s_stop()
226 	if (!dev->active) {  in i2s_stop()
227 		i2s_write_reg(dev->i2s_base, CER, 0);  in i2s_stop()
228 		i2s_write_reg(dev->i2s_base, IER, 0);  in i2s_stop()
237 	if (dev->is_jh7110) {  in dw_i2s_startup()
239 		struct snd_soc_dai_link *dai_link = rtd->dai_link;  in dw_i2s_startup()
241 		dai_link->trigger_stop = SND_SOC_TRIGGER_ORDER_LDC;  in dw_i2s_startup()
250 	struct i2s_clk_config_data *config = &dev->config;  in dw_i2s_config()
255 	for (ch_reg = 0; ch_reg < (config->chan_nr / 2); ch_reg++) {  in dw_i2s_config()
257 			i2s_write_reg(dev->i2s_base, TCR(ch_reg),  in dw_i2s_config()
258 				      dev->xfer_resolution);  in dw_i2s_config()
259 			i2s_write_reg(dev->i2s_base, TFCR(ch_reg),  in dw_i2s_config()
260 				      dev->fifo_th - 1);  in dw_i2s_config()
261 			i2s_write_reg(dev->i2s_base, TER(ch_reg), TER_TXCHEN |  in dw_i2s_config()
262 				      dev->tdm_mask << TER_TXSLOT_SHIFT);  in dw_i2s_config()
264 			i2s_write_reg(dev->i2s_base, RCR(ch_reg),  in dw_i2s_config()
265 				      dev->xfer_resolution);  in dw_i2s_config()
266 			i2s_write_reg(dev->i2s_base, RFCR(ch_reg),  in dw_i2s_config()
267 				      dev->fifo_th - 1);  in dw_i2s_config()
268 			i2s_write_reg(dev->i2s_base, RER(ch_reg), RER_RXCHEN |  in dw_i2s_config()
269 				      dev->tdm_mask << RER_RXSLOT_SHIFT);  in dw_i2s_config()
279 	struct i2s_clk_config_data *config = &dev->config;  in dw_i2s_hw_params()
284 		config->data_width = 16;  in dw_i2s_hw_params()
285 		dev->ccr = 0x00;  in dw_i2s_hw_params()
286 		dev->xfer_resolution = 0x02;  in dw_i2s_hw_params()
290 		config->data_width = 24;  in dw_i2s_hw_params()
291 		dev->ccr = 0x08;  in dw_i2s_hw_params()
292 		dev->xfer_resolution = 0x04;  in dw_i2s_hw_params()
296 		config->data_width = 32;  in dw_i2s_hw_params()
297 		dev->ccr = 0x10;  in dw_i2s_hw_params()
298 		dev->xfer_resolution = 0x05;  in dw_i2s_hw_params()
302 		dev_err(dev->dev, "designware-i2s: unsupported PCM fmt");  in dw_i2s_hw_params()
303 		return -EINVAL;  in dw_i2s_hw_params()
306 	if (dev->tdm_slots)  in dw_i2s_hw_params()
307 		config->data_width = 32;  in dw_i2s_hw_params()
309 	config->chan_nr = params_channels(params);  in dw_i2s_hw_params()
311 	switch (config->chan_nr) {  in dw_i2s_hw_params()
318 		dev_err(dev->dev, "channel not supported\n");  in dw_i2s_hw_params()
319 		return -EINVAL;  in dw_i2s_hw_params()
322 	dw_i2s_config(dev, substream->stream);  in dw_i2s_hw_params()
324 	i2s_write_reg(dev->i2s_base, CCR, dev->ccr);  in dw_i2s_hw_params()
326 	config->sample_rate = params_rate(params);  in dw_i2s_hw_params()
328 	if (dev->capability & DW_I2S_MASTER) {  in dw_i2s_hw_params()
329 		if (dev->i2s_clk_cfg) {  in dw_i2s_hw_params()
330 			ret = dev->i2s_clk_cfg(config);  in dw_i2s_hw_params()
332 				dev_err(dev->dev, "runtime audio clk config fail\n");  in dw_i2s_hw_params()
336 			u32 bitclk = config->sample_rate *  in dw_i2s_hw_params()
337 					config->data_width * 2;  in dw_i2s_hw_params()
339 			ret = clk_set_rate(dev->clk, bitclk);  in dw_i2s_hw_params()
341 				dev_err(dev->dev, "Can't set I2S clock rate: %d\n",  in dw_i2s_hw_params()
355 	if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)  in dw_i2s_prepare()
356 		i2s_write_reg(dev->i2s_base, TXFFR, 1);  in dw_i2s_prepare()
358 		i2s_write_reg(dev->i2s_base, RXFFR, 1);  in dw_i2s_prepare()
373 		dev->active++;  in dw_i2s_trigger()
380 		dev->active--;  in dw_i2s_trigger()
384 		ret = -EINVAL;  in dw_i2s_trigger()
397 		if (dev->capability & DW_I2S_SLAVE)  in dw_i2s_set_fmt()
400 			ret = -EINVAL;  in dw_i2s_set_fmt()
403 		if (dev->capability & DW_I2S_MASTER)  in dw_i2s_set_fmt()
406 			ret = -EINVAL;  in dw_i2s_set_fmt()
410 		ret = -EINVAL;  in dw_i2s_set_fmt()
413 		dev_dbg(dev->dev, "dwc : Invalid clock provider format\n");  in dw_i2s_set_fmt()
414 		ret = -EINVAL;  in dw_i2s_set_fmt()
424 		dev->frame_offset = 1;  in dw_i2s_set_fmt()
427 		dev->frame_offset = 0;  in dw_i2s_set_fmt()
430 		dev_err(dev->dev, "DAI format unsupported");  in dw_i2s_set_fmt()
431 		return -EINVAL;  in dw_i2s_set_fmt()
443 		return -EINVAL;  in dw_i2s_set_tdm_slot()
446 		return -EINVAL;  in dw_i2s_set_tdm_slot()
449 		return -EINVAL;  in dw_i2s_set_tdm_slot()
452 		return -EINVAL;  in dw_i2s_set_tdm_slot()
454 	dev->tdm_slots = slots;  in dw_i2s_set_tdm_slot()
455 	dev->tdm_mask = rx_mask;  in dw_i2s_set_tdm_slot()
457 	dev->l_reg = RSLOT_TSLOT(ffs(rx_mask) - 1);  in dw_i2s_set_tdm_slot()
458 	dev->r_reg = RSLOT_TSLOT(fls(rx_mask) - 1);  in dw_i2s_set_tdm_slot()
467 	snd_soc_dai_init_dma_data(dai, &dev->play_dma_data, &dev->capture_dma_data);  in dw_i2s_dai_probe()
486 	if (dw_dev->capability & DW_I2S_MASTER)  in dw_i2s_runtime_suspend()
487 		clk_disable(dw_dev->clk);  in dw_i2s_runtime_suspend()
496 	if (dw_dev->capability & DW_I2S_MASTER) {  in dw_i2s_runtime_resume()
497 		ret = clk_enable(dw_dev->clk);  in dw_i2s_runtime_resume()
508 	if (dev->capability & DW_I2S_MASTER)  in dw_i2s_suspend()
509 		clk_disable(dev->clk);  in dw_i2s_suspend()
519 	if (dev->capability & DW_I2S_MASTER) {  in dw_i2s_resume()
520 		ret = clk_enable(dev->clk);  in dw_i2s_resume()
540 	.name			= "dw-i2s",
548  * defined in the I2S block's configuration in terms of sound system
550  * according to the number of configuration bits describing an I2S
554 /* Maximum bit resolution of a channel - not uniformly spaced */
585 	 * the I2S block's configuration.  in dw_configure_dai()
587 	u32 comp1 = i2s_read_reg(dev->i2s_base, dev->i2s_reg_comp1);  in dw_configure_dai()
588 	u32 comp2 = i2s_read_reg(dev->i2s_base, dev->i2s_reg_comp2);  in dw_configure_dai()
592 	if (dev->capability & DWC_I2S_RECORD &&  in dw_configure_dai()
593 			dev->quirks & DW_I2S_QUIRK_COMP_PARAM1)  in dw_configure_dai()
596 	if (dev->capability & DWC_I2S_PLAY &&  in dw_configure_dai()
597 			dev->quirks & DW_I2S_QUIRK_COMP_PARAM1)  in dw_configure_dai()
601 		dev_dbg(dev->dev, " designware: play supported\n");  in dw_configure_dai()
604 			return -EINVAL;  in dw_configure_dai()
605 		if (dev->quirks & DW_I2S_QUIRK_16BIT_IDX_OVERRIDE)  in dw_configure_dai()
607 		dw_i2s_dai->playback.channels_min = MIN_CHANNEL_NUM;  in dw_configure_dai()
608 		dw_i2s_dai->playback.channels_max =  in dw_configure_dai()
610 		dw_i2s_dai->playback.formats = formats[idx];  in dw_configure_dai()
611 		dw_i2s_dai->playback.rates = rates;  in dw_configure_dai()
615 		dev_dbg(dev->dev, "designware: record supported\n");  in dw_configure_dai()
618 			return -EINVAL;  in dw_configure_dai()
619 		if (dev->quirks & DW_I2S_QUIRK_16BIT_IDX_OVERRIDE)  in dw_configure_dai()
621 		dw_i2s_dai->capture.channels_min = MIN_CHANNEL_NUM;  in dw_configure_dai()
622 		dw_i2s_dai->capture.channels_max =  in dw_configure_dai()
624 		dw_i2s_dai->capture.formats = formats[idx];  in dw_configure_dai()
625 		dw_i2s_dai->capture.rates = rates;  in dw_configure_dai()
629 		dev_dbg(dev->dev, "designware: i2s master mode supported\n");  in dw_configure_dai()
630 		dev->capability |= DW_I2S_MASTER;  in dw_configure_dai()
632 		dev_dbg(dev->dev, "designware: i2s slave mode supported\n");  in dw_configure_dai()
633 		dev->capability |= DW_I2S_SLAVE;  in dw_configure_dai()
636 	dev->fifo_th = fifo_depth / 2;  in dw_configure_dai()
645 	u32 comp1 = i2s_read_reg(dev->i2s_base, dev->i2s_reg_comp1);  in dw_configure_dai_by_pd()
650 		return -EINVAL;  in dw_configure_dai_by_pd()
652 	ret = dw_configure_dai(dev, dw_i2s_dai, pdata->snd_rates);  in dw_configure_dai_by_pd()
656 	if (dev->quirks & DW_I2S_QUIRK_16BIT_IDX_OVERRIDE)  in dw_configure_dai_by_pd()
659 	if (dev->is_jh7110) {  in dw_configure_dai_by_pd()
661 		u32 comp2 = i2s_read_reg(dev->i2s_base, I2S_COMP_PARAM_2);  in dw_configure_dai_by_pd()
666 			dev->play_dma_data.dt.addr = res->start + I2S_TXDMA;  in dw_configure_dai_by_pd()
667 			dev->play_dma_data.dt.fifo_size = dev->fifo_th * 2 *  in dw_configure_dai_by_pd()
669 			dev->play_dma_data.dt.maxburst = 16;  in dw_configure_dai_by_pd()
673 			dev->capture_dma_data.dt.addr = res->start + I2S_RXDMA;  in dw_configure_dai_by_pd()
674 			dev->capture_dma_data.dt.fifo_size = dev->fifo_th * 2 *  in dw_configure_dai_by_pd()
676 			dev->capture_dma_data.dt.maxburst = 16;  in dw_configure_dai_by_pd()
680 		dev->play_dma_data.pd.data = pdata->play_dma_data;  in dw_configure_dai_by_pd()
681 		dev->capture_dma_data.pd.data = pdata->capture_dma_data;  in dw_configure_dai_by_pd()
682 		dev->play_dma_data.pd.addr = res->start + I2S_TXDMA;  in dw_configure_dai_by_pd()
683 		dev->capture_dma_data.pd.addr = res->start + I2S_RXDMA;  in dw_configure_dai_by_pd()
684 		dev->play_dma_data.pd.max_burst = 16;  in dw_configure_dai_by_pd()
685 		dev->capture_dma_data.pd.max_burst = 16;  in dw_configure_dai_by_pd()
686 		dev->play_dma_data.pd.addr_width = bus_widths[idx];  in dw_configure_dai_by_pd()
687 		dev->capture_dma_data.pd.addr_width = bus_widths[idx];  in dw_configure_dai_by_pd()
688 		dev->play_dma_data.pd.filter = pdata->filter;  in dw_configure_dai_by_pd()
689 		dev->capture_dma_data.pd.filter = pdata->filter;  in dw_configure_dai_by_pd()
699 	u32 comp1 = i2s_read_reg(dev->i2s_base, I2S_COMP_PARAM_1);  in dw_configure_dai_by_dt()
700 	u32 comp2 = i2s_read_reg(dev->i2s_base, I2S_COMP_PARAM_2);  in dw_configure_dai_by_dt()
712 		dev->capability |= DWC_I2S_PLAY;  in dw_configure_dai_by_dt()
713 		dev->play_dma_data.dt.addr = res->start + I2S_TXDMA;  in dw_configure_dai_by_dt()
714 		dev->play_dma_data.dt.fifo_size = fifo_depth *  in dw_configure_dai_by_dt()
716 		dev->play_dma_data.dt.maxburst = 16;  in dw_configure_dai_by_dt()
721 		dev->capability |= DWC_I2S_RECORD;  in dw_configure_dai_by_dt()
722 		dev->capture_dma_data.dt.addr = res->start + I2S_RXDMA;  in dw_configure_dai_by_dt()
723 		dev->capture_dma_data.dt.fifo_size = fifo_depth *  in dw_configure_dai_by_dt()
725 		dev->capture_dma_data.dt.maxburst = 16;  in dw_configure_dai_by_dt()
743 	struct reset_control *resets = devm_reset_control_array_get_exclusive(dev->dev);  in jh7110_i2s_crg_master_init()
752 		return dev_err_probe(dev->dev, PTR_ERR(resets), "failed to get i2s resets\n");  in jh7110_i2s_crg_master_init()
754 	ret = clk_bulk_get(dev->dev, ARRAY_SIZE(clks), clks);  in jh7110_i2s_crg_master_init()
756 		return dev_err_probe(dev->dev, ret, "failed to get i2s clocks\n");  in jh7110_i2s_crg_master_init()
790 	dev->is_jh7110 = true;  in jh7110_i2s_crg_master_init()
817 	struct reset_control *resets = devm_reset_control_array_get_exclusive(dev->dev);  in jh7110_i2s_crg_slave_init()
830 		return dev_err_probe(dev->dev, PTR_ERR(resets), "failed to get i2s resets\n");  in jh7110_i2s_crg_slave_init()
832 	ret = clk_bulk_get(dev->dev, ARRAY_SIZE(clks), clks);  in jh7110_i2s_crg_slave_init()
834 		return dev_err_probe(dev->dev, ret, "failed to get i2s clocks\n");  in jh7110_i2s_crg_slave_init()
878 	dev->is_jh7110 = true;  in jh7110_i2s_crg_slave_init()
897 	regmap = syscon_regmap_lookup_by_phandle_args(dev->dev->of_node,  in jh7110_i2srx_crg_init()
901 		return dev_err_probe(dev->dev, PTR_ERR(regmap), "getting the regmap failed\n");  in jh7110_i2srx_crg_init()
912 	u32 bclk_rate = config->sample_rate * 64;  in jh7110_i2stx0_clk_cfg()
914 	return clk_set_rate(dev->clk, bclk_rate);  in jh7110_i2stx0_clk_cfg()
920 	const struct i2s_platform_data *pdata = pdev->dev.platform_data;  in dw_i2s_probe()
927 	dev = devm_kzalloc(&pdev->dev, sizeof(*dev), GFP_KERNEL);  in dw_i2s_probe()
929 		return -ENOMEM;  in dw_i2s_probe()
931 	dw_i2s_dai = devm_kzalloc(&pdev->dev, sizeof(*dw_i2s_dai), GFP_KERNEL);  in dw_i2s_probe()
933 		return -ENOMEM;  in dw_i2s_probe()
935 	dw_i2s_dai->ops = &dw_i2s_dai_ops;  in dw_i2s_probe()
937 	dev->i2s_base = devm_platform_get_and_ioremap_resource(pdev, 0, &res);  in dw_i2s_probe()
938 	if (IS_ERR(dev->i2s_base))  in dw_i2s_probe()
939 		return PTR_ERR(dev->i2s_base);  in dw_i2s_probe()
941 	dev->dev = &pdev->dev;  in dw_i2s_probe()
942 	dev->is_jh7110 = false;  in dw_i2s_probe()
944 		if (pdata->i2s_pd_init) {  in dw_i2s_probe()
945 			ret = pdata->i2s_pd_init(dev);  in dw_i2s_probe()
951 	if (!dev->is_jh7110) {  in dw_i2s_probe()
952 		dev->reset = devm_reset_control_array_get_optional_shared(&pdev->dev);  in dw_i2s_probe()
953 		if (IS_ERR(dev->reset))  in dw_i2s_probe()
954 			return PTR_ERR(dev->reset);  in dw_i2s_probe()
956 		ret = reset_control_deassert(dev->reset);  in dw_i2s_probe()
963 		ret = devm_request_irq(&pdev->dev, irq, i2s_irq_handler, 0,  in dw_i2s_probe()
964 				pdev->name, dev);  in dw_i2s_probe()
966 			dev_err(&pdev->dev, "failed to request irq\n");  in dw_i2s_probe()
971 	dev->i2s_reg_comp1 = I2S_COMP_PARAM_1;  in dw_i2s_probe()
972 	dev->i2s_reg_comp2 = I2S_COMP_PARAM_2;  in dw_i2s_probe()
974 		dev->capability = pdata->cap;  in dw_i2s_probe()
976 		dev->quirks = pdata->quirks;  in dw_i2s_probe()
977 		if (dev->quirks & DW_I2S_QUIRK_COMP_REG_OFFSET) {  in dw_i2s_probe()
978 			dev->i2s_reg_comp1 = pdata->i2s_reg_comp1;  in dw_i2s_probe()
979 			dev->i2s_reg_comp2 = pdata->i2s_reg_comp2;  in dw_i2s_probe()
989 	if (dev->capability & DW_I2S_MASTER) {  in dw_i2s_probe()
991 			dev->i2s_clk_cfg = pdata->i2s_clk_cfg;  in dw_i2s_probe()
992 			if (!dev->i2s_clk_cfg) {  in dw_i2s_probe()
993 				dev_err(&pdev->dev, "no clock configure method\n");  in dw_i2s_probe()
994 				ret = -ENODEV;  in dw_i2s_probe()
998 		dev->clk = devm_clk_get_enabled(&pdev->dev, clk_id);  in dw_i2s_probe()
1000 		if (IS_ERR(dev->clk)) {  in dw_i2s_probe()
1001 			ret = PTR_ERR(dev->clk);  in dw_i2s_probe()
1006 	dev_set_drvdata(&pdev->dev, dev);  in dw_i2s_probe()
1007 	ret = devm_snd_soc_register_component(&pdev->dev, &dw_i2s_component,  in dw_i2s_probe()
1010 		dev_err(&pdev->dev, "not able to register dai\n");  in dw_i2s_probe()
1014 	if (!pdata || dev->is_jh7110) {  in dw_i2s_probe()
1017 			dev->use_pio = true;  in dw_i2s_probe()
1018 			dev->l_reg = LRBR_LTHR(0);  in dw_i2s_probe()
1019 			dev->r_reg = RRBR_RTHR(0);  in dw_i2s_probe()
1021 			ret = devm_snd_dmaengine_pcm_register(&pdev->dev, NULL,  in dw_i2s_probe()
1023 			dev->use_pio = false;  in dw_i2s_probe()
1027 			dev_err(&pdev->dev, "could not register pcm: %d\n",  in dw_i2s_probe()
1033 	pm_runtime_enable(&pdev->dev);  in dw_i2s_probe()
1037 	reset_control_assert(dev->reset);  in dw_i2s_probe()
1043 	struct dw_i2s_dev *dev = dev_get_drvdata(&pdev->dev);  in dw_i2s_remove()
1045 	reset_control_assert(dev->reset);  in dw_i2s_remove()
1046 	pm_runtime_disable(&pdev->dev);  in dw_i2s_remove()
1076 	{ .compatible = "snps,designware-i2s",	 },
1077 	{ .compatible = "starfive,jh7110-i2stx0", .data = &jh7110_i2stx0_data, },
1078 	{ .compatible = "starfive,jh7110-i2stx1", .data = &jh7110_i2stx1_data,},
1079 	{ .compatible = "starfive,jh7110-i2srx", .data = &jh7110_i2srx_data,},
1094 		.name	= "designware-i2s",
1103 MODULE_DESCRIPTION("DESIGNWARE I2S SoC Interface");