Lines Matching +full:spk +full:- +full:shutdown
1 // SPDX-License-Identifier: GPL-2.0-only
3 * wm8983.c -- WM8983 ALSA SoC Audio driver
29 { 0x01, 0x0000 }, /* R1 - Power management 1 */
30 { 0x02, 0x0000 }, /* R2 - Power management 2 */
31 { 0x03, 0x0000 }, /* R3 - Power management 3 */
32 { 0x04, 0x0050 }, /* R4 - Audio Interface */
33 { 0x05, 0x0000 }, /* R5 - Companding control */
34 { 0x06, 0x0140 }, /* R6 - Clock Gen control */
35 { 0x07, 0x0000 }, /* R7 - Additional control */
36 { 0x08, 0x0000 }, /* R8 - GPIO Control */
37 { 0x09, 0x0000 }, /* R9 - Jack Detect Control 1 */
38 { 0x0A, 0x0000 }, /* R10 - DAC Control */
39 { 0x0B, 0x00FF }, /* R11 - Left DAC digital Vol */
40 { 0x0C, 0x00FF }, /* R12 - Right DAC digital vol */
41 { 0x0D, 0x0000 }, /* R13 - Jack Detect Control 2 */
42 { 0x0E, 0x0100 }, /* R14 - ADC Control */
43 { 0x0F, 0x00FF }, /* R15 - Left ADC Digital Vol */
44 { 0x10, 0x00FF }, /* R16 - Right ADC Digital Vol */
45 { 0x12, 0x012C }, /* R18 - EQ1 - low shelf */
46 { 0x13, 0x002C }, /* R19 - EQ2 - peak 1 */
47 { 0x14, 0x002C }, /* R20 - EQ3 - peak 2 */
48 { 0x15, 0x002C }, /* R21 - EQ4 - peak 3 */
49 { 0x16, 0x002C }, /* R22 - EQ5 - high shelf */
50 { 0x18, 0x0032 }, /* R24 - DAC Limiter 1 */
51 { 0x19, 0x0000 }, /* R25 - DAC Limiter 2 */
52 { 0x1B, 0x0000 }, /* R27 - Notch Filter 1 */
53 { 0x1C, 0x0000 }, /* R28 - Notch Filter 2 */
54 { 0x1D, 0x0000 }, /* R29 - Notch Filter 3 */
55 { 0x1E, 0x0000 }, /* R30 - Notch Filter 4 */
56 { 0x20, 0x0038 }, /* R32 - ALC control 1 */
57 { 0x21, 0x000B }, /* R33 - ALC control 2 */
58 { 0x22, 0x0032 }, /* R34 - ALC control 3 */
59 { 0x23, 0x0000 }, /* R35 - Noise Gate */
60 { 0x24, 0x0008 }, /* R36 - PLL N */
61 { 0x25, 0x000C }, /* R37 - PLL K 1 */
62 { 0x26, 0x0093 }, /* R38 - PLL K 2 */
63 { 0x27, 0x00E9 }, /* R39 - PLL K 3 */
64 { 0x29, 0x0000 }, /* R41 - 3D control */
65 { 0x2A, 0x0000 }, /* R42 - OUT4 to ADC */
66 { 0x2B, 0x0000 }, /* R43 - Beep control */
67 { 0x2C, 0x0033 }, /* R44 - Input ctrl */
68 { 0x2D, 0x0010 }, /* R45 - Left INP PGA gain ctrl */
69 { 0x2E, 0x0010 }, /* R46 - Right INP PGA gain ctrl */
70 { 0x2F, 0x0100 }, /* R47 - Left ADC BOOST ctrl */
71 { 0x30, 0x0100 }, /* R48 - Right ADC BOOST ctrl */
72 { 0x31, 0x0002 }, /* R49 - Output ctrl */
73 { 0x32, 0x0001 }, /* R50 - Left mixer ctrl */
74 { 0x33, 0x0001 }, /* R51 - Right mixer ctrl */
75 { 0x34, 0x0039 }, /* R52 - LOUT1 (HP) volume ctrl */
76 { 0x35, 0x0039 }, /* R53 - ROUT1 (HP) volume ctrl */
77 { 0x36, 0x0039 }, /* R54 - LOUT2 (SPK) volume ctrl */
78 { 0x37, 0x0039 }, /* R55 - ROUT2 (SPK) volume ctrl */
79 { 0x38, 0x0001 }, /* R56 - OUT3 mixer ctrl */
80 { 0x39, 0x0001 }, /* R57 - OUT4 (MONO) mix ctrl */
81 { 0x3D, 0x0000 }, /* R61 - BIAS CTRL */
129 static const DECLARE_TLV_DB_SCALE(dac_tlv, -12700, 50, 1);
130 static const DECLARE_TLV_DB_SCALE(adc_tlv, -12700, 50, 1);
131 static const DECLARE_TLV_DB_SCALE(out_tlv, -5700, 100, 0);
132 static const DECLARE_TLV_DB_SCALE(lim_thresh_tlv, -600, 100, 0);
134 static const DECLARE_TLV_DB_SCALE(alc_min_tlv, -1200, 600, 0);
135 static const DECLARE_TLV_DB_SCALE(alc_max_tlv, -675, 600, 0);
136 static const DECLARE_TLV_DB_SCALE(alc_tar_tlv, -2250, 150, 0);
137 static const DECLARE_TLV_DB_SCALE(pga_vol_tlv, -1200, 75, 0);
138 static const DECLARE_TLV_DB_SCALE(boost_tlv, -1200, 300, 1);
139 static const DECLARE_TLV_DB_SCALE(eq_tlv, -1200, 100, 0);
140 static const DECLARE_TLV_DB_SCALE(aux_tlv, -1500, 300, 0);
141 static const DECLARE_TLV_DB_SCALE(bypass_tlv, -1500, 300, 0);
497 ucontrol->value.enumerated.item[0] = 1; in eqmode_get()
499 ucontrol->value.enumerated.item[0] = 0; in eqmode_get()
511 if (ucontrol->value.enumerated.item[0] != 0 in eqmode_put()
512 && ucontrol->value.enumerated.item[0] != 1) in eqmode_put()
513 return -EINVAL; in eqmode_put()
518 if (!ucontrol->value.enumerated.item[0]) in eqmode_put()
522 if (ucontrol->value.enumerated.item[0]) in eqmode_put()
537 ucontrol->value.enumerated.item[0] in eqmode_put()
562 struct snd_soc_component *component = dai->component; in wm8983_dac_mute()
571 struct snd_soc_component *component = dai->component; in wm8983_set_fmt()
589 dev_err(dai->dev, "Unknown dai format\n"); in wm8983_set_fmt()
590 return -EINVAL; in wm8983_set_fmt()
604 dev_err(dai->dev, "Unknown master/slave configuration\n"); in wm8983_set_fmt()
605 return -EINVAL; in wm8983_set_fmt()
615 dev_err(dai->dev, "DSP A/B modes are not supported\n"); in wm8983_set_fmt()
616 return -EINVAL; in wm8983_set_fmt()
635 dev_err(dai->dev, "Unknown polarity configuration\n"); in wm8983_set_fmt()
636 return -EINVAL; in wm8983_set_fmt()
651 struct snd_soc_component *component = dai->component; in wm8983_hw_params()
660 dev_err(component->dev, "Failed to convert params to bclk: %d\n", ret); in wm8983_hw_params()
664 wm8983->bclk = ret; in wm8983_hw_params()
680 dev_err(dai->dev, "Unsupported word length %u\n", in wm8983_hw_params()
682 return -EINVAL; in wm8983_hw_params()
693 srate_best = abs(srates[0] - params_rate(params)); in wm8983_hw_params()
695 if (abs(srates[i] - params_rate(params)) >= srate_best) in wm8983_hw_params()
698 srate_best = abs(srates[i] - params_rate(params)); in wm8983_hw_params()
701 dev_dbg(dai->dev, "Selected SRATE = %d\n", srates[srate_idx]); in wm8983_hw_params()
705 dev_dbg(dai->dev, "Target BCLK = %uHz\n", wm8983->bclk); in wm8983_hw_params()
706 dev_dbg(dai->dev, "SYSCLK = %uHz\n", wm8983->sysclk); in wm8983_hw_params()
709 if (wm8983->sysclk / params_rate(params) in wm8983_hw_params()
715 dev_err(dai->dev, "Unable to configure MCLK ratio %u/%u\n", in wm8983_hw_params()
716 wm8983->sysclk, params_rate(params)); in wm8983_hw_params()
717 return -EINVAL; in wm8983_hw_params()
720 dev_dbg(dai->dev, "MCLK ratio = %dfs\n", fs_ratios[i].ratio); in wm8983_hw_params()
725 tmp = (wm8983->sysclk / fs_ratios[i].div) * 10; in wm8983_hw_params()
727 if (wm8983->bclk == tmp / bclk_divs[i]) in wm8983_hw_params()
732 dev_err(dai->dev, "No matching BCLK divider found\n"); in wm8983_hw_params()
733 return -EINVAL; in wm8983_hw_params()
736 dev_dbg(dai->dev, "BCLK div = %d\n", i); in wm8983_hw_params()
756 pll_div->div2 = 0; in pll_factors()
760 pll_div->div2 = 1; in pll_factors()
767 return -EINVAL; in pll_factors()
769 pll_div->n = Ndiv; in pll_factors()
780 pll_div->k = K; in pll_factors()
792 component = dai->component; in wm8983_set_pll()
803 /* disable the PLL before re-programming it */ in wm8983_set_pll()
826 struct snd_soc_component *component = dai->component; in wm8983_set_sysclk()
839 dev_err(dai->dev, "Unknown clock source: %d\n", clk_id); in wm8983_set_sysclk()
840 return -EINVAL; in wm8983_set_sysclk()
843 wm8983->sysclk = freq; in wm8983_set_sysclk()
863 ret = regcache_sync(wm8983->regmap); in wm8983_set_bias_level()
865 dev_err(component->dev, "Failed to sync cache: %d\n", ret); in wm8983_set_bias_level()
868 /* enable anti-pop features */ in wm8983_set_bias_level()
872 /* enable thermal shutdown */ in wm8983_set_bias_level()
883 /* disable anti-pop features */ in wm8983_set_bias_level()
895 /* disable thermal shutdown */ in wm8983_set_bias_level()
920 dev_err(component->dev, "Failed to issue reset: %d\n", ret); in wm8983_probe()
958 .name = "wm8983-hifi",
1010 wm8983 = devm_kzalloc(&spi->dev, sizeof *wm8983, GFP_KERNEL); in wm8983_spi_probe()
1012 return -ENOMEM; in wm8983_spi_probe()
1014 wm8983->regmap = devm_regmap_init_spi(spi, &wm8983_regmap); in wm8983_spi_probe()
1015 if (IS_ERR(wm8983->regmap)) { in wm8983_spi_probe()
1016 ret = PTR_ERR(wm8983->regmap); in wm8983_spi_probe()
1017 dev_err(&spi->dev, "Failed to init regmap: %d\n", ret); in wm8983_spi_probe()
1023 ret = devm_snd_soc_register_component(&spi->dev, in wm8983_spi_probe()
1042 wm8983 = devm_kzalloc(&i2c->dev, sizeof *wm8983, GFP_KERNEL); in wm8983_i2c_probe()
1044 return -ENOMEM; in wm8983_i2c_probe()
1046 wm8983->regmap = devm_regmap_init_i2c(i2c, &wm8983_regmap); in wm8983_i2c_probe()
1047 if (IS_ERR(wm8983->regmap)) { in wm8983_i2c_probe()
1048 ret = PTR_ERR(wm8983->regmap); in wm8983_i2c_probe()
1049 dev_err(&i2c->dev, "Failed to init regmap: %d\n", ret); in wm8983_i2c_probe()
1055 ret = devm_snd_soc_register_component(&i2c->dev, in wm8983_i2c_probe()