Lines Matching +full:dsp +full:- +full:aif2 +full:- +full:lrclk
1 // SPDX-License-Identifier: GPL-2.0-only
3 * wm8962.c -- WM8962 ALSA SoC Audio driver
5 * Copyright 2010-2 Wolfson Microelectronics plc
60 int lrclk; member
98 regcache_mark_dirty(wm8962->regmap); \
113 { 0, 0x009F }, /* R0 - Left Input volume */
114 { 1, 0x049F }, /* R1 - Right Input volume */
115 { 2, 0x0000 }, /* R2 - HPOUTL volume */
116 { 3, 0x0000 }, /* R3 - HPOUTR volume */
118 { 5, 0x0018 }, /* R5 - ADC & DAC Control 1 */
119 { 6, 0x2008 }, /* R6 - ADC & DAC Control 2 */
120 { 7, 0x000A }, /* R7 - Audio Interface 0 */
121 { 8, 0x01E4 }, /* R8 - Clocking2 */
122 { 9, 0x0300 }, /* R9 - Audio Interface 1 */
123 { 10, 0x00C0 }, /* R10 - Left DAC volume */
124 { 11, 0x00C0 }, /* R11 - Right DAC volume */
126 { 14, 0x0040 }, /* R14 - Audio Interface 2 */
127 { 15, 0x6243 }, /* R15 - Software Reset */
129 { 17, 0x007B }, /* R17 - ALC1 */
130 { 18, 0x0000 }, /* R18 - ALC2 */
131 { 19, 0x1C32 }, /* R19 - ALC3 */
132 { 20, 0x3200 }, /* R20 - Noise Gate */
133 { 21, 0x00C0 }, /* R21 - Left ADC volume */
134 { 22, 0x00C0 }, /* R22 - Right ADC volume */
135 { 23, 0x0160 }, /* R23 - Additional control(1) */
136 { 24, 0x0000 }, /* R24 - Additional control(2) */
137 { 25, 0x0000 }, /* R25 - Pwr Mgmt (1) */
138 { 26, 0x0000 }, /* R26 - Pwr Mgmt (2) */
139 { 27, 0x0010 }, /* R27 - Additional Control (3) */
140 { 28, 0x0000 }, /* R28 - Anti-pop */
142 { 30, 0x005E }, /* R30 - Clocking 3 */
143 { 31, 0x0000 }, /* R31 - Input mixer control (1) */
144 { 32, 0x0145 }, /* R32 - Left input mixer volume */
145 { 33, 0x0145 }, /* R33 - Right input mixer volume */
146 { 34, 0x0009 }, /* R34 - Input mixer control (2) */
147 { 35, 0x0003 }, /* R35 - Input bias control */
148 { 37, 0x0008 }, /* R37 - Left input PGA control */
149 { 38, 0x0008 }, /* R38 - Right input PGA control */
151 { 40, 0x0000 }, /* R40 - SPKOUTL volume */
152 { 41, 0x0000 }, /* R41 - SPKOUTR volume */
154 { 49, 0x0010 }, /* R49 - Class D Control 1 */
155 { 51, 0x0003 }, /* R51 - Class D Control 2 */
157 { 56, 0x0506 }, /* R56 - Clocking 4 */
158 { 57, 0x0000 }, /* R57 - DAC DSP Mixing (1) */
159 { 58, 0x0000 }, /* R58 - DAC DSP Mixing (2) */
161 { 60, 0x0300 }, /* R60 - DC Servo 0 */
162 { 61, 0x0300 }, /* R61 - DC Servo 1 */
164 { 64, 0x0810 }, /* R64 - DC Servo 4 */
166 { 68, 0x001B }, /* R68 - Analogue PGA Bias */
167 { 69, 0x0000 }, /* R69 - Analogue HP 0 */
169 { 71, 0x01FB }, /* R71 - Analogue HP 2 */
170 { 72, 0x0000 }, /* R72 - Charge Pump 1 */
172 { 82, 0x0004 }, /* R82 - Charge Pump B */
174 { 87, 0x0000 }, /* R87 - Write Sequencer Control 1 */
176 { 90, 0x0000 }, /* R90 - Write Sequencer Control 2 */
178 { 93, 0x0000 }, /* R93 - Write Sequencer Control 3 */
179 { 94, 0x0000 }, /* R94 - Control Interface */
181 { 99, 0x0000 }, /* R99 - Mixer Enables */
182 { 100, 0x0000 }, /* R100 - Headphone Mixer (1) */
183 { 101, 0x0000 }, /* R101 - Headphone Mixer (2) */
184 { 102, 0x013F }, /* R102 - Headphone Mixer (3) */
185 { 103, 0x013F }, /* R103 - Headphone Mixer (4) */
187 { 105, 0x0000 }, /* R105 - Speaker Mixer (1) */
188 { 106, 0x0000 }, /* R106 - Speaker Mixer (2) */
189 { 107, 0x013F }, /* R107 - Speaker Mixer (3) */
190 { 108, 0x013F }, /* R108 - Speaker Mixer (4) */
191 { 109, 0x0003 }, /* R109 - Speaker Mixer (5) */
192 { 110, 0x0002 }, /* R110 - Beep Generator (1) */
194 { 115, 0x0006 }, /* R115 - Oscillator Trim (3) */
195 { 116, 0x0026 }, /* R116 - Oscillator Trim (4) */
197 { 119, 0x0000 }, /* R119 - Oscillator Trim (7) */
199 { 124, 0x0011 }, /* R124 - Analogue Clocking1 */
200 { 125, 0x004B }, /* R125 - Analogue Clocking2 */
201 { 126, 0x000D }, /* R126 - Analogue Clocking3 */
202 { 127, 0x0000 }, /* R127 - PLL Software Reset */
204 { 131, 0x0000 }, /* R131 - PLL 4 */
206 { 136, 0x0067 }, /* R136 - PLL 9 */
207 { 137, 0x001C }, /* R137 - PLL 10 */
208 { 138, 0x0071 }, /* R138 - PLL 11 */
209 { 139, 0x00C7 }, /* R139 - PLL 12 */
210 { 140, 0x0067 }, /* R140 - PLL 13 */
211 { 141, 0x0048 }, /* R141 - PLL 14 */
212 { 142, 0x0022 }, /* R142 - PLL 15 */
213 { 143, 0x0097 }, /* R143 - PLL 16 */
215 { 155, 0x000C }, /* R155 - FLL Control (1) */
216 { 156, 0x0039 }, /* R156 - FLL Control (2) */
217 { 157, 0x0180 }, /* R157 - FLL Control (3) */
219 { 159, 0x0032 }, /* R159 - FLL Control (5) */
220 { 160, 0x0018 }, /* R160 - FLL Control (6) */
221 { 161, 0x007D }, /* R161 - FLL Control (7) */
222 { 162, 0x0008 }, /* R162 - FLL Control (8) */
224 { 252, 0x0005 }, /* R252 - General test 1 */
226 { 256, 0x0000 }, /* R256 - DF1 */
227 { 257, 0x0000 }, /* R257 - DF2 */
228 { 258, 0x0000 }, /* R258 - DF3 */
229 { 259, 0x0000 }, /* R259 - DF4 */
230 { 260, 0x0000 }, /* R260 - DF5 */
231 { 261, 0x0000 }, /* R261 - DF6 */
232 { 262, 0x0000 }, /* R262 - DF7 */
234 { 264, 0x0000 }, /* R264 - LHPF1 */
235 { 265, 0x0000 }, /* R265 - LHPF2 */
237 { 268, 0x0000 }, /* R268 - THREED1 */
238 { 269, 0x0000 }, /* R269 - THREED2 */
239 { 270, 0x0000 }, /* R270 - THREED3 */
240 { 271, 0x0000 }, /* R271 - THREED4 */
242 { 276, 0x000C }, /* R276 - DRC 1 */
243 { 277, 0x0925 }, /* R277 - DRC 2 */
244 { 278, 0x0000 }, /* R278 - DRC 3 */
245 { 279, 0x0000 }, /* R279 - DRC 4 */
246 { 280, 0x0000 }, /* R280 - DRC 5 */
248 { 285, 0x0000 }, /* R285 - Tloopback */
250 { 335, 0x0004 }, /* R335 - EQ1 */
251 { 336, 0x6318 }, /* R336 - EQ2 */
252 { 337, 0x6300 }, /* R337 - EQ3 */
253 { 338, 0x0FCA }, /* R338 - EQ4 */
254 { 339, 0x0400 }, /* R339 - EQ5 */
255 { 340, 0x00D8 }, /* R340 - EQ6 */
256 { 341, 0x1EB5 }, /* R341 - EQ7 */
257 { 342, 0xF145 }, /* R342 - EQ8 */
258 { 343, 0x0B75 }, /* R343 - EQ9 */
259 { 344, 0x01C5 }, /* R344 - EQ10 */
260 { 345, 0x1C58 }, /* R345 - EQ11 */
261 { 346, 0xF373 }, /* R346 - EQ12 */
262 { 347, 0x0A54 }, /* R347 - EQ13 */
263 { 348, 0x0558 }, /* R348 - EQ14 */
264 { 349, 0x168E }, /* R349 - EQ15 */
265 { 350, 0xF829 }, /* R350 - EQ16 */
266 { 351, 0x07AD }, /* R351 - EQ17 */
267 { 352, 0x1103 }, /* R352 - EQ18 */
268 { 353, 0x0564 }, /* R353 - EQ19 */
269 { 354, 0x0559 }, /* R354 - EQ20 */
270 { 355, 0x4000 }, /* R355 - EQ21 */
271 { 356, 0x6318 }, /* R356 - EQ22 */
272 { 357, 0x6300 }, /* R357 - EQ23 */
273 { 358, 0x0FCA }, /* R358 - EQ24 */
274 { 359, 0x0400 }, /* R359 - EQ25 */
275 { 360, 0x00D8 }, /* R360 - EQ26 */
276 { 361, 0x1EB5 }, /* R361 - EQ27 */
277 { 362, 0xF145 }, /* R362 - EQ28 */
278 { 363, 0x0B75 }, /* R363 - EQ29 */
279 { 364, 0x01C5 }, /* R364 - EQ30 */
280 { 365, 0x1C58 }, /* R365 - EQ31 */
281 { 366, 0xF373 }, /* R366 - EQ32 */
282 { 367, 0x0A54 }, /* R367 - EQ33 */
283 { 368, 0x0558 }, /* R368 - EQ34 */
284 { 369, 0x168E }, /* R369 - EQ35 */
285 { 370, 0xF829 }, /* R370 - EQ36 */
286 { 371, 0x07AD }, /* R371 - EQ37 */
287 { 372, 0x1103 }, /* R372 - EQ38 */
288 { 373, 0x0564 }, /* R373 - EQ39 */
289 { 374, 0x0559 }, /* R374 - EQ40 */
290 { 375, 0x4000 }, /* R375 - EQ41 */
292 { 513, 0x0000 }, /* R513 - GPIO 2 */
293 { 514, 0x0000 }, /* R514 - GPIO 3 */
295 { 516, 0x8100 }, /* R516 - GPIO 5 */
296 { 517, 0x8100 }, /* R517 - GPIO 6 */
298 { 568, 0x0030 }, /* R568 - Interrupt Status 1 Mask */
299 { 569, 0xFFED }, /* R569 - Interrupt Status 2 Mask */
301 { 576, 0x0000 }, /* R576 - Interrupt Control */
303 { 584, 0x002D }, /* R584 - IRQ Debounce */
305 { 586, 0x0000 }, /* R586 - MICINT Source Pol */
307 { 768, 0x1C00 }, /* R768 - DSP2 Power Management */
309 { 8192, 0x0000 }, /* R8192 - DSP2 Instruction RAM 0 */
311 { 9216, 0x0030 }, /* R9216 - DSP2 Address RAM 2 */
312 { 9217, 0x0000 }, /* R9217 - DSP2 Address RAM 1 */
313 { 9218, 0x0000 }, /* R9218 - DSP2 Address RAM 0 */
315 { 12288, 0x0000 }, /* R12288 - DSP2 Data1 RAM 1 */
316 { 12289, 0x0000 }, /* R12289 - DSP2 Data1 RAM 0 */
318 { 13312, 0x0000 }, /* R13312 - DSP2 Data2 RAM 1 */
319 { 13313, 0x0000 }, /* R13313 - DSP2 Data2 RAM 0 */
321 { 14336, 0x0000 }, /* R14336 - DSP2 Data3 RAM 1 */
322 { 14337, 0x0000 }, /* R14337 - DSP2 Data3 RAM 0 */
324 { 15360, 0x000A }, /* R15360 - DSP2 Coeff RAM 0 */
326 { 16384, 0x0000 }, /* R16384 - RETUNEADC_SHARED_COEFF_1 */
327 { 16385, 0x0000 }, /* R16385 - RETUNEADC_SHARED_COEFF_0 */
328 { 16386, 0x0000 }, /* R16386 - RETUNEDAC_SHARED_COEFF_1 */
329 { 16387, 0x0000 }, /* R16387 - RETUNEDAC_SHARED_COEFF_0 */
330 { 16388, 0x0000 }, /* R16388 - SOUNDSTAGE_ENABLES_1 */
331 { 16389, 0x0000 }, /* R16389 - SOUNDSTAGE_ENABLES_0 */
333 { 16896, 0x0002 }, /* R16896 - HDBASS_AI_1 */
334 { 16897, 0xBD12 }, /* R16897 - HDBASS_AI_0 */
335 { 16898, 0x007C }, /* R16898 - HDBASS_AR_1 */
336 { 16899, 0x586C }, /* R16899 - HDBASS_AR_0 */
337 { 16900, 0x0053 }, /* R16900 - HDBASS_B_1 */
338 { 16901, 0x8121 }, /* R16901 - HDBASS_B_0 */
339 { 16902, 0x003F }, /* R16902 - HDBASS_K_1 */
340 { 16903, 0x8BD8 }, /* R16903 - HDBASS_K_0 */
341 { 16904, 0x0032 }, /* R16904 - HDBASS_N1_1 */
342 { 16905, 0xF52D }, /* R16905 - HDBASS_N1_0 */
343 { 16906, 0x0065 }, /* R16906 - HDBASS_N2_1 */
344 { 16907, 0xAC8C }, /* R16907 - HDBASS_N2_0 */
345 { 16908, 0x006B }, /* R16908 - HDBASS_N3_1 */
346 { 16909, 0xE087 }, /* R16909 - HDBASS_N3_0 */
347 { 16910, 0x0072 }, /* R16910 - HDBASS_N4_1 */
348 { 16911, 0x1483 }, /* R16911 - HDBASS_N4_0 */
349 { 16912, 0x0072 }, /* R16912 - HDBASS_N5_1 */
350 { 16913, 0x1483 }, /* R16913 - HDBASS_N5_0 */
351 { 16914, 0x0043 }, /* R16914 - HDBASS_X1_1 */
352 { 16915, 0x3525 }, /* R16915 - HDBASS_X1_0 */
353 { 16916, 0x0006 }, /* R16916 - HDBASS_X2_1 */
354 { 16917, 0x6A4A }, /* R16917 - HDBASS_X2_0 */
355 { 16918, 0x0043 }, /* R16918 - HDBASS_X3_1 */
356 { 16919, 0x6079 }, /* R16919 - HDBASS_X3_0 */
357 { 16920, 0x0008 }, /* R16920 - HDBASS_ATK_1 */
358 { 16921, 0x0000 }, /* R16921 - HDBASS_ATK_0 */
359 { 16922, 0x0001 }, /* R16922 - HDBASS_DCY_1 */
360 { 16923, 0x0000 }, /* R16923 - HDBASS_DCY_0 */
361 { 16924, 0x0059 }, /* R16924 - HDBASS_PG_1 */
362 { 16925, 0x999A }, /* R16925 - HDBASS_PG_0 */
364 { 17408, 0x0083 }, /* R17408 - HPF_C_1 */
365 { 17409, 0x98AD }, /* R17409 - HPF_C_0 */
367 { 17920, 0x007F }, /* R17920 - ADCL_RETUNE_C1_1 */
368 { 17921, 0xFFFF }, /* R17921 - ADCL_RETUNE_C1_0 */
369 { 17922, 0x0000 }, /* R17922 - ADCL_RETUNE_C2_1 */
370 { 17923, 0x0000 }, /* R17923 - ADCL_RETUNE_C2_0 */
371 { 17924, 0x0000 }, /* R17924 - ADCL_RETUNE_C3_1 */
372 { 17925, 0x0000 }, /* R17925 - ADCL_RETUNE_C3_0 */
373 { 17926, 0x0000 }, /* R17926 - ADCL_RETUNE_C4_1 */
374 { 17927, 0x0000 }, /* R17927 - ADCL_RETUNE_C4_0 */
375 { 17928, 0x0000 }, /* R17928 - ADCL_RETUNE_C5_1 */
376 { 17929, 0x0000 }, /* R17929 - ADCL_RETUNE_C5_0 */
377 { 17930, 0x0000 }, /* R17930 - ADCL_RETUNE_C6_1 */
378 { 17931, 0x0000 }, /* R17931 - ADCL_RETUNE_C6_0 */
379 { 17932, 0x0000 }, /* R17932 - ADCL_RETUNE_C7_1 */
380 { 17933, 0x0000 }, /* R17933 - ADCL_RETUNE_C7_0 */
381 { 17934, 0x0000 }, /* R17934 - ADCL_RETUNE_C8_1 */
382 { 17935, 0x0000 }, /* R17935 - ADCL_RETUNE_C8_0 */
383 { 17936, 0x0000 }, /* R17936 - ADCL_RETUNE_C9_1 */
384 { 17937, 0x0000 }, /* R17937 - ADCL_RETUNE_C9_0 */
385 { 17938, 0x0000 }, /* R17938 - ADCL_RETUNE_C10_1 */
386 { 17939, 0x0000 }, /* R17939 - ADCL_RETUNE_C10_0 */
387 { 17940, 0x0000 }, /* R17940 - ADCL_RETUNE_C11_1 */
388 { 17941, 0x0000 }, /* R17941 - ADCL_RETUNE_C11_0 */
389 { 17942, 0x0000 }, /* R17942 - ADCL_RETUNE_C12_1 */
390 { 17943, 0x0000 }, /* R17943 - ADCL_RETUNE_C12_0 */
391 { 17944, 0x0000 }, /* R17944 - ADCL_RETUNE_C13_1 */
392 { 17945, 0x0000 }, /* R17945 - ADCL_RETUNE_C13_0 */
393 { 17946, 0x0000 }, /* R17946 - ADCL_RETUNE_C14_1 */
394 { 17947, 0x0000 }, /* R17947 - ADCL_RETUNE_C14_0 */
395 { 17948, 0x0000 }, /* R17948 - ADCL_RETUNE_C15_1 */
396 { 17949, 0x0000 }, /* R17949 - ADCL_RETUNE_C15_0 */
397 { 17950, 0x0000 }, /* R17950 - ADCL_RETUNE_C16_1 */
398 { 17951, 0x0000 }, /* R17951 - ADCL_RETUNE_C16_0 */
399 { 17952, 0x0000 }, /* R17952 - ADCL_RETUNE_C17_1 */
400 { 17953, 0x0000 }, /* R17953 - ADCL_RETUNE_C17_0 */
401 { 17954, 0x0000 }, /* R17954 - ADCL_RETUNE_C18_1 */
402 { 17955, 0x0000 }, /* R17955 - ADCL_RETUNE_C18_0 */
403 { 17956, 0x0000 }, /* R17956 - ADCL_RETUNE_C19_1 */
404 { 17957, 0x0000 }, /* R17957 - ADCL_RETUNE_C19_0 */
405 { 17958, 0x0000 }, /* R17958 - ADCL_RETUNE_C20_1 */
406 { 17959, 0x0000 }, /* R17959 - ADCL_RETUNE_C20_0 */
407 { 17960, 0x0000 }, /* R17960 - ADCL_RETUNE_C21_1 */
408 { 17961, 0x0000 }, /* R17961 - ADCL_RETUNE_C21_0 */
409 { 17962, 0x0000 }, /* R17962 - ADCL_RETUNE_C22_1 */
410 { 17963, 0x0000 }, /* R17963 - ADCL_RETUNE_C22_0 */
411 { 17964, 0x0000 }, /* R17964 - ADCL_RETUNE_C23_1 */
412 { 17965, 0x0000 }, /* R17965 - ADCL_RETUNE_C23_0 */
413 { 17966, 0x0000 }, /* R17966 - ADCL_RETUNE_C24_1 */
414 { 17967, 0x0000 }, /* R17967 - ADCL_RETUNE_C24_0 */
415 { 17968, 0x0000 }, /* R17968 - ADCL_RETUNE_C25_1 */
416 { 17969, 0x0000 }, /* R17969 - ADCL_RETUNE_C25_0 */
417 { 17970, 0x0000 }, /* R17970 - ADCL_RETUNE_C26_1 */
418 { 17971, 0x0000 }, /* R17971 - ADCL_RETUNE_C26_0 */
419 { 17972, 0x0000 }, /* R17972 - ADCL_RETUNE_C27_1 */
420 { 17973, 0x0000 }, /* R17973 - ADCL_RETUNE_C27_0 */
421 { 17974, 0x0000 }, /* R17974 - ADCL_RETUNE_C28_1 */
422 { 17975, 0x0000 }, /* R17975 - ADCL_RETUNE_C28_0 */
423 { 17976, 0x0000 }, /* R17976 - ADCL_RETUNE_C29_1 */
424 { 17977, 0x0000 }, /* R17977 - ADCL_RETUNE_C29_0 */
425 { 17978, 0x0000 }, /* R17978 - ADCL_RETUNE_C30_1 */
426 { 17979, 0x0000 }, /* R17979 - ADCL_RETUNE_C30_0 */
427 { 17980, 0x0000 }, /* R17980 - ADCL_RETUNE_C31_1 */
428 { 17981, 0x0000 }, /* R17981 - ADCL_RETUNE_C31_0 */
429 { 17982, 0x0000 }, /* R17982 - ADCL_RETUNE_C32_1 */
430 { 17983, 0x0000 }, /* R17983 - ADCL_RETUNE_C32_0 */
432 { 18432, 0x0020 }, /* R18432 - RETUNEADC_PG2_1 */
433 { 18433, 0x0000 }, /* R18433 - RETUNEADC_PG2_0 */
434 { 18434, 0x0040 }, /* R18434 - RETUNEADC_PG_1 */
435 { 18435, 0x0000 }, /* R18435 - RETUNEADC_PG_0 */
437 { 18944, 0x007F }, /* R18944 - ADCR_RETUNE_C1_1 */
438 { 18945, 0xFFFF }, /* R18945 - ADCR_RETUNE_C1_0 */
439 { 18946, 0x0000 }, /* R18946 - ADCR_RETUNE_C2_1 */
440 { 18947, 0x0000 }, /* R18947 - ADCR_RETUNE_C2_0 */
441 { 18948, 0x0000 }, /* R18948 - ADCR_RETUNE_C3_1 */
442 { 18949, 0x0000 }, /* R18949 - ADCR_RETUNE_C3_0 */
443 { 18950, 0x0000 }, /* R18950 - ADCR_RETUNE_C4_1 */
444 { 18951, 0x0000 }, /* R18951 - ADCR_RETUNE_C4_0 */
445 { 18952, 0x0000 }, /* R18952 - ADCR_RETUNE_C5_1 */
446 { 18953, 0x0000 }, /* R18953 - ADCR_RETUNE_C5_0 */
447 { 18954, 0x0000 }, /* R18954 - ADCR_RETUNE_C6_1 */
448 { 18955, 0x0000 }, /* R18955 - ADCR_RETUNE_C6_0 */
449 { 18956, 0x0000 }, /* R18956 - ADCR_RETUNE_C7_1 */
450 { 18957, 0x0000 }, /* R18957 - ADCR_RETUNE_C7_0 */
451 { 18958, 0x0000 }, /* R18958 - ADCR_RETUNE_C8_1 */
452 { 18959, 0x0000 }, /* R18959 - ADCR_RETUNE_C8_0 */
453 { 18960, 0x0000 }, /* R18960 - ADCR_RETUNE_C9_1 */
454 { 18961, 0x0000 }, /* R18961 - ADCR_RETUNE_C9_0 */
455 { 18962, 0x0000 }, /* R18962 - ADCR_RETUNE_C10_1 */
456 { 18963, 0x0000 }, /* R18963 - ADCR_RETUNE_C10_0 */
457 { 18964, 0x0000 }, /* R18964 - ADCR_RETUNE_C11_1 */
458 { 18965, 0x0000 }, /* R18965 - ADCR_RETUNE_C11_0 */
459 { 18966, 0x0000 }, /* R18966 - ADCR_RETUNE_C12_1 */
460 { 18967, 0x0000 }, /* R18967 - ADCR_RETUNE_C12_0 */
461 { 18968, 0x0000 }, /* R18968 - ADCR_RETUNE_C13_1 */
462 { 18969, 0x0000 }, /* R18969 - ADCR_RETUNE_C13_0 */
463 { 18970, 0x0000 }, /* R18970 - ADCR_RETUNE_C14_1 */
464 { 18971, 0x0000 }, /* R18971 - ADCR_RETUNE_C14_0 */
465 { 18972, 0x0000 }, /* R18972 - ADCR_RETUNE_C15_1 */
466 { 18973, 0x0000 }, /* R18973 - ADCR_RETUNE_C15_0 */
467 { 18974, 0x0000 }, /* R18974 - ADCR_RETUNE_C16_1 */
468 { 18975, 0x0000 }, /* R18975 - ADCR_RETUNE_C16_0 */
469 { 18976, 0x0000 }, /* R18976 - ADCR_RETUNE_C17_1 */
470 { 18977, 0x0000 }, /* R18977 - ADCR_RETUNE_C17_0 */
471 { 18978, 0x0000 }, /* R18978 - ADCR_RETUNE_C18_1 */
472 { 18979, 0x0000 }, /* R18979 - ADCR_RETUNE_C18_0 */
473 { 18980, 0x0000 }, /* R18980 - ADCR_RETUNE_C19_1 */
474 { 18981, 0x0000 }, /* R18981 - ADCR_RETUNE_C19_0 */
475 { 18982, 0x0000 }, /* R18982 - ADCR_RETUNE_C20_1 */
476 { 18983, 0x0000 }, /* R18983 - ADCR_RETUNE_C20_0 */
477 { 18984, 0x0000 }, /* R18984 - ADCR_RETUNE_C21_1 */
478 { 18985, 0x0000 }, /* R18985 - ADCR_RETUNE_C21_0 */
479 { 18986, 0x0000 }, /* R18986 - ADCR_RETUNE_C22_1 */
480 { 18987, 0x0000 }, /* R18987 - ADCR_RETUNE_C22_0 */
481 { 18988, 0x0000 }, /* R18988 - ADCR_RETUNE_C23_1 */
482 { 18989, 0x0000 }, /* R18989 - ADCR_RETUNE_C23_0 */
483 { 18990, 0x0000 }, /* R18990 - ADCR_RETUNE_C24_1 */
484 { 18991, 0x0000 }, /* R18991 - ADCR_RETUNE_C24_0 */
485 { 18992, 0x0000 }, /* R18992 - ADCR_RETUNE_C25_1 */
486 { 18993, 0x0000 }, /* R18993 - ADCR_RETUNE_C25_0 */
487 { 18994, 0x0000 }, /* R18994 - ADCR_RETUNE_C26_1 */
488 { 18995, 0x0000 }, /* R18995 - ADCR_RETUNE_C26_0 */
489 { 18996, 0x0000 }, /* R18996 - ADCR_RETUNE_C27_1 */
490 { 18997, 0x0000 }, /* R18997 - ADCR_RETUNE_C27_0 */
491 { 18998, 0x0000 }, /* R18998 - ADCR_RETUNE_C28_1 */
492 { 18999, 0x0000 }, /* R18999 - ADCR_RETUNE_C28_0 */
493 { 19000, 0x0000 }, /* R19000 - ADCR_RETUNE_C29_1 */
494 { 19001, 0x0000 }, /* R19001 - ADCR_RETUNE_C29_0 */
495 { 19002, 0x0000 }, /* R19002 - ADCR_RETUNE_C30_1 */
496 { 19003, 0x0000 }, /* R19003 - ADCR_RETUNE_C30_0 */
497 { 19004, 0x0000 }, /* R19004 - ADCR_RETUNE_C31_1 */
498 { 19005, 0x0000 }, /* R19005 - ADCR_RETUNE_C31_0 */
499 { 19006, 0x0000 }, /* R19006 - ADCR_RETUNE_C32_1 */
500 { 19007, 0x0000 }, /* R19007 - ADCR_RETUNE_C32_0 */
502 { 19456, 0x007F }, /* R19456 - DACL_RETUNE_C1_1 */
503 { 19457, 0xFFFF }, /* R19457 - DACL_RETUNE_C1_0 */
504 { 19458, 0x0000 }, /* R19458 - DACL_RETUNE_C2_1 */
505 { 19459, 0x0000 }, /* R19459 - DACL_RETUNE_C2_0 */
506 { 19460, 0x0000 }, /* R19460 - DACL_RETUNE_C3_1 */
507 { 19461, 0x0000 }, /* R19461 - DACL_RETUNE_C3_0 */
508 { 19462, 0x0000 }, /* R19462 - DACL_RETUNE_C4_1 */
509 { 19463, 0x0000 }, /* R19463 - DACL_RETUNE_C4_0 */
510 { 19464, 0x0000 }, /* R19464 - DACL_RETUNE_C5_1 */
511 { 19465, 0x0000 }, /* R19465 - DACL_RETUNE_C5_0 */
512 { 19466, 0x0000 }, /* R19466 - DACL_RETUNE_C6_1 */
513 { 19467, 0x0000 }, /* R19467 - DACL_RETUNE_C6_0 */
514 { 19468, 0x0000 }, /* R19468 - DACL_RETUNE_C7_1 */
515 { 19469, 0x0000 }, /* R19469 - DACL_RETUNE_C7_0 */
516 { 19470, 0x0000 }, /* R19470 - DACL_RETUNE_C8_1 */
517 { 19471, 0x0000 }, /* R19471 - DACL_RETUNE_C8_0 */
518 { 19472, 0x0000 }, /* R19472 - DACL_RETUNE_C9_1 */
519 { 19473, 0x0000 }, /* R19473 - DACL_RETUNE_C9_0 */
520 { 19474, 0x0000 }, /* R19474 - DACL_RETUNE_C10_1 */
521 { 19475, 0x0000 }, /* R19475 - DACL_RETUNE_C10_0 */
522 { 19476, 0x0000 }, /* R19476 - DACL_RETUNE_C11_1 */
523 { 19477, 0x0000 }, /* R19477 - DACL_RETUNE_C11_0 */
524 { 19478, 0x0000 }, /* R19478 - DACL_RETUNE_C12_1 */
525 { 19479, 0x0000 }, /* R19479 - DACL_RETUNE_C12_0 */
526 { 19480, 0x0000 }, /* R19480 - DACL_RETUNE_C13_1 */
527 { 19481, 0x0000 }, /* R19481 - DACL_RETUNE_C13_0 */
528 { 19482, 0x0000 }, /* R19482 - DACL_RETUNE_C14_1 */
529 { 19483, 0x0000 }, /* R19483 - DACL_RETUNE_C14_0 */
530 { 19484, 0x0000 }, /* R19484 - DACL_RETUNE_C15_1 */
531 { 19485, 0x0000 }, /* R19485 - DACL_RETUNE_C15_0 */
532 { 19486, 0x0000 }, /* R19486 - DACL_RETUNE_C16_1 */
533 { 19487, 0x0000 }, /* R19487 - DACL_RETUNE_C16_0 */
534 { 19488, 0x0000 }, /* R19488 - DACL_RETUNE_C17_1 */
535 { 19489, 0x0000 }, /* R19489 - DACL_RETUNE_C17_0 */
536 { 19490, 0x0000 }, /* R19490 - DACL_RETUNE_C18_1 */
537 { 19491, 0x0000 }, /* R19491 - DACL_RETUNE_C18_0 */
538 { 19492, 0x0000 }, /* R19492 - DACL_RETUNE_C19_1 */
539 { 19493, 0x0000 }, /* R19493 - DACL_RETUNE_C19_0 */
540 { 19494, 0x0000 }, /* R19494 - DACL_RETUNE_C20_1 */
541 { 19495, 0x0000 }, /* R19495 - DACL_RETUNE_C20_0 */
542 { 19496, 0x0000 }, /* R19496 - DACL_RETUNE_C21_1 */
543 { 19497, 0x0000 }, /* R19497 - DACL_RETUNE_C21_0 */
544 { 19498, 0x0000 }, /* R19498 - DACL_RETUNE_C22_1 */
545 { 19499, 0x0000 }, /* R19499 - DACL_RETUNE_C22_0 */
546 { 19500, 0x0000 }, /* R19500 - DACL_RETUNE_C23_1 */
547 { 19501, 0x0000 }, /* R19501 - DACL_RETUNE_C23_0 */
548 { 19502, 0x0000 }, /* R19502 - DACL_RETUNE_C24_1 */
549 { 19503, 0x0000 }, /* R19503 - DACL_RETUNE_C24_0 */
550 { 19504, 0x0000 }, /* R19504 - DACL_RETUNE_C25_1 */
551 { 19505, 0x0000 }, /* R19505 - DACL_RETUNE_C25_0 */
552 { 19506, 0x0000 }, /* R19506 - DACL_RETUNE_C26_1 */
553 { 19507, 0x0000 }, /* R19507 - DACL_RETUNE_C26_0 */
554 { 19508, 0x0000 }, /* R19508 - DACL_RETUNE_C27_1 */
555 { 19509, 0x0000 }, /* R19509 - DACL_RETUNE_C27_0 */
556 { 19510, 0x0000 }, /* R19510 - DACL_RETUNE_C28_1 */
557 { 19511, 0x0000 }, /* R19511 - DACL_RETUNE_C28_0 */
558 { 19512, 0x0000 }, /* R19512 - DACL_RETUNE_C29_1 */
559 { 19513, 0x0000 }, /* R19513 - DACL_RETUNE_C29_0 */
560 { 19514, 0x0000 }, /* R19514 - DACL_RETUNE_C30_1 */
561 { 19515, 0x0000 }, /* R19515 - DACL_RETUNE_C30_0 */
562 { 19516, 0x0000 }, /* R19516 - DACL_RETUNE_C31_1 */
563 { 19517, 0x0000 }, /* R19517 - DACL_RETUNE_C31_0 */
564 { 19518, 0x0000 }, /* R19518 - DACL_RETUNE_C32_1 */
565 { 19519, 0x0000 }, /* R19519 - DACL_RETUNE_C32_0 */
567 { 19968, 0x0020 }, /* R19968 - RETUNEDAC_PG2_1 */
568 { 19969, 0x0000 }, /* R19969 - RETUNEDAC_PG2_0 */
569 { 19970, 0x0040 }, /* R19970 - RETUNEDAC_PG_1 */
570 { 19971, 0x0000 }, /* R19971 - RETUNEDAC_PG_0 */
572 { 20480, 0x007F }, /* R20480 - DACR_RETUNE_C1_1 */
573 { 20481, 0xFFFF }, /* R20481 - DACR_RETUNE_C1_0 */
574 { 20482, 0x0000 }, /* R20482 - DACR_RETUNE_C2_1 */
575 { 20483, 0x0000 }, /* R20483 - DACR_RETUNE_C2_0 */
576 { 20484, 0x0000 }, /* R20484 - DACR_RETUNE_C3_1 */
577 { 20485, 0x0000 }, /* R20485 - DACR_RETUNE_C3_0 */
578 { 20486, 0x0000 }, /* R20486 - DACR_RETUNE_C4_1 */
579 { 20487, 0x0000 }, /* R20487 - DACR_RETUNE_C4_0 */
580 { 20488, 0x0000 }, /* R20488 - DACR_RETUNE_C5_1 */
581 { 20489, 0x0000 }, /* R20489 - DACR_RETUNE_C5_0 */
582 { 20490, 0x0000 }, /* R20490 - DACR_RETUNE_C6_1 */
583 { 20491, 0x0000 }, /* R20491 - DACR_RETUNE_C6_0 */
584 { 20492, 0x0000 }, /* R20492 - DACR_RETUNE_C7_1 */
585 { 20493, 0x0000 }, /* R20493 - DACR_RETUNE_C7_0 */
586 { 20494, 0x0000 }, /* R20494 - DACR_RETUNE_C8_1 */
587 { 20495, 0x0000 }, /* R20495 - DACR_RETUNE_C8_0 */
588 { 20496, 0x0000 }, /* R20496 - DACR_RETUNE_C9_1 */
589 { 20497, 0x0000 }, /* R20497 - DACR_RETUNE_C9_0 */
590 { 20498, 0x0000 }, /* R20498 - DACR_RETUNE_C10_1 */
591 { 20499, 0x0000 }, /* R20499 - DACR_RETUNE_C10_0 */
592 { 20500, 0x0000 }, /* R20500 - DACR_RETUNE_C11_1 */
593 { 20501, 0x0000 }, /* R20501 - DACR_RETUNE_C11_0 */
594 { 20502, 0x0000 }, /* R20502 - DACR_RETUNE_C12_1 */
595 { 20503, 0x0000 }, /* R20503 - DACR_RETUNE_C12_0 */
596 { 20504, 0x0000 }, /* R20504 - DACR_RETUNE_C13_1 */
597 { 20505, 0x0000 }, /* R20505 - DACR_RETUNE_C13_0 */
598 { 20506, 0x0000 }, /* R20506 - DACR_RETUNE_C14_1 */
599 { 20507, 0x0000 }, /* R20507 - DACR_RETUNE_C14_0 */
600 { 20508, 0x0000 }, /* R20508 - DACR_RETUNE_C15_1 */
601 { 20509, 0x0000 }, /* R20509 - DACR_RETUNE_C15_0 */
602 { 20510, 0x0000 }, /* R20510 - DACR_RETUNE_C16_1 */
603 { 20511, 0x0000 }, /* R20511 - DACR_RETUNE_C16_0 */
604 { 20512, 0x0000 }, /* R20512 - DACR_RETUNE_C17_1 */
605 { 20513, 0x0000 }, /* R20513 - DACR_RETUNE_C17_0 */
606 { 20514, 0x0000 }, /* R20514 - DACR_RETUNE_C18_1 */
607 { 20515, 0x0000 }, /* R20515 - DACR_RETUNE_C18_0 */
608 { 20516, 0x0000 }, /* R20516 - DACR_RETUNE_C19_1 */
609 { 20517, 0x0000 }, /* R20517 - DACR_RETUNE_C19_0 */
610 { 20518, 0x0000 }, /* R20518 - DACR_RETUNE_C20_1 */
611 { 20519, 0x0000 }, /* R20519 - DACR_RETUNE_C20_0 */
612 { 20520, 0x0000 }, /* R20520 - DACR_RETUNE_C21_1 */
613 { 20521, 0x0000 }, /* R20521 - DACR_RETUNE_C21_0 */
614 { 20522, 0x0000 }, /* R20522 - DACR_RETUNE_C22_1 */
615 { 20523, 0x0000 }, /* R20523 - DACR_RETUNE_C22_0 */
616 { 20524, 0x0000 }, /* R20524 - DACR_RETUNE_C23_1 */
617 { 20525, 0x0000 }, /* R20525 - DACR_RETUNE_C23_0 */
618 { 20526, 0x0000 }, /* R20526 - DACR_RETUNE_C24_1 */
619 { 20527, 0x0000 }, /* R20527 - DACR_RETUNE_C24_0 */
620 { 20528, 0x0000 }, /* R20528 - DACR_RETUNE_C25_1 */
621 { 20529, 0x0000 }, /* R20529 - DACR_RETUNE_C25_0 */
622 { 20530, 0x0000 }, /* R20530 - DACR_RETUNE_C26_1 */
623 { 20531, 0x0000 }, /* R20531 - DACR_RETUNE_C26_0 */
624 { 20532, 0x0000 }, /* R20532 - DACR_RETUNE_C27_1 */
625 { 20533, 0x0000 }, /* R20533 - DACR_RETUNE_C27_0 */
626 { 20534, 0x0000 }, /* R20534 - DACR_RETUNE_C28_1 */
627 { 20535, 0x0000 }, /* R20535 - DACR_RETUNE_C28_0 */
628 { 20536, 0x0000 }, /* R20536 - DACR_RETUNE_C29_1 */
629 { 20537, 0x0000 }, /* R20537 - DACR_RETUNE_C29_0 */
630 { 20538, 0x0000 }, /* R20538 - DACR_RETUNE_C30_1 */
631 { 20539, 0x0000 }, /* R20539 - DACR_RETUNE_C30_0 */
632 { 20540, 0x0000 }, /* R20540 - DACR_RETUNE_C31_1 */
633 { 20541, 0x0000 }, /* R20541 - DACR_RETUNE_C31_0 */
634 { 20542, 0x0000 }, /* R20542 - DACR_RETUNE_C32_1 */
635 { 20543, 0x0000 }, /* R20543 - DACR_RETUNE_C32_0 */
637 { 20992, 0x008C }, /* R20992 - VSS_XHD2_1 */
638 { 20993, 0x0200 }, /* R20993 - VSS_XHD2_0 */
639 { 20994, 0x0035 }, /* R20994 - VSS_XHD3_1 */
640 { 20995, 0x0700 }, /* R20995 - VSS_XHD3_0 */
641 { 20996, 0x003A }, /* R20996 - VSS_XHN1_1 */
642 { 20997, 0x4100 }, /* R20997 - VSS_XHN1_0 */
643 { 20998, 0x008B }, /* R20998 - VSS_XHN2_1 */
644 { 20999, 0x7D00 }, /* R20999 - VSS_XHN2_0 */
645 { 21000, 0x003A }, /* R21000 - VSS_XHN3_1 */
646 { 21001, 0x4100 }, /* R21001 - VSS_XHN3_0 */
647 { 21002, 0x008C }, /* R21002 - VSS_XLA_1 */
648 { 21003, 0xFEE8 }, /* R21003 - VSS_XLA_0 */
649 { 21004, 0x0078 }, /* R21004 - VSS_XLB_1 */
650 { 21005, 0x0000 }, /* R21005 - VSS_XLB_0 */
651 { 21006, 0x003F }, /* R21006 - VSS_XLG_1 */
652 { 21007, 0xB260 }, /* R21007 - VSS_XLG_0 */
653 { 21008, 0x002D }, /* R21008 - VSS_PG2_1 */
654 { 21009, 0x1818 }, /* R21009 - VSS_PG2_0 */
655 { 21010, 0x0020 }, /* R21010 - VSS_PG_1 */
656 { 21011, 0x0000 }, /* R21011 - VSS_PG_0 */
657 { 21012, 0x00F1 }, /* R21012 - VSS_XTD1_1 */
658 { 21013, 0x8340 }, /* R21013 - VSS_XTD1_0 */
659 { 21014, 0x00FB }, /* R21014 - VSS_XTD2_1 */
660 { 21015, 0x8300 }, /* R21015 - VSS_XTD2_0 */
661 { 21016, 0x00EE }, /* R21016 - VSS_XTD3_1 */
662 { 21017, 0xAEC0 }, /* R21017 - VSS_XTD3_0 */
663 { 21018, 0x00FB }, /* R21018 - VSS_XTD4_1 */
664 { 21019, 0xAC40 }, /* R21019 - VSS_XTD4_0 */
665 { 21020, 0x00F1 }, /* R21020 - VSS_XTD5_1 */
666 { 21021, 0x7F80 }, /* R21021 - VSS_XTD5_0 */
667 { 21022, 0x00F4 }, /* R21022 - VSS_XTD6_1 */
668 { 21023, 0x3B40 }, /* R21023 - VSS_XTD6_0 */
669 { 21024, 0x00F5 }, /* R21024 - VSS_XTD7_1 */
670 { 21025, 0xFB00 }, /* R21025 - VSS_XTD7_0 */
671 { 21026, 0x00EA }, /* R21026 - VSS_XTD8_1 */
672 { 21027, 0x10C0 }, /* R21027 - VSS_XTD8_0 */
673 { 21028, 0x00FC }, /* R21028 - VSS_XTD9_1 */
674 { 21029, 0xC580 }, /* R21029 - VSS_XTD9_0 */
675 { 21030, 0x00E2 }, /* R21030 - VSS_XTD10_1 */
676 { 21031, 0x75C0 }, /* R21031 - VSS_XTD10_0 */
677 { 21032, 0x0004 }, /* R21032 - VSS_XTD11_1 */
678 { 21033, 0xB480 }, /* R21033 - VSS_XTD11_0 */
679 { 21034, 0x00D4 }, /* R21034 - VSS_XTD12_1 */
680 { 21035, 0xF980 }, /* R21035 - VSS_XTD12_0 */
681 { 21036, 0x0004 }, /* R21036 - VSS_XTD13_1 */
682 { 21037, 0x9140 }, /* R21037 - VSS_XTD13_0 */
683 { 21038, 0x00D8 }, /* R21038 - VSS_XTD14_1 */
684 { 21039, 0xA480 }, /* R21039 - VSS_XTD14_0 */
685 { 21040, 0x0002 }, /* R21040 - VSS_XTD15_1 */
686 { 21041, 0x3DC0 }, /* R21041 - VSS_XTD15_0 */
687 { 21042, 0x00CF }, /* R21042 - VSS_XTD16_1 */
688 { 21043, 0x7A80 }, /* R21043 - VSS_XTD16_0 */
689 { 21044, 0x00DC }, /* R21044 - VSS_XTD17_1 */
690 { 21045, 0x0600 }, /* R21045 - VSS_XTD17_0 */
691 { 21046, 0x00F2 }, /* R21046 - VSS_XTD18_1 */
692 { 21047, 0xDAC0 }, /* R21047 - VSS_XTD18_0 */
693 { 21048, 0x00BA }, /* R21048 - VSS_XTD19_1 */
694 { 21049, 0xF340 }, /* R21049 - VSS_XTD19_0 */
695 { 21050, 0x000A }, /* R21050 - VSS_XTD20_1 */
696 { 21051, 0x7940 }, /* R21051 - VSS_XTD20_0 */
697 { 21052, 0x001C }, /* R21052 - VSS_XTD21_1 */
698 { 21053, 0x0680 }, /* R21053 - VSS_XTD21_0 */
699 { 21054, 0x00FD }, /* R21054 - VSS_XTD22_1 */
700 { 21055, 0x2D00 }, /* R21055 - VSS_XTD22_0 */
701 { 21056, 0x001C }, /* R21056 - VSS_XTD23_1 */
702 { 21057, 0xE840 }, /* R21057 - VSS_XTD23_0 */
703 { 21058, 0x000D }, /* R21058 - VSS_XTD24_1 */
704 { 21059, 0xDC40 }, /* R21059 - VSS_XTD24_0 */
705 { 21060, 0x00FC }, /* R21060 - VSS_XTD25_1 */
706 { 21061, 0x9D00 }, /* R21061 - VSS_XTD25_0 */
707 { 21062, 0x0009 }, /* R21062 - VSS_XTD26_1 */
708 { 21063, 0x5580 }, /* R21063 - VSS_XTD26_0 */
709 { 21064, 0x00FE }, /* R21064 - VSS_XTD27_1 */
710 { 21065, 0x7E80 }, /* R21065 - VSS_XTD27_0 */
711 { 21066, 0x000E }, /* R21066 - VSS_XTD28_1 */
712 { 21067, 0xAB40 }, /* R21067 - VSS_XTD28_0 */
713 { 21068, 0x00F9 }, /* R21068 - VSS_XTD29_1 */
714 { 21069, 0x9880 }, /* R21069 - VSS_XTD29_0 */
715 { 21070, 0x0009 }, /* R21070 - VSS_XTD30_1 */
716 { 21071, 0x87C0 }, /* R21071 - VSS_XTD30_0 */
717 { 21072, 0x00FD }, /* R21072 - VSS_XTD31_1 */
718 { 21073, 0x2C40 }, /* R21073 - VSS_XTD31_0 */
719 { 21074, 0x0009 }, /* R21074 - VSS_XTD32_1 */
720 { 21075, 0x4800 }, /* R21075 - VSS_XTD32_0 */
721 { 21076, 0x0003 }, /* R21076 - VSS_XTS1_1 */
722 { 21077, 0x5F40 }, /* R21077 - VSS_XTS1_0 */
723 { 21078, 0x0000 }, /* R21078 - VSS_XTS2_1 */
724 { 21079, 0x8700 }, /* R21079 - VSS_XTS2_0 */
725 { 21080, 0x00FA }, /* R21080 - VSS_XTS3_1 */
726 { 21081, 0xE4C0 }, /* R21081 - VSS_XTS3_0 */
727 { 21082, 0x0000 }, /* R21082 - VSS_XTS4_1 */
728 { 21083, 0x0B40 }, /* R21083 - VSS_XTS4_0 */
729 { 21084, 0x0004 }, /* R21084 - VSS_XTS5_1 */
730 { 21085, 0xE180 }, /* R21085 - VSS_XTS5_0 */
731 { 21086, 0x0001 }, /* R21086 - VSS_XTS6_1 */
732 { 21087, 0x1F40 }, /* R21087 - VSS_XTS6_0 */
733 { 21088, 0x00F8 }, /* R21088 - VSS_XTS7_1 */
734 { 21089, 0xB000 }, /* R21089 - VSS_XTS7_0 */
735 { 21090, 0x00FB }, /* R21090 - VSS_XTS8_1 */
736 { 21091, 0xCBC0 }, /* R21091 - VSS_XTS8_0 */
737 { 21092, 0x0004 }, /* R21092 - VSS_XTS9_1 */
738 { 21093, 0xF380 }, /* R21093 - VSS_XTS9_0 */
739 { 21094, 0x0007 }, /* R21094 - VSS_XTS10_1 */
740 { 21095, 0xDF40 }, /* R21095 - VSS_XTS10_0 */
741 { 21096, 0x00FF }, /* R21096 - VSS_XTS11_1 */
742 { 21097, 0x0700 }, /* R21097 - VSS_XTS11_0 */
743 { 21098, 0x00EF }, /* R21098 - VSS_XTS12_1 */
744 { 21099, 0xD700 }, /* R21099 - VSS_XTS12_0 */
745 { 21100, 0x00FB }, /* R21100 - VSS_XTS13_1 */
746 { 21101, 0xAF40 }, /* R21101 - VSS_XTS13_0 */
747 { 21102, 0x0010 }, /* R21102 - VSS_XTS14_1 */
748 { 21103, 0x8A80 }, /* R21103 - VSS_XTS14_0 */
749 { 21104, 0x0011 }, /* R21104 - VSS_XTS15_1 */
750 { 21105, 0x07C0 }, /* R21105 - VSS_XTS15_0 */
751 { 21106, 0x00E0 }, /* R21106 - VSS_XTS16_1 */
752 { 21107, 0x0800 }, /* R21107 - VSS_XTS16_0 */
753 { 21108, 0x00D2 }, /* R21108 - VSS_XTS17_1 */
754 { 21109, 0x7600 }, /* R21109 - VSS_XTS17_0 */
755 { 21110, 0x0020 }, /* R21110 - VSS_XTS18_1 */
756 { 21111, 0xCF40 }, /* R21111 - VSS_XTS18_0 */
757 { 21112, 0x0030 }, /* R21112 - VSS_XTS19_1 */
758 { 21113, 0x2340 }, /* R21113 - VSS_XTS19_0 */
759 { 21114, 0x00FD }, /* R21114 - VSS_XTS20_1 */
760 { 21115, 0x69C0 }, /* R21115 - VSS_XTS20_0 */
761 { 21116, 0x0028 }, /* R21116 - VSS_XTS21_1 */
762 { 21117, 0x3500 }, /* R21117 - VSS_XTS21_0 */
763 { 21118, 0x0006 }, /* R21118 - VSS_XTS22_1 */
764 { 21119, 0x3300 }, /* R21119 - VSS_XTS22_0 */
765 { 21120, 0x00D9 }, /* R21120 - VSS_XTS23_1 */
766 { 21121, 0xF6C0 }, /* R21121 - VSS_XTS23_0 */
767 { 21122, 0x00F3 }, /* R21122 - VSS_XTS24_1 */
768 { 21123, 0x3340 }, /* R21123 - VSS_XTS24_0 */
769 { 21124, 0x000F }, /* R21124 - VSS_XTS25_1 */
770 { 21125, 0x4200 }, /* R21125 - VSS_XTS25_0 */
771 { 21126, 0x0004 }, /* R21126 - VSS_XTS26_1 */
772 { 21127, 0x0C80 }, /* R21127 - VSS_XTS26_0 */
773 { 21128, 0x00FB }, /* R21128 - VSS_XTS27_1 */
774 { 21129, 0x3F80 }, /* R21129 - VSS_XTS27_0 */
775 { 21130, 0x00F7 }, /* R21130 - VSS_XTS28_1 */
776 { 21131, 0x57C0 }, /* R21131 - VSS_XTS28_0 */
777 { 21132, 0x0003 }, /* R21132 - VSS_XTS29_1 */
778 { 21133, 0x5400 }, /* R21133 - VSS_XTS29_0 */
779 { 21134, 0x0000 }, /* R21134 - VSS_XTS30_1 */
780 { 21135, 0xC6C0 }, /* R21135 - VSS_XTS30_0 */
781 { 21136, 0x0003 }, /* R21136 - VSS_XTS31_1 */
782 { 21137, 0x12C0 }, /* R21137 - VSS_XTS31_0 */
783 { 21138, 0x00FD }, /* R21138 - VSS_XTS32_1 */
784 { 21139, 0x8580 }, /* R21139 - VSS_XTS32_0 */
1443 ret = regmap_write(wm8962->regmap, WM8962_SOFTWARE_RESET, 0x6243); in wm8962_reset()
1447 return regmap_write(wm8962->regmap, WM8962_PLL_SOFTWARE_RESET, 0); in wm8962_reset()
1450 static const DECLARE_TLV_DB_SCALE(inpga_tlv, -2325, 75, 0);
1451 static const DECLARE_TLV_DB_SCALE(mixin_tlv, -1500, 300, 0);
1459 static const DECLARE_TLV_DB_SCALE(beep_tlv, -9600, 600, 1);
1460 static const DECLARE_TLV_DB_SCALE(digital_tlv, -7200, 75, 1);
1461 static const DECLARE_TLV_DB_SCALE(st_tlv, -3600, 300, 0);
1462 static const DECLARE_TLV_DB_SCALE(inmix_tlv, -600, 600, 0);
1463 static const DECLARE_TLV_DB_SCALE(bypass_tlv, -1500, 300, 0);
1464 static const DECLARE_TLV_DB_SCALE(out_tlv, -12100, 100, 1);
1465 static const DECLARE_TLV_DB_SCALE(hp_tlv, -700, 100, 0);
1470 static const DECLARE_TLV_DB_SCALE(eq_tlv, -1200, 100, 0);
1476 return regcache_sync_region(wm8962->regmap, in wm8962_dsp2_write_config()
1511 wm8962_dsp2_set_enable(component, wm8962->dsp2_ena); in wm8962_dsp2_start()
1534 uinfo->type = SNDRV_CTL_ELEM_TYPE_BOOLEAN; in wm8962_dsp2_ena_info()
1536 uinfo->count = 1; in wm8962_dsp2_ena_info()
1537 uinfo->value.integer.min = 0; in wm8962_dsp2_ena_info()
1538 uinfo->value.integer.max = 1; in wm8962_dsp2_ena_info()
1546 int shift = kcontrol->private_value; in wm8962_dsp2_ena_get()
1550 ucontrol->value.integer.value[0] = !!(wm8962->dsp2_ena & 1 << shift); in wm8962_dsp2_ena_get()
1558 int shift = kcontrol->private_value; in wm8962_dsp2_ena_put()
1561 int old = wm8962->dsp2_ena; in wm8962_dsp2_ena_put()
1566 mutex_lock(&wm8962->dsp2_ena_lock); in wm8962_dsp2_ena_put()
1568 if (ucontrol->value.integer.value[0]) in wm8962_dsp2_ena_put()
1569 wm8962->dsp2_ena |= 1 << shift; in wm8962_dsp2_ena_put()
1571 wm8962->dsp2_ena &= ~(1 << shift); in wm8962_dsp2_ena_put()
1573 if (wm8962->dsp2_ena == old) in wm8962_dsp2_ena_put()
1579 if (wm8962->dsp2_ena) in wm8962_dsp2_ena_put()
1580 wm8962_dsp2_set_enable(component, wm8962->dsp2_ena); in wm8962_dsp2_ena_put()
1586 mutex_unlock(&wm8962->dsp2_ena_lock); in wm8962_dsp2_ena_put()
1652 "Hi-fi", "Application"
1847 struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm); in tp_event()
1849 ret = pm_runtime_resume_and_get(component->dev); in tp_event()
1851 dev_err(component->dev, "Failed to resume device: %d\n", ret); in tp_event()
1864 pm_runtime_put(component->dev); in tp_event()
1865 return -EINVAL; in tp_event()
1877 pm_runtime_put(component->dev); in tp_event()
1878 return -EINVAL; in tp_event()
1881 pm_runtime_put(component->dev); in tp_event()
1896 return -EINVAL; in cp_event()
1905 struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm); in hp_event()
1937 dev_err(component->dev, in hp_event()
1942 dev_dbg(component->dev, "DCS status: %x\n", reg); in hp_event()
1946 dev_err(component->dev, "DC servo timed out\n"); in hp_event()
1948 dev_dbg(component->dev, "DC servo complete after %dms\n", in hp_event()
1988 return -EINVAL; in hp_event()
1999 struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm); in out_pga_event()
2002 switch (w->shift) { in out_pga_event()
2016 WARN(1, "Invalid shift %d\n", w->shift); in out_pga_event()
2017 return -EINVAL; in out_pga_event()
2026 return -EINVAL; in out_pga_event()
2033 struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm); in dsp2_event()
2038 if (wm8962->dsp2_ena) in dsp2_event()
2043 if (wm8962->dsp2_ena) in dsp2_event()
2049 return -EINVAL; in dsp2_event()
2420 struct wm8962_pdata *pdata = &wm8962->pdata; in wm8962_add_widgets()
2425 if (pdata->spk_mono) in wm8962_add_widgets()
2435 if (pdata->spk_mono) in wm8962_add_widgets()
2444 if (pdata->spk_mono) in wm8962_add_widgets()
2457 /* -1 for reserved values */
2459 1, -1, 2, 3, 4, -1, 6, 8, -1, 12, 16, 24, -1, 32, 32, 32
2473 int aif2 = 0; in wm8962_configure_bclk() local
2475 if (!wm8962->sysclk_rate) { in wm8962_configure_bclk()
2476 dev_dbg(component->dev, "No SYSCLK configured\n"); in wm8962_configure_bclk()
2480 if (!wm8962->bclk || !wm8962->lrclk) { in wm8962_configure_bclk()
2481 dev_dbg(component->dev, "No audio clocks configured\n"); in wm8962_configure_bclk()
2486 if (sysclk_rates[i] == wm8962->sysclk_rate / wm8962->lrclk) { in wm8962_configure_bclk()
2493 dev_err(component->dev, "Unsupported sysclk ratio %d\n", in wm8962_configure_bclk()
2494 wm8962->sysclk_rate / wm8962->lrclk); in wm8962_configure_bclk()
2498 dev_dbg(component->dev, "Selected sysclk ratio %d\n", sysclk_rates[i]); in wm8962_configure_bclk()
2512 * correct frequency of LRCLK and BCLK. Sometimes the read-only value in wm8962_configure_bclk()
2526 dev_err(component->dev, "Failed to read DSPCLK: %d\n", dspclk); in wm8962_configure_bclk()
2533 dspclk = wm8962->sysclk_rate; in wm8962_configure_bclk()
2536 dspclk = wm8962->sysclk_rate / 2; in wm8962_configure_bclk()
2539 dspclk = wm8962->sysclk_rate / 4; in wm8962_configure_bclk()
2542 dev_warn(component->dev, "Unknown DSPCLK divisor read back\n"); in wm8962_configure_bclk()
2543 dspclk = wm8962->sysclk_rate; in wm8962_configure_bclk()
2546 dev_dbg(component->dev, "DSPCLK is %dHz, BCLK %d\n", dspclk, wm8962->bclk); in wm8962_configure_bclk()
2555 diff = (dspclk / bclk_divs[i]) - wm8962->bclk; in wm8962_configure_bclk()
2563 wm8962->bclk = dspclk / bclk_divs[best]; in wm8962_configure_bclk()
2565 dev_dbg(component->dev, "Selected BCLK_DIV %d for %dHz\n", in wm8962_configure_bclk()
2566 bclk_divs[best], wm8962->bclk); in wm8962_configure_bclk()
2568 aif2 |= wm8962->bclk / wm8962->lrclk; in wm8962_configure_bclk()
2569 dev_dbg(component->dev, "Selected LRCLK divisor %d for %dHz\n", in wm8962_configure_bclk()
2570 wm8962->bclk / wm8962->lrclk, wm8962->lrclk); in wm8962_configure_bclk()
2575 WM8962_AIF_RATE_MASK, aif2); in wm8962_configure_bclk()
2630 struct snd_soc_component *component = dai->component; in wm8962_hw_params()
2636 wm8962->bclk = snd_soc_params_to_bclk(params); in wm8962_hw_params()
2638 wm8962->bclk *= 2; in wm8962_hw_params()
2640 wm8962->lrclk = params_rate(params); in wm8962_hw_params()
2643 if (sr_vals[i].rate == wm8962->lrclk) { in wm8962_hw_params()
2649 dev_err(component->dev, "Unsupported rate %dHz\n", wm8962->lrclk); in wm8962_hw_params()
2650 return -EINVAL; in wm8962_hw_params()
2653 if (wm8962->lrclk % 8000 == 0) in wm8962_hw_params()
2669 return -EINVAL; in wm8962_hw_params()
2678 dev_dbg(component->dev, "hw_params set BCLK %dHz LRCLK %dHz\n", in wm8962_hw_params()
2679 wm8962->bclk, wm8962->lrclk); in wm8962_hw_params()
2690 struct snd_soc_component *component = dai->component; in wm8962_set_dai_sysclk()
2696 wm8962->sysclk = WM8962_SYSCLK_MCLK; in wm8962_set_dai_sysclk()
2700 wm8962->sysclk = WM8962_SYSCLK_FLL; in wm8962_set_dai_sysclk()
2704 return -EINVAL; in wm8962_set_dai_sysclk()
2710 wm8962->sysclk_rate = freq; in wm8962_set_dai_sysclk()
2717 struct snd_soc_component *component = dai->component; in wm8962_set_dai_fmt()
2732 return -EINVAL; in wm8962_set_dai_fmt()
2745 return -EINVAL; in wm8962_set_dai_fmt()
2761 return -EINVAL; in wm8962_set_dai_fmt()
2771 return -EINVAL; in wm8962_set_dai_fmt()
2817 fll_div->fll_refclk_div = 0; in fll_factors()
2820 fll_div->fll_refclk_div++; in fll_factors()
2825 return -EINVAL; in fll_factors()
2834 /* Fvco should be 90-100MHz; don't check the upper bound */ in fll_factors()
2841 return -EINVAL; in fll_factors()
2845 fll_div->fll_outdiv = div - 1; in fll_factors()
2852 fll_div->fll_fratio = fll_fratios[i].fll_fratio; in fll_factors()
2859 return -EINVAL; in fll_factors()
2862 fll_div->n = target / (fratio * Fref); in fll_factors()
2865 fll_div->theta = 0; in fll_factors()
2866 fll_div->lambda = 1; in fll_factors()
2870 fll_div->theta = (target - (fll_div->n * fratio * Fref)) in fll_factors()
2872 fll_div->lambda = (fratio * Fref) / gcd_fll; in fll_factors()
2876 fll_div->n, fll_div->theta, fll_div->lambda); in fll_factors()
2878 fll_div->fll_fratio, fll_div->fll_outdiv, in fll_factors()
2879 fll_div->fll_refclk_div); in fll_factors()
2894 if (source == wm8962->fll_src && Fref == wm8962->fll_fref && in wm8962_set_fll()
2895 Fout == wm8962->fll_fout) in wm8962_set_fll()
2899 dev_dbg(component->dev, "FLL disabled\n"); in wm8962_set_fll()
2901 wm8962->fll_fref = 0; in wm8962_set_fll()
2902 wm8962->fll_fout = 0; in wm8962_set_fll()
2907 pm_runtime_put(component->dev); in wm8962_set_fll()
2922 fll1 |= (fll_id - 1) << WM8962_FLL_REFCLK_SRC_SHIFT; in wm8962_set_fll()
2925 fll1 |= (fll_id - 1) << WM8962_FLL_REFCLK_SRC_SHIFT; in wm8962_set_fll()
2936 dev_err(component->dev, "Unknown FLL source %d\n", source); in wm8962_set_fll()
2937 return -EINVAL; in wm8962_set_fll()
2959 reinit_completion(&wm8962->fll_lock); in wm8962_set_fll()
2961 ret = pm_runtime_resume_and_get(component->dev); in wm8962_set_fll()
2963 dev_err(component->dev, "Failed to resume device: %d\n", ret); in wm8962_set_fll()
2971 dev_dbg(component->dev, "FLL configured for %dHz->%dHz\n", Fref, Fout); in wm8962_set_fll()
2976 if (wm8962->irq) in wm8962_set_fll()
2981 time_left = wait_for_completion_timeout(&wm8962->fll_lock, in wm8962_set_fll()
2984 if (time_left == 0 && wm8962->irq) { in wm8962_set_fll()
2985 dev_err(component->dev, "FLL lock timed out"); in wm8962_set_fll()
2988 pm_runtime_put(component->dev); in wm8962_set_fll()
2989 return -ETIMEDOUT; in wm8962_set_fll()
2992 wm8962->fll_fref = Fref; in wm8962_set_fll()
2993 wm8962->fll_fout = Fout; in wm8962_set_fll()
2994 wm8962->fll_src = source; in wm8962_set_fll()
3001 struct snd_soc_component *component = dai->component; in wm8962_mute()
3061 struct snd_soc_component *component = wm8962->component; in wm8962_mic_work()
3078 snd_soc_jack_report(wm8962->jack, status, in wm8962_mic_work()
3100 ret = regmap_read(wm8962->regmap, WM8962_INTERRUPT_STATUS_2_MASK, in wm8962_irq()
3109 ret = regmap_read(wm8962->regmap, WM8962_INTERRUPT_STATUS_2, &active); in wm8962_irq()
3124 ret = regmap_write(wm8962->regmap, WM8962_INTERRUPT_STATUS_2, active); in wm8962_irq()
3130 complete(&wm8962->fll_lock); in wm8962_irq()
3139 ret = regmap_read(wm8962->regmap, in wm8962_irq()
3167 &wm8962->mic_work, in wm8962_irq()
3177 * wm8962_mic_detect - Enable microphone detection via the WM8962 IRQ
3195 wm8962->jack = jack; in wm8962_mic_detect()
3210 snd_soc_jack_report(wm8962->jack, 0, in wm8962_mic_detect()
3237 struct snd_soc_component *component = wm8962->component; in wm8962_beep_work()
3243 if (wm8962->beep_rate) { in wm8962_beep_work()
3245 if (abs(wm8962->beep_rate - beep_rates[i]) < in wm8962_beep_work()
3246 abs(wm8962->beep_rate - beep_rates[best])) in wm8962_beep_work()
3250 dev_dbg(component->dev, "Set beep rate %dHz for requested %dHz\n", in wm8962_beep_work()
3251 beep_rates[best], wm8962->beep_rate); in wm8962_beep_work()
3257 dev_dbg(component->dev, "Disabling beep\n"); in wm8962_beep_work()
3267 /* For usability define a way of injecting beep events for the device -
3276 dev_dbg(component->dev, "Beep event %x %x\n", code, hz); in wm8962_beep_event()
3286 return -1; in wm8962_beep_event()
3290 wm8962->beep_rate = hz; in wm8962_beep_event()
3291 schedule_work(&wm8962->beep_work); in wm8962_beep_event()
3306 input_event(wm8962->beep, EV_SND, SND_TONE, time); in beep_store()
3318 wm8962->beep = devm_input_allocate_device(component->dev); in wm8962_init_beep()
3319 if (!wm8962->beep) { in wm8962_init_beep()
3320 dev_err(component->dev, "Failed to allocate beep device\n"); in wm8962_init_beep()
3324 INIT_WORK(&wm8962->beep_work, wm8962_beep_work); in wm8962_init_beep()
3325 wm8962->beep_rate = 0; in wm8962_init_beep()
3327 wm8962->beep->name = "WM8962 Beep Generator"; in wm8962_init_beep()
3328 wm8962->beep->phys = dev_name(component->dev); in wm8962_init_beep()
3329 wm8962->beep->id.bustype = BUS_I2C; in wm8962_init_beep()
3331 wm8962->beep->evbit[0] = BIT_MASK(EV_SND); in wm8962_init_beep()
3332 wm8962->beep->sndbit[0] = BIT_MASK(SND_BELL) | BIT_MASK(SND_TONE); in wm8962_init_beep()
3333 wm8962->beep->event = wm8962_beep_event; in wm8962_init_beep()
3334 wm8962->beep->dev.parent = component->dev; in wm8962_init_beep()
3335 input_set_drvdata(wm8962->beep, component); in wm8962_init_beep()
3337 ret = input_register_device(wm8962->beep); in wm8962_init_beep()
3339 wm8962->beep = NULL; in wm8962_init_beep()
3340 dev_err(component->dev, "Failed to register beep device\n"); in wm8962_init_beep()
3343 ret = device_create_file(component->dev, &dev_attr_beep); in wm8962_init_beep()
3345 dev_err(component->dev, "Failed to create keyclick file: %d\n", in wm8962_init_beep()
3354 device_remove_file(component->dev, &dev_attr_beep); in wm8962_free_beep()
3355 cancel_work_sync(&wm8962->beep_work); in wm8962_free_beep()
3356 wm8962->beep = NULL; in wm8962_free_beep()
3382 regmap_update_bits(wm8962->regmap, WM8962_ANALOGUE_CLOCKING1, in wm8962_set_gpio_mode()
3402 return -EINVAL; in wm8962_gpio_request()
3413 struct snd_soc_component *component = wm8962->component; in wm8962_gpio_set()
3423 struct snd_soc_component *component = wm8962->component; in wm8962_gpio_direction_out()
3449 struct wm8962_pdata *pdata = &wm8962->pdata; in wm8962_init_gpio()
3452 wm8962->gpio_chip = wm8962_template_chip; in wm8962_init_gpio()
3453 wm8962->gpio_chip.ngpio = WM8962_MAX_GPIO; in wm8962_init_gpio()
3454 wm8962->gpio_chip.parent = component->dev; in wm8962_init_gpio()
3456 if (pdata->gpio_base) in wm8962_init_gpio()
3457 wm8962->gpio_chip.base = pdata->gpio_base; in wm8962_init_gpio()
3459 wm8962->gpio_chip.base = -1; in wm8962_init_gpio()
3461 ret = gpiochip_add_data(&wm8962->gpio_chip, wm8962); in wm8962_init_gpio()
3463 dev_err(component->dev, "Failed to add GPIOs: %d\n", ret); in wm8962_init_gpio()
3470 gpiochip_remove(&wm8962->gpio_chip); in wm8962_free_gpio()
3490 wm8962->component = component; in wm8962_probe()
3492 wm8962->disable_nb[0].notifier_call = wm8962_regulator_event_0; in wm8962_probe()
3493 wm8962->disable_nb[1].notifier_call = wm8962_regulator_event_1; in wm8962_probe()
3494 wm8962->disable_nb[2].notifier_call = wm8962_regulator_event_2; in wm8962_probe()
3495 wm8962->disable_nb[3].notifier_call = wm8962_regulator_event_3; in wm8962_probe()
3496 wm8962->disable_nb[4].notifier_call = wm8962_regulator_event_4; in wm8962_probe()
3497 wm8962->disable_nb[5].notifier_call = wm8962_regulator_event_5; in wm8962_probe()
3498 wm8962->disable_nb[6].notifier_call = wm8962_regulator_event_6; in wm8962_probe()
3499 wm8962->disable_nb[7].notifier_call = wm8962_regulator_event_7; in wm8962_probe()
3502 for (i = 0; i < ARRAY_SIZE(wm8962->supplies); i++) { in wm8962_probe()
3504 wm8962->supplies[i].consumer, in wm8962_probe()
3505 &wm8962->disable_nb[i]); in wm8962_probe()
3507 dev_err(component->dev, in wm8962_probe()
3538 dev_dbg(component->dev, "DMIC not in use, disabling\n"); in wm8962_probe()
3542 dev_warn(component->dev, "DMIC GPIOs partially configured\n"); in wm8962_probe()
3554 cancel_delayed_work_sync(&wm8962->mic_work); in wm8962_remove()
3591 const struct device_node *np = i2c->dev.of_node; in wm8962_set_pdata_from_of()
3595 if (of_property_read_bool(np, "spk-mono")) in wm8962_set_pdata_from_of()
3596 pdata->spk_mono = true; in wm8962_set_pdata_from_of()
3598 if (of_property_read_u32(np, "mic-cfg", &val32) >= 0) in wm8962_set_pdata_from_of()
3599 pdata->mic_cfg = val32; in wm8962_set_pdata_from_of()
3601 if (of_property_read_u32_array(np, "gpio-cfg", pdata->gpio_init, in wm8962_set_pdata_from_of()
3602 ARRAY_SIZE(pdata->gpio_init)) >= 0) in wm8962_set_pdata_from_of()
3603 for (i = 0; i < ARRAY_SIZE(pdata->gpio_init); i++) { in wm8962_set_pdata_from_of()
3609 if (pdata->gpio_init[i] > 0xffff) in wm8962_set_pdata_from_of()
3610 pdata->gpio_init[i] = 0x0; in wm8962_set_pdata_from_of()
3613 pdata->mclk = devm_clk_get_optional(&i2c->dev, NULL); in wm8962_set_pdata_from_of()
3614 return PTR_ERR_OR_ZERO(pdata->mclk); in wm8962_set_pdata_from_of()
3619 struct wm8962_pdata *pdata = dev_get_platdata(&i2c->dev); in wm8962_i2c_probe()
3624 wm8962 = devm_kzalloc(&i2c->dev, sizeof(*wm8962), GFP_KERNEL); in wm8962_i2c_probe()
3626 return -ENOMEM; in wm8962_i2c_probe()
3628 mutex_init(&wm8962->dsp2_ena_lock); in wm8962_i2c_probe()
3632 INIT_DELAYED_WORK(&wm8962->mic_work, wm8962_mic_work); in wm8962_i2c_probe()
3633 init_completion(&wm8962->fll_lock); in wm8962_i2c_probe()
3634 wm8962->irq = i2c->irq; in wm8962_i2c_probe()
3638 memcpy(&wm8962->pdata, pdata, sizeof(struct wm8962_pdata)); in wm8962_i2c_probe()
3639 } else if (i2c->dev.of_node) { in wm8962_i2c_probe()
3640 ret = wm8962_set_pdata_from_of(i2c, &wm8962->pdata); in wm8962_i2c_probe()
3645 for (i = 0; i < ARRAY_SIZE(wm8962->supplies); i++) in wm8962_i2c_probe()
3646 wm8962->supplies[i].supply = wm8962_supply_names[i]; in wm8962_i2c_probe()
3648 ret = devm_regulator_bulk_get(&i2c->dev, ARRAY_SIZE(wm8962->supplies), in wm8962_i2c_probe()
3649 wm8962->supplies); in wm8962_i2c_probe()
3651 dev_err(&i2c->dev, "Failed to request supplies: %d\n", ret); in wm8962_i2c_probe()
3655 ret = regulator_bulk_enable(ARRAY_SIZE(wm8962->supplies), in wm8962_i2c_probe()
3656 wm8962->supplies); in wm8962_i2c_probe()
3658 dev_err(&i2c->dev, "Failed to enable supplies: %d\n", ret); in wm8962_i2c_probe()
3662 wm8962->regmap = devm_regmap_init_i2c(i2c, &wm8962_regmap); in wm8962_i2c_probe()
3663 if (IS_ERR(wm8962->regmap)) { in wm8962_i2c_probe()
3664 ret = PTR_ERR(wm8962->regmap); in wm8962_i2c_probe()
3665 dev_err(&i2c->dev, "Failed to allocate regmap: %d\n", ret); in wm8962_i2c_probe()
3674 regcache_cache_bypass(wm8962->regmap, true); in wm8962_i2c_probe()
3676 ret = regmap_read(wm8962->regmap, WM8962_SOFTWARE_RESET, ®); in wm8962_i2c_probe()
3678 dev_err(&i2c->dev, "Failed to read ID register\n"); in wm8962_i2c_probe()
3682 dev_err(&i2c->dev, in wm8962_i2c_probe()
3684 ret = -EINVAL; in wm8962_i2c_probe()
3688 ret = regmap_read(wm8962->regmap, WM8962_RIGHT_INPUT_VOLUME, ®); in wm8962_i2c_probe()
3690 dev_err(&i2c->dev, "Failed to read device revision: %d\n", in wm8962_i2c_probe()
3695 dev_info(&i2c->dev, "customer id %x revision %c\n", in wm8962_i2c_probe()
3700 regcache_cache_bypass(wm8962->regmap, false); in wm8962_i2c_probe()
3704 dev_err(&i2c->dev, "Failed to issue reset\n"); in wm8962_i2c_probe()
3711 regmap_update_bits(wm8962->regmap, WM8962_CLOCKING2, in wm8962_i2c_probe()
3715 regmap_update_bits(wm8962->regmap, WM8962_CLOCKING2, in wm8962_i2c_probe()
3719 regmap_update_bits(wm8962->regmap, WM8962_PLL2, in wm8962_i2c_probe()
3724 for (i = 0; i < ARRAY_SIZE(wm8962->pdata.gpio_init); i++) in wm8962_i2c_probe()
3725 if (wm8962->pdata.gpio_init[i]) { in wm8962_i2c_probe()
3727 regmap_write(wm8962->regmap, 0x200 + i, in wm8962_i2c_probe()
3728 wm8962->pdata.gpio_init[i] & 0xffff); in wm8962_i2c_probe()
3733 if (wm8962->pdata.spk_mono) in wm8962_i2c_probe()
3734 regmap_update_bits(wm8962->regmap, WM8962_CLASS_D_CONTROL_2, in wm8962_i2c_probe()
3739 if (wm8962->pdata.mic_cfg) in wm8962_i2c_probe()
3740 regmap_update_bits(wm8962->regmap, WM8962_ADDITIONAL_CONTROL_4, in wm8962_i2c_probe()
3745 wm8962->pdata.mic_cfg); in wm8962_i2c_probe()
3748 regmap_update_bits(wm8962->regmap, WM8962_LEFT_INPUT_VOLUME, in wm8962_i2c_probe()
3750 regmap_update_bits(wm8962->regmap, WM8962_RIGHT_INPUT_VOLUME, in wm8962_i2c_probe()
3752 regmap_update_bits(wm8962->regmap, WM8962_LEFT_ADC_VOLUME, in wm8962_i2c_probe()
3754 regmap_update_bits(wm8962->regmap, WM8962_RIGHT_ADC_VOLUME, in wm8962_i2c_probe()
3756 regmap_update_bits(wm8962->regmap, WM8962_LEFT_DAC_VOLUME, in wm8962_i2c_probe()
3758 regmap_update_bits(wm8962->regmap, WM8962_RIGHT_DAC_VOLUME, in wm8962_i2c_probe()
3760 regmap_update_bits(wm8962->regmap, WM8962_SPKOUTL_VOLUME, in wm8962_i2c_probe()
3762 regmap_update_bits(wm8962->regmap, WM8962_SPKOUTR_VOLUME, in wm8962_i2c_probe()
3764 regmap_update_bits(wm8962->regmap, WM8962_HPOUTL_VOLUME, in wm8962_i2c_probe()
3766 regmap_update_bits(wm8962->regmap, WM8962_HPOUTR_VOLUME, in wm8962_i2c_probe()
3770 regmap_update_bits(wm8962->regmap, WM8962_EQ1, in wm8962_i2c_probe()
3774 regmap_update_bits(wm8962->regmap, WM8962_IRQ_DEBOUNCE, in wm8962_i2c_probe()
3779 if (wm8962->pdata.in4_dc_measure) { in wm8962_i2c_probe()
3780 ret = regmap_register_patch(wm8962->regmap, in wm8962_i2c_probe()
3784 dev_err(&i2c->dev, in wm8962_i2c_probe()
3789 if (wm8962->irq) { in wm8962_i2c_probe()
3790 if (wm8962->pdata.irq_active_low) { in wm8962_i2c_probe()
3798 regmap_update_bits(wm8962->regmap, WM8962_INTERRUPT_CONTROL, in wm8962_i2c_probe()
3801 ret = devm_request_threaded_irq(&i2c->dev, wm8962->irq, NULL, in wm8962_i2c_probe()
3804 "wm8962", &i2c->dev); in wm8962_i2c_probe()
3806 dev_err(&i2c->dev, "Failed to request IRQ %d: %d\n", in wm8962_i2c_probe()
3807 wm8962->irq, ret); in wm8962_i2c_probe()
3808 wm8962->irq = 0; in wm8962_i2c_probe()
3809 /* Non-fatal */ in wm8962_i2c_probe()
3812 regmap_update_bits(wm8962->regmap, in wm8962_i2c_probe()
3820 pm_runtime_enable(&i2c->dev); in wm8962_i2c_probe()
3821 pm_request_idle(&i2c->dev); in wm8962_i2c_probe()
3823 ret = devm_snd_soc_register_component(&i2c->dev, in wm8962_i2c_probe()
3828 regmap_update_bits(wm8962->regmap, WM8962_ADDITIONAL_CONTROL_4, in wm8962_i2c_probe()
3830 regmap_update_bits(wm8962->regmap, WM8962_ADDITIONAL_CONTROL_4, in wm8962_i2c_probe()
3833 regcache_cache_only(wm8962->regmap, true); in wm8962_i2c_probe()
3836 regulator_bulk_disable(ARRAY_SIZE(wm8962->supplies), wm8962->supplies); in wm8962_i2c_probe()
3841 pm_runtime_disable(&i2c->dev); in wm8962_i2c_probe()
3843 regulator_bulk_disable(ARRAY_SIZE(wm8962->supplies), wm8962->supplies); in wm8962_i2c_probe()
3850 pm_runtime_disable(&client->dev); in wm8962_i2c_remove()
3859 ret = clk_prepare_enable(wm8962->pdata.mclk); in wm8962_runtime_resume()
3865 ret = regulator_bulk_enable(ARRAY_SIZE(wm8962->supplies), in wm8962_runtime_resume()
3866 wm8962->supplies); in wm8962_runtime_resume()
3872 regcache_cache_only(wm8962->regmap, false); in wm8962_runtime_resume()
3876 regcache_mark_dirty(wm8962->regmap); in wm8962_runtime_resume()
3881 regmap_write_bits(wm8962->regmap, WM8962_CLOCKING2, in wm8962_runtime_resume()
3885 regmap_update_bits(wm8962->regmap, WM8962_CLOCKING2, in wm8962_runtime_resume()
3889 regmap_update_bits(wm8962->regmap, WM8962_PLL2, in wm8962_runtime_resume()
3893 regcache_sync(wm8962->regmap); in wm8962_runtime_resume()
3895 regmap_update_bits(wm8962->regmap, WM8962_ANTI_POP, in wm8962_runtime_resume()
3899 /* Bias enable at 2*5k (fast start-up) */ in wm8962_runtime_resume()
3900 regmap_update_bits(wm8962->regmap, WM8962_PWR_MGMT_1, in wm8962_runtime_resume()
3909 clk_disable_unprepare(wm8962->pdata.mclk); in wm8962_runtime_resume()
3917 regmap_update_bits(wm8962->regmap, WM8962_PWR_MGMT_1, in wm8962_runtime_suspend()
3920 regmap_update_bits(wm8962->regmap, WM8962_ANTI_POP, in wm8962_runtime_suspend()
3924 regcache_cache_only(wm8962->regmap, true); in wm8962_runtime_suspend()
3926 regulator_bulk_disable(ARRAY_SIZE(wm8962->supplies), in wm8962_runtime_suspend()
3927 wm8962->supplies); in wm8962_runtime_suspend()
3929 clk_disable_unprepare(wm8962->pdata.mclk); in wm8962_runtime_suspend()