Lines Matching +full:codec +full:- +full:aif1 +full:- +full:lrclk
1 // SPDX-License-Identifier: GPL-2.0-only
3 * wm8904.c -- WM8904 ALSA SoC Audio driver
5 * Copyright 2009-12 Wolfson Microelectronics plc
45 /* codec private data */
84 /* DC servo configuration - cached offset values */
89 { 4, 0x0018 }, /* R4 - Bias Control 0 */
90 { 5, 0x0000 }, /* R5 - VMID Control 0 */
91 { 6, 0x0000 }, /* R6 - Mic Bias Control 0 */
92 { 7, 0x0000 }, /* R7 - Mic Bias Control 1 */
93 { 8, 0x0001 }, /* R8 - Analogue DAC 0 */
94 { 9, 0x9696 }, /* R9 - mic Filter Control */
95 { 10, 0x0001 }, /* R10 - Analogue ADC 0 */
96 { 12, 0x0000 }, /* R12 - Power Management 0 */
97 { 14, 0x0000 }, /* R14 - Power Management 2 */
98 { 15, 0x0000 }, /* R15 - Power Management 3 */
99 { 18, 0x0000 }, /* R18 - Power Management 6 */
100 { 20, 0x945E }, /* R20 - Clock Rates 0 */
101 { 21, 0x0C05 }, /* R21 - Clock Rates 1 */
102 { 22, 0x0006 }, /* R22 - Clock Rates 2 */
103 { 24, 0x0050 }, /* R24 - Audio Interface 0 */
104 { 25, 0x000A }, /* R25 - Audio Interface 1 */
105 { 26, 0x00E4 }, /* R26 - Audio Interface 2 */
106 { 27, 0x0040 }, /* R27 - Audio Interface 3 */
107 { 30, 0x00C0 }, /* R30 - DAC Digital Volume Left */
108 { 31, 0x00C0 }, /* R31 - DAC Digital Volume Right */
109 { 32, 0x0000 }, /* R32 - DAC Digital 0 */
110 { 33, 0x0008 }, /* R33 - DAC Digital 1 */
111 { 36, 0x00C0 }, /* R36 - ADC Digital Volume Left */
112 { 37, 0x00C0 }, /* R37 - ADC Digital Volume Right */
113 { 38, 0x0010 }, /* R38 - ADC Digital 0 */
114 { 39, 0x0000 }, /* R39 - Digital Microphone 0 */
115 { 40, 0x01AF }, /* R40 - DRC 0 */
116 { 41, 0x3248 }, /* R41 - DRC 1 */
117 { 42, 0x0000 }, /* R42 - DRC 2 */
118 { 43, 0x0000 }, /* R43 - DRC 3 */
119 { 44, 0x0085 }, /* R44 - Analogue Left Input 0 */
120 { 45, 0x0085 }, /* R45 - Analogue Right Input 0 */
121 { 46, 0x0044 }, /* R46 - Analogue Left Input 1 */
122 { 47, 0x0044 }, /* R47 - Analogue Right Input 1 */
123 { 57, 0x002D }, /* R57 - Analogue OUT1 Left */
124 { 58, 0x002D }, /* R58 - Analogue OUT1 Right */
125 { 59, 0x0039 }, /* R59 - Analogue OUT2 Left */
126 { 60, 0x0039 }, /* R60 - Analogue OUT2 Right */
127 { 61, 0x0000 }, /* R61 - Analogue OUT12 ZC */
128 { 67, 0x0000 }, /* R67 - DC Servo 0 */
129 { 69, 0xAAAA }, /* R69 - DC Servo 2 */
130 { 71, 0xAAAA }, /* R71 - DC Servo 4 */
131 { 72, 0xAAAA }, /* R72 - DC Servo 5 */
132 { 90, 0x0000 }, /* R90 - Analogue HP 0 */
133 { 94, 0x0000 }, /* R94 - Analogue Lineout 0 */
134 { 98, 0x0000 }, /* R98 - Charge Pump 0 */
135 { 104, 0x0004 }, /* R104 - Class W 0 */
136 { 108, 0x0000 }, /* R108 - Write Sequencer 0 */
137 { 109, 0x0000 }, /* R109 - Write Sequencer 1 */
138 { 110, 0x0000 }, /* R110 - Write Sequencer 2 */
139 { 111, 0x0000 }, /* R111 - Write Sequencer 3 */
140 { 112, 0x0000 }, /* R112 - Write Sequencer 4 */
141 { 116, 0x0000 }, /* R116 - FLL Control 1 */
142 { 117, 0x0007 }, /* R117 - FLL Control 2 */
143 { 118, 0x0000 }, /* R118 - FLL Control 3 */
144 { 119, 0x2EE0 }, /* R119 - FLL Control 4 */
145 { 120, 0x0004 }, /* R120 - FLL Control 5 */
146 { 121, 0x0014 }, /* R121 - GPIO Control 1 */
147 { 122, 0x0010 }, /* R122 - GPIO Control 2 */
148 { 123, 0x0010 }, /* R123 - GPIO Control 3 */
149 { 124, 0x0000 }, /* R124 - GPIO Control 4 */
150 { 126, 0x0000 }, /* R126 - Digital Pulls */
151 { 128, 0xFFFF }, /* R128 - Interrupt Status Mask */
152 { 129, 0x0000 }, /* R129 - Interrupt Polarity */
153 { 130, 0x0000 }, /* R130 - Interrupt Debounce */
154 { 134, 0x0000 }, /* R134 - EQ1 */
155 { 135, 0x000C }, /* R135 - EQ2 */
156 { 136, 0x000C }, /* R136 - EQ3 */
157 { 137, 0x000C }, /* R137 - EQ4 */
158 { 138, 0x000C }, /* R138 - EQ5 */
159 { 139, 0x000C }, /* R139 - EQ6 */
160 { 140, 0x0FCA }, /* R140 - EQ7 */
161 { 141, 0x0400 }, /* R141 - EQ8 */
162 { 142, 0x00D8 }, /* R142 - EQ9 */
163 { 143, 0x1EB5 }, /* R143 - EQ10 */
164 { 144, 0xF145 }, /* R144 - EQ11 */
165 { 145, 0x0B75 }, /* R145 - EQ12 */
166 { 146, 0x01C5 }, /* R146 - EQ13 */
167 { 147, 0x1C58 }, /* R147 - EQ14 */
168 { 148, 0xF373 }, /* R148 - EQ15 */
169 { 149, 0x0A54 }, /* R149 - EQ16 */
170 { 150, 0x0558 }, /* R150 - EQ17 */
171 { 151, 0x168E }, /* R151 - EQ18 */
172 { 152, 0xF829 }, /* R152 - EQ19 */
173 { 153, 0x07AD }, /* R153 - EQ20 */
174 { 154, 0x1103 }, /* R154 - EQ21 */
175 { 155, 0x0564 }, /* R155 - EQ22 */
176 { 156, 0x0559 }, /* R156 - EQ23 */
177 { 157, 0x4000 }, /* R157 - EQ24 */
178 { 161, 0x0000 }, /* R161 - Control Interface Test 1 */
179 { 204, 0x0000 }, /* R204 - Analogue Output Bias 0 */
180 { 247, 0x0000 }, /* R247 - FLL NCO Test 0 */
181 { 248, 0x0019 }, /* R248 - FLL NCO Test 1 */
325 switch (wm8904->sysclk_src) { in wm8904_configure_clocking()
327 dev_dbg(component->dev, "Using %dHz MCLK\n", wm8904->mclk_rate); in wm8904_configure_clocking()
330 rate = wm8904->mclk_rate; in wm8904_configure_clocking()
338 dev_dbg(component->dev, "Using %dHz FLL clock\n", in wm8904_configure_clocking()
339 wm8904->fll_fout); in wm8904_configure_clocking()
342 rate = wm8904->fll_fout; in wm8904_configure_clocking()
346 dev_err(component->dev, "System clock not configured\n"); in wm8904_configure_clocking()
347 return -EINVAL; in wm8904_configure_clocking()
353 wm8904->sysclk_rate = rate / 2; in wm8904_configure_clocking()
356 wm8904->sysclk_rate = rate; in wm8904_configure_clocking()
365 dev_dbg(component->dev, "CLK_SYS is %dHz\n", wm8904->sysclk_rate); in wm8904_configure_clocking()
373 struct wm8904_pdata *pdata = wm8904->pdata; in wm8904_set_drc()
381 pdata->drc_cfgs[wm8904->drc_cfg].regs[i]); in wm8904_set_drc()
393 struct wm8904_pdata *pdata = wm8904->pdata; in wm8904_put_drc_enum()
394 int value = ucontrol->value.enumerated.item[0]; in wm8904_put_drc_enum()
396 if (value >= pdata->num_drc_cfgs) in wm8904_put_drc_enum()
397 return -EINVAL; in wm8904_put_drc_enum()
399 wm8904->drc_cfg = value; in wm8904_put_drc_enum()
412 ucontrol->value.enumerated.item[0] = wm8904->drc_cfg; in wm8904_get_drc_enum()
420 struct wm8904_pdata *pdata = wm8904->pdata; in wm8904_set_retune_mobile()
423 if (!pdata || !wm8904->num_retune_mobile_texts) in wm8904_set_retune_mobile()
428 cfg = wm8904->retune_mobile_cfg; in wm8904_set_retune_mobile()
431 for (i = 0; i < pdata->num_retune_mobile_cfgs; i++) { in wm8904_set_retune_mobile()
432 if (strcmp(pdata->retune_mobile_cfgs[i].name, in wm8904_set_retune_mobile()
433 wm8904->retune_mobile_texts[cfg]) == 0 && in wm8904_set_retune_mobile()
434 abs(pdata->retune_mobile_cfgs[i].rate in wm8904_set_retune_mobile()
435 - wm8904->fs) < best_val) { in wm8904_set_retune_mobile()
437 best_val = abs(pdata->retune_mobile_cfgs[i].rate in wm8904_set_retune_mobile()
438 - wm8904->fs); in wm8904_set_retune_mobile()
442 dev_dbg(component->dev, "ReTune Mobile %s/%dHz for %dHz sample rate\n", in wm8904_set_retune_mobile()
443 pdata->retune_mobile_cfgs[best].name, in wm8904_set_retune_mobile()
444 pdata->retune_mobile_cfgs[best].rate, in wm8904_set_retune_mobile()
445 wm8904->fs); in wm8904_set_retune_mobile()
454 pdata->retune_mobile_cfgs[best].regs[i]); in wm8904_set_retune_mobile()
464 struct wm8904_pdata *pdata = wm8904->pdata; in wm8904_put_retune_mobile_enum()
465 int value = ucontrol->value.enumerated.item[0]; in wm8904_put_retune_mobile_enum()
467 if (value >= pdata->num_retune_mobile_cfgs) in wm8904_put_retune_mobile_enum()
468 return -EINVAL; in wm8904_put_retune_mobile_enum()
470 wm8904->retune_mobile_cfg = value; in wm8904_put_retune_mobile_enum()
483 ucontrol->value.enumerated.item[0] = wm8904->retune_mobile_cfg; in wm8904_get_retune_mobile_enum()
498 if (wm8904->deemph) { in wm8904_set_deemph()
501 if (abs(deemph_settings[i] - wm8904->fs) < in wm8904_set_deemph()
502 abs(deemph_settings[best] - wm8904->fs)) in wm8904_set_deemph()
511 dev_dbg(component->dev, "Set deemphasis %d\n", val); in wm8904_set_deemph()
523 ucontrol->value.integer.value[0] = wm8904->deemph; in wm8904_get_deemph()
532 unsigned int deemph = ucontrol->value.integer.value[0]; in wm8904_put_deemph()
535 return -EINVAL; in wm8904_put_deemph()
537 wm8904->deemph = deemph; in wm8904_put_deemph()
543 static const DECLARE_TLV_DB_SCALE(digital_tlv, -7200, 75, 1);
544 static const DECLARE_TLV_DB_SCALE(out_tlv, -5700, 100, 0);
545 static const DECLARE_TLV_DB_SCALE(sidetone_tlv, -3600, 300, 0);
546 static const DECLARE_TLV_DB_SCALE(eq_tlv, -1200, 100, 0);
549 "Hi-fi", "Voice 1", "Voice 2", "Voice 3"
566 if (ucontrol->value.integer.value[0]) in wm8904_adc_osr_put()
645 return -EINVAL; in cp_event()
656 struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm); in sysclk_event()
666 switch (wm8904->sysclk_src) { in sysclk_event()
694 struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm); in out_pga_event()
708 reg = w->shift; in out_pga_event()
731 return -EINVAL; in out_pga_event()
759 if (wm8904->dcs_state[dcs_l] || wm8904->dcs_state[dcs_r]) { in out_pga_event()
760 dev_dbg(component->dev, "Restoring DC servo state\n"); in out_pga_event()
763 wm8904->dcs_state[dcs_l]); in out_pga_event()
765 wm8904->dcs_state[dcs_r]); in out_pga_event()
771 dev_dbg(component->dev, "Calibrating DC servo\n"); in out_pga_event()
787 } while (--timeout); in out_pga_event()
790 dev_warn(component->dev, "DC servo timed out\n"); in out_pga_event()
792 dev_dbg(component->dev, "DC servo ready\n"); in out_pga_event()
824 wm8904->dcs_state[dcs_l] = snd_soc_component_read(component, dcs_l_reg); in out_pga_event()
825 wm8904->dcs_state[dcs_r] = snd_soc_component_read(component, dcs_r_reg); in out_pga_event()
848 "Single-Ended", "Differential Line", "Differential Mic"
1072 { "Left Capture Mode", "Single-Ended", "Left Capture Inverting Mux" },
1086 { "Right Capture Mode", "Single-Ended", "Right Capture Inverting Mux" },
1194 switch (wm8904->devtype) { in wm8904_add_widgets()
1297 struct snd_soc_component *component = dai->component; in wm8904_hw_params()
1300 unsigned int aif1 = 0; in wm8904_hw_params() local
1307 wm8904->fs = params_rate(params); in wm8904_hw_params()
1308 if (wm8904->tdm_slots) { in wm8904_hw_params()
1309 dev_dbg(component->dev, "Configuring for %d %d bit TDM slots\n", in wm8904_hw_params()
1310 wm8904->tdm_slots, wm8904->tdm_width); in wm8904_hw_params()
1311 wm8904->bclk = snd_soc_calc_bclk(wm8904->fs, in wm8904_hw_params()
1312 wm8904->tdm_width, 2, in wm8904_hw_params()
1313 wm8904->tdm_slots); in wm8904_hw_params()
1315 wm8904->bclk = snd_soc_params_to_bclk(params); in wm8904_hw_params()
1322 aif1 |= 0x40; in wm8904_hw_params()
1325 aif1 |= 0x80; in wm8904_hw_params()
1328 aif1 |= 0xc0; in wm8904_hw_params()
1331 return -EINVAL; in wm8904_hw_params()
1335 dev_dbg(component->dev, "Target BCLK is %dHz\n", wm8904->bclk); in wm8904_hw_params()
1343 best_val = abs((wm8904->sysclk_rate / clk_sys_rates[0].ratio) in wm8904_hw_params()
1344 - wm8904->fs); in wm8904_hw_params()
1346 cur_val = abs((wm8904->sysclk_rate / in wm8904_hw_params()
1347 clk_sys_rates[i].ratio) - wm8904->fs); in wm8904_hw_params()
1353 dev_dbg(component->dev, "Selected CLK_SYS_RATIO of %d\n", in wm8904_hw_params()
1360 best_val = abs(wm8904->fs - sample_rates[0].rate); in wm8904_hw_params()
1363 cur_val = abs(wm8904->fs - sample_rates[i].rate); in wm8904_hw_params()
1369 dev_dbg(component->dev, "Selected SAMPLE_RATE of %dHz\n", in wm8904_hw_params()
1375 if (wm8904->fs <= 24000) in wm8904_hw_params()
1382 cur_val = ((wm8904->sysclk_rate * 10) / bclk_divs[i].div) in wm8904_hw_params()
1383 - wm8904->bclk; in wm8904_hw_params()
1391 wm8904->bclk = (wm8904->sysclk_rate * 10) / bclk_divs[best].div; in wm8904_hw_params()
1392 dev_dbg(component->dev, "Selected BCLK_DIV of %d for %dHz BCLK\n", in wm8904_hw_params()
1393 bclk_divs[best].div, wm8904->bclk); in wm8904_hw_params()
1396 /* LRCLK is a simple fraction of BCLK */ in wm8904_hw_params()
1397 dev_dbg(component->dev, "LRCLK_RATE is %d\n", wm8904->bclk / wm8904->fs); in wm8904_hw_params()
1398 aif3 |= wm8904->bclk / wm8904->fs; in wm8904_hw_params()
1404 WM8904_AIF_WL_MASK, aif1); in wm8904_hw_params()
1422 struct snd_soc_component *component = dai->component; in wm8904_set_fmt()
1423 unsigned int aif1 = 0; in wm8904_set_fmt() local
1433 aif1 |= WM8904_BCLK_DIR; in wm8904_set_fmt()
1436 aif1 |= WM8904_BCLK_DIR; in wm8904_set_fmt()
1440 return -EINVAL; in wm8904_set_fmt()
1445 aif1 |= 0x3 | WM8904_AIF_LRCLK_INV; in wm8904_set_fmt()
1448 aif1 |= 0x3; in wm8904_set_fmt()
1451 aif1 |= 0x2; in wm8904_set_fmt()
1456 aif1 |= 0x1; in wm8904_set_fmt()
1459 return -EINVAL; in wm8904_set_fmt()
1470 aif1 |= WM8904_AIF_BCLK_INV; in wm8904_set_fmt()
1473 return -EINVAL; in wm8904_set_fmt()
1484 aif1 |= WM8904_AIF_BCLK_INV | WM8904_AIF_LRCLK_INV; in wm8904_set_fmt()
1487 aif1 |= WM8904_AIF_BCLK_INV; in wm8904_set_fmt()
1490 aif1 |= WM8904_AIF_LRCLK_INV; in wm8904_set_fmt()
1493 return -EINVAL; in wm8904_set_fmt()
1497 return -EINVAL; in wm8904_set_fmt()
1502 WM8904_AIF_FMT_MASK | WM8904_BCLK_DIR, aif1); in wm8904_set_fmt()
1513 struct snd_soc_component *component = dai->component; in wm8904_set_tdm_slot()
1515 int aif1 = 0; in wm8904_set_tdm_slot() local
1521 /* Note that we allow configurations we can't handle ourselves - in wm8904_set_tdm_slot()
1525 aif1 |= WM8904_AIFADC_TDM | WM8904_AIFDAC_TDM; in wm8904_set_tdm_slot()
1531 aif1 |= WM8904_AIFADC_TDM_CHAN; in wm8904_set_tdm_slot()
1534 return -EINVAL; in wm8904_set_tdm_slot()
1542 aif1 |= WM8904_AIFDAC_TDM_CHAN; in wm8904_set_tdm_slot()
1545 return -EINVAL; in wm8904_set_tdm_slot()
1549 wm8904->tdm_width = slot_width; in wm8904_set_tdm_slot()
1550 wm8904->tdm_slots = slots / 2; in wm8904_set_tdm_slot()
1554 WM8904_AIFDAC_TDM | WM8904_AIFDAC_TDM_CHAN, aif1); in wm8904_set_tdm_slot()
1594 fll_div->fll_clk_ref_div = 0; in fll_factors()
1597 fll_div->fll_clk_ref_div++; in fll_factors()
1602 return -EINVAL; in fll_factors()
1611 /* Fvco should be 90-100MHz; don't check the upper bound */ in fll_factors()
1618 return -EINVAL; in fll_factors()
1622 fll_div->fll_outdiv = div - 1; in fll_factors()
1629 fll_div->fll_fratio = fll_fratios[i].fll_fratio; in fll_factors()
1636 return -EINVAL; in fll_factors()
1642 fll_div->n = Ndiv; in fll_factors()
1646 /* Calculate fractional part - scale up so we can round. */ in fll_factors()
1657 fll_div->k = K / 10; in fll_factors()
1660 fll_div->n, fll_div->k, in fll_factors()
1661 fll_div->fll_fratio, fll_div->fll_outdiv, in fll_factors()
1662 fll_div->fll_clk_ref_div); in fll_factors()
1670 struct snd_soc_component *component = dai->component; in wm8904_set_fll()
1677 if (source == wm8904->fll_src && Fref == wm8904->fll_fref && in wm8904_set_fll()
1678 Fout == wm8904->fll_fout) in wm8904_set_fll()
1684 dev_dbg(component->dev, "FLL disabled\n"); in wm8904_set_fll()
1686 wm8904->fll_fref = 0; in wm8904_set_fll()
1687 wm8904->fll_fout = 0; in wm8904_set_fll()
1710 dev_dbg(component->dev, "Using free running FLL\n"); in wm8904_set_fll()
1720 dev_err(component->dev, "Unknown FLL ID %d\n", fll_id); in wm8904_set_fll()
1721 return -EINVAL; in wm8904_set_fll()
1786 dev_dbg(component->dev, "FLL configured for %dHz->%dHz\n", Fref, Fout); in wm8904_set_fll()
1788 wm8904->fll_fref = Fref; in wm8904_set_fll()
1789 wm8904->fll_fout = Fout; in wm8904_set_fll()
1790 wm8904->fll_src = source; in wm8904_set_fll()
1809 struct snd_soc_component *component = dai->component; in wm8904_set_sysclk()
1822 mclk_freq = clk_get_rate(priv->mclk); in wm8904_set_sysclk()
1825 priv->sysclk_src = WM8904_CLK_FLL; in wm8904_set_sysclk()
1837 priv->sysclk_src = clk_id; in wm8904_set_sysclk()
1838 priv->mclk_rate = freq; in wm8904_set_sysclk()
1842 priv->sysclk_src = clk_id; in wm8904_set_sysclk()
1846 return -EINVAL; in wm8904_set_sysclk()
1849 dev_dbg(dai->dev, "Clock source is %d at %uHz\n", clk_id, freq); in wm8904_set_sysclk()
1858 struct snd_soc_component *component = codec_dai->component; in wm8904_mute()
1894 ret = regulator_bulk_enable(ARRAY_SIZE(wm8904->supplies), in wm8904_set_bias_level()
1895 wm8904->supplies); in wm8904_set_bias_level()
1897 dev_err(component->dev, in wm8904_set_bias_level()
1903 ret = clk_prepare_enable(wm8904->mclk); in wm8904_set_bias_level()
1905 dev_err(component->dev, in wm8904_set_bias_level()
1907 regulator_bulk_disable(ARRAY_SIZE(wm8904->supplies), in wm8904_set_bias_level()
1908 wm8904->supplies); in wm8904_set_bias_level()
1912 regcache_cache_only(wm8904->regmap, false); in wm8904_set_bias_level()
1913 regcache_sync(wm8904->regmap); in wm8904_set_bias_level()
1950 regcache_cache_only(wm8904->regmap, true); in wm8904_set_bias_level()
1951 regcache_mark_dirty(wm8904->regmap); in wm8904_set_bias_level()
1953 regulator_bulk_disable(ARRAY_SIZE(wm8904->supplies), in wm8904_set_bias_level()
1954 wm8904->supplies); in wm8904_set_bias_level()
1955 clk_disable_unprepare(wm8904->mclk); in wm8904_set_bias_level()
1977 .name = "wm8904-hifi",
1999 struct wm8904_pdata *pdata = wm8904->pdata; in wm8904_handle_retune_mobile_pdata()
2002 wm8904->retune_mobile_enum, in wm8904_handle_retune_mobile_pdata()
2012 wm8904->num_retune_mobile_texts = 0; in wm8904_handle_retune_mobile_pdata()
2013 wm8904->retune_mobile_texts = NULL; in wm8904_handle_retune_mobile_pdata()
2014 for (i = 0; i < pdata->num_retune_mobile_cfgs; i++) { in wm8904_handle_retune_mobile_pdata()
2015 for (j = 0; j < wm8904->num_retune_mobile_texts; j++) { in wm8904_handle_retune_mobile_pdata()
2016 if (strcmp(pdata->retune_mobile_cfgs[i].name, in wm8904_handle_retune_mobile_pdata()
2017 wm8904->retune_mobile_texts[j]) == 0) in wm8904_handle_retune_mobile_pdata()
2021 if (j != wm8904->num_retune_mobile_texts) in wm8904_handle_retune_mobile_pdata()
2025 t = krealloc(wm8904->retune_mobile_texts, in wm8904_handle_retune_mobile_pdata()
2027 (wm8904->num_retune_mobile_texts + 1), in wm8904_handle_retune_mobile_pdata()
2033 t[wm8904->num_retune_mobile_texts] = in wm8904_handle_retune_mobile_pdata()
2034 pdata->retune_mobile_cfgs[i].name; in wm8904_handle_retune_mobile_pdata()
2037 wm8904->num_retune_mobile_texts++; in wm8904_handle_retune_mobile_pdata()
2038 wm8904->retune_mobile_texts = t; in wm8904_handle_retune_mobile_pdata()
2041 dev_dbg(component->dev, "Allocated %d unique ReTune Mobile names\n", in wm8904_handle_retune_mobile_pdata()
2042 wm8904->num_retune_mobile_texts); in wm8904_handle_retune_mobile_pdata()
2044 wm8904->retune_mobile_enum.items = wm8904->num_retune_mobile_texts; in wm8904_handle_retune_mobile_pdata()
2045 wm8904->retune_mobile_enum.texts = wm8904->retune_mobile_texts; in wm8904_handle_retune_mobile_pdata()
2049 dev_err(component->dev, in wm8904_handle_retune_mobile_pdata()
2056 struct wm8904_pdata *pdata = wm8904->pdata; in wm8904_handle_pdata()
2065 dev_dbg(component->dev, "%d DRC configurations\n", pdata->num_drc_cfgs); in wm8904_handle_pdata()
2067 if (pdata->num_drc_cfgs) { in wm8904_handle_pdata()
2069 SOC_ENUM_EXT("DRC Mode", wm8904->drc_enum, in wm8904_handle_pdata()
2073 wm8904->drc_texts = kmalloc_array(pdata->num_drc_cfgs, in wm8904_handle_pdata()
2076 if (!wm8904->drc_texts) in wm8904_handle_pdata()
2079 for (i = 0; i < pdata->num_drc_cfgs; i++) in wm8904_handle_pdata()
2080 wm8904->drc_texts[i] = pdata->drc_cfgs[i].name; in wm8904_handle_pdata()
2082 wm8904->drc_enum.items = pdata->num_drc_cfgs; in wm8904_handle_pdata()
2083 wm8904->drc_enum.texts = wm8904->drc_texts; in wm8904_handle_pdata()
2087 dev_err(component->dev, in wm8904_handle_pdata()
2093 dev_dbg(component->dev, "%d ReTune Mobile configurations\n", in wm8904_handle_pdata()
2094 pdata->num_retune_mobile_cfgs); in wm8904_handle_pdata()
2096 if (pdata->num_retune_mobile_cfgs) in wm8904_handle_pdata()
2108 switch (wm8904->devtype) { in wm8904_probe()
2115 dev_err(component->dev, "Unknown device type %d\n", in wm8904_probe()
2116 wm8904->devtype); in wm8904_probe()
2117 return -EINVAL; in wm8904_probe()
2131 kfree(wm8904->retune_mobile_texts); in wm8904_remove()
2132 kfree(wm8904->drc_texts); in wm8904_remove()
2179 wm8904 = devm_kzalloc(&i2c->dev, sizeof(struct wm8904_priv), in wm8904_i2c_probe()
2182 return -ENOMEM; in wm8904_i2c_probe()
2184 wm8904->mclk = devm_clk_get(&i2c->dev, "mclk"); in wm8904_i2c_probe()
2185 if (IS_ERR(wm8904->mclk)) { in wm8904_i2c_probe()
2186 ret = PTR_ERR(wm8904->mclk); in wm8904_i2c_probe()
2187 dev_err(&i2c->dev, "Failed to get MCLK\n"); in wm8904_i2c_probe()
2191 wm8904->regmap = devm_regmap_init_i2c(i2c, &wm8904_regmap); in wm8904_i2c_probe()
2192 if (IS_ERR(wm8904->regmap)) { in wm8904_i2c_probe()
2193 ret = PTR_ERR(wm8904->regmap); in wm8904_i2c_probe()
2194 dev_err(&i2c->dev, "Failed to allocate register map: %d\n", in wm8904_i2c_probe()
2199 if (i2c->dev.of_node) { in wm8904_i2c_probe()
2202 match = of_match_node(wm8904_of_match, i2c->dev.of_node); in wm8904_i2c_probe()
2204 return -EINVAL; in wm8904_i2c_probe()
2205 wm8904->devtype = (uintptr_t)match->data; in wm8904_i2c_probe()
2209 wm8904->devtype = id->driver_data; in wm8904_i2c_probe()
2213 wm8904->pdata = i2c->dev.platform_data; in wm8904_i2c_probe()
2215 for (i = 0; i < ARRAY_SIZE(wm8904->supplies); i++) in wm8904_i2c_probe()
2216 wm8904->supplies[i].supply = wm8904_supply_names[i]; in wm8904_i2c_probe()
2218 ret = devm_regulator_bulk_get(&i2c->dev, ARRAY_SIZE(wm8904->supplies), in wm8904_i2c_probe()
2219 wm8904->supplies); in wm8904_i2c_probe()
2221 dev_err(&i2c->dev, "Failed to request supplies: %d\n", ret); in wm8904_i2c_probe()
2225 ret = regulator_bulk_enable(ARRAY_SIZE(wm8904->supplies), in wm8904_i2c_probe()
2226 wm8904->supplies); in wm8904_i2c_probe()
2228 dev_err(&i2c->dev, "Failed to enable supplies: %d\n", ret); in wm8904_i2c_probe()
2232 ret = regmap_read(wm8904->regmap, WM8904_SW_RESET_AND_ID, &val); in wm8904_i2c_probe()
2234 dev_err(&i2c->dev, "Failed to read ID register: %d\n", ret); in wm8904_i2c_probe()
2238 dev_err(&i2c->dev, "Device is not a WM8904, ID is %x\n", val); in wm8904_i2c_probe()
2239 ret = -EINVAL; in wm8904_i2c_probe()
2243 ret = regmap_read(wm8904->regmap, WM8904_REVISION, &val); in wm8904_i2c_probe()
2245 dev_err(&i2c->dev, "Failed to read device revision: %d\n", in wm8904_i2c_probe()
2249 dev_info(&i2c->dev, "revision %c\n", val + 'A'); in wm8904_i2c_probe()
2251 ret = regmap_write(wm8904->regmap, WM8904_SW_RESET_AND_ID, 0); in wm8904_i2c_probe()
2253 dev_err(&i2c->dev, "Failed to issue reset: %d\n", ret); in wm8904_i2c_probe()
2257 /* Change some default settings - latch VU and enable ZC */ in wm8904_i2c_probe()
2258 regmap_update_bits(wm8904->regmap, WM8904_ADC_DIGITAL_VOLUME_LEFT, in wm8904_i2c_probe()
2260 regmap_update_bits(wm8904->regmap, WM8904_ADC_DIGITAL_VOLUME_RIGHT, in wm8904_i2c_probe()
2262 regmap_update_bits(wm8904->regmap, WM8904_DAC_DIGITAL_VOLUME_LEFT, in wm8904_i2c_probe()
2264 regmap_update_bits(wm8904->regmap, WM8904_DAC_DIGITAL_VOLUME_RIGHT, in wm8904_i2c_probe()
2266 regmap_update_bits(wm8904->regmap, WM8904_ANALOGUE_OUT1_LEFT, in wm8904_i2c_probe()
2269 regmap_update_bits(wm8904->regmap, WM8904_ANALOGUE_OUT1_RIGHT, in wm8904_i2c_probe()
2272 regmap_update_bits(wm8904->regmap, WM8904_ANALOGUE_OUT2_LEFT, in wm8904_i2c_probe()
2275 regmap_update_bits(wm8904->regmap, WM8904_ANALOGUE_OUT2_RIGHT, in wm8904_i2c_probe()
2278 regmap_update_bits(wm8904->regmap, WM8904_CLOCK_RATES_0, in wm8904_i2c_probe()
2282 if (wm8904->pdata) { in wm8904_i2c_probe()
2284 if (!wm8904->pdata->gpio_cfg[i]) in wm8904_i2c_probe()
2287 regmap_update_bits(wm8904->regmap, in wm8904_i2c_probe()
2290 wm8904->pdata->gpio_cfg[i]); in wm8904_i2c_probe()
2295 regmap_update_bits(wm8904->regmap, in wm8904_i2c_probe()
2298 wm8904->pdata->mic_cfg[i]); in wm8904_i2c_probe()
2301 /* Set Class W by default - this will be managed by the Class in wm8904_i2c_probe()
2304 regmap_update_bits(wm8904->regmap, WM8904_CLASS_W_0, in wm8904_i2c_probe()
2308 regmap_update_bits(wm8904->regmap, WM8904_BIAS_CONTROL_0, in wm8904_i2c_probe()
2312 regmap_read(wm8904->regmap, WM8904_ADC_TEST_0, &val); in wm8904_i2c_probe()
2315 regcache_cache_only(wm8904->regmap, true); in wm8904_i2c_probe()
2316 regulator_bulk_disable(ARRAY_SIZE(wm8904->supplies), wm8904->supplies); in wm8904_i2c_probe()
2318 ret = devm_snd_soc_register_component(&i2c->dev, in wm8904_i2c_probe()
2326 regulator_bulk_disable(ARRAY_SIZE(wm8904->supplies), wm8904->supplies); in wm8904_i2c_probe()