Lines Matching full:15
893 #define WM5100_SW_RST_DEV_ID1_MASK 0xFFFF /* SW_RST_DEV_ID1 - [15:0] */
894 #define WM5100_SW_RST_DEV_ID1_SHIFT 0 /* SW_RST_DEV_ID1 - [15:0] */
895 #define WM5100_SW_RST_DEV_ID1_WIDTH 16 /* SW_RST_DEV_ID1 - [15:0] */
1102 #define WM5100_ISRC1_INT1_ENA_SHIFT 15 /* ISRC1_INT1_ENA */
1159 #define WM5100_ISRC2_INT1_ENA_SHIFT 15 /* ISRC2_INT1_ENA */
1215 #define WM5100_FLL1_THETA_MASK 0xFFFF /* FLL1_THETA - [15:0] */
1216 #define WM5100_FLL1_THETA_SHIFT 0 /* FLL1_THETA - [15:0] */
1217 #define WM5100_FLL1_THETA_WIDTH 16 /* FLL1_THETA - [15:0] */
1239 #define WM5100_FLL1_LAMBDA_MASK 0xFFFF /* FLL1_LAMBDA - [15:0] */
1240 #define WM5100_FLL1_LAMBDA_SHIFT 0 /* FLL1_LAMBDA - [15:0] */
1241 #define WM5100_FLL1_LAMBDA_WIDTH 16 /* FLL1_LAMBDA - [15:0] */
1264 #define WM5100_FLL2_THETA_MASK 0xFFFF /* FLL2_THETA - [15:0] */
1265 #define WM5100_FLL2_THETA_SHIFT 0 /* FLL2_THETA - [15:0] */
1266 #define WM5100_FLL2_THETA_WIDTH 16 /* FLL2_THETA - [15:0] */
1288 #define WM5100_FLL2_LAMBDA_MASK 0xFFFF /* FLL2_LAMBDA - [15:0] */
1289 #define WM5100_FLL2_LAMBDA_SHIFT 0 /* FLL2_LAMBDA - [15:0] */
1290 #define WM5100_FLL2_LAMBDA_WIDTH 16 /* FLL2_LAMBDA - [15:0] */
1307 #define WM5100_LDO2_VSEL_MASK 0xF800 /* LDO2_VSEL - [15:11] */
1308 #define WM5100_LDO2_VSEL_SHIFT 11 /* LDO2_VSEL - [15:11] */
1309 #define WM5100_LDO2_VSEL_WIDTH 5 /* LDO2_VSEL - [15:11] */
1399 #define WM5100_ACCDET_BIAS_SRC_MASK 0xC000 /* ACCDET_BIAS_SRC - [15:14] */
1400 #define WM5100_ACCDET_BIAS_SRC_SHIFT 14 /* ACCDET_BIAS_SRC - [15:14] */
1401 #define WM5100_ACCDET_BIAS_SRC_WIDTH 2 /* ACCDET_BIAS_SRC - [15:14] */
1442 #define WM5100_ACCDET_BIAS_STARTTIME_MASK 0xF000 /* ACCDET_BIAS_STARTTIME - [15:12] */
1443 #define WM5100_ACCDET_BIAS_STARTTIME_SHIFT 12 /* ACCDET_BIAS_STARTTIME - [15:12] */
1444 #define WM5100_ACCDET_BIAS_STARTTIME_WIDTH 4 /* ACCDET_BIAS_STARTTIME - [15:12] */
1560 #define WM5100_IN_RATE_MASK 0xC000 /* IN_RATE - [15:14] */
1561 #define WM5100_IN_RATE_SHIFT 14 /* IN_RATE - [15:14] */
1562 #define WM5100_IN_RATE_WIDTH 2 /* IN_RATE - [15:14] */
1908 #define WM5100_OUT_RATE_MASK 0xC000 /* OUT_RATE - [15:14] */
1909 #define WM5100_OUT_RATE_SHIFT 14 /* OUT_RATE - [15:14] */
1910 #define WM5100_OUT_RATE_WIDTH 2 /* OUT_RATE - [15:14] */
3007 #define WM5100_GP1_DIR_SHIFT 15 /* GP1_DIR */
3042 #define WM5100_GP2_DIR_SHIFT 15 /* GP2_DIR */
3077 #define WM5100_GP3_DIR_SHIFT 15 /* GP3_DIR */
3112 #define WM5100_GP4_DIR_SHIFT 15 /* GP4_DIR */
3147 #define WM5100_GP5_DIR_SHIFT 15 /* GP5_DIR */
3182 #define WM5100_GP6_DIR_SHIFT 15 /* GP6_DIR */
3217 #define WM5100_LDO1ENA_PD_SHIFT 15 /* LDO1ENA_PD */
3408 #define WM5100_SPK_SHUTDOWN_WARN_EINT_SHIFT 15 /* SPK_SHUTDOWN_WARN_EINT */
3544 #define WM5100_SPK_SHUTDOWN_WARN_STS_SHIFT 15 /* SPK_SHUTDOWN_WARN_STS */
3704 #define WM5100_IM_SPK_SHUTDOWN_WARN_EINT_SHIFT 15 /* IM_SPK_SHUTDOWN_WARN_EINT */
3854 #define WM5100_FX_STS_MASK 0xFFC0 /* FX_STS - [15:6] */
3855 #define WM5100_FX_STS_SHIFT 6 /* FX_STS - [15:6] */
3856 #define WM5100_FX_STS_WIDTH 10 /* FX_STS - [15:6] */
3864 #define WM5100_EQ1_B1_GAIN_MASK 0xF800 /* EQ1_B1_GAIN - [15:11] */
3865 #define WM5100_EQ1_B1_GAIN_SHIFT 11 /* EQ1_B1_GAIN - [15:11] */
3866 #define WM5100_EQ1_B1_GAIN_WIDTH 5 /* EQ1_B1_GAIN - [15:11] */
3881 #define WM5100_EQ1_B4_GAIN_MASK 0xF800 /* EQ1_B4_GAIN - [15:11] */
3882 #define WM5100_EQ1_B4_GAIN_SHIFT 11 /* EQ1_B4_GAIN - [15:11] */
3883 #define WM5100_EQ1_B4_GAIN_WIDTH 5 /* EQ1_B4_GAIN - [15:11] */
3891 #define WM5100_EQ1_B1_A_MASK 0xFFFF /* EQ1_B1_A - [15:0] */
3892 #define WM5100_EQ1_B1_A_SHIFT 0 /* EQ1_B1_A - [15:0] */
3893 #define WM5100_EQ1_B1_A_WIDTH 16 /* EQ1_B1_A - [15:0] */
3898 #define WM5100_EQ1_B1_B_MASK 0xFFFF /* EQ1_B1_B - [15:0] */
3899 #define WM5100_EQ1_B1_B_SHIFT 0 /* EQ1_B1_B - [15:0] */
3900 #define WM5100_EQ1_B1_B_WIDTH 16 /* EQ1_B1_B - [15:0] */
3905 #define WM5100_EQ1_B1_PG_MASK 0xFFFF /* EQ1_B1_PG - [15:0] */
3906 #define WM5100_EQ1_B1_PG_SHIFT 0 /* EQ1_B1_PG - [15:0] */
3907 #define WM5100_EQ1_B1_PG_WIDTH 16 /* EQ1_B1_PG - [15:0] */
3912 #define WM5100_EQ1_B2_A_MASK 0xFFFF /* EQ1_B2_A - [15:0] */
3913 #define WM5100_EQ1_B2_A_SHIFT 0 /* EQ1_B2_A - [15:0] */
3914 #define WM5100_EQ1_B2_A_WIDTH 16 /* EQ1_B2_A - [15:0] */
3919 #define WM5100_EQ1_B2_B_MASK 0xFFFF /* EQ1_B2_B - [15:0] */
3920 #define WM5100_EQ1_B2_B_SHIFT 0 /* EQ1_B2_B - [15:0] */
3921 #define WM5100_EQ1_B2_B_WIDTH 16 /* EQ1_B2_B - [15:0] */
3926 #define WM5100_EQ1_B2_C_MASK 0xFFFF /* EQ1_B2_C - [15:0] */
3927 #define WM5100_EQ1_B2_C_SHIFT 0 /* EQ1_B2_C - [15:0] */
3928 #define WM5100_EQ1_B2_C_WIDTH 16 /* EQ1_B2_C - [15:0] */
3933 #define WM5100_EQ1_B2_PG_MASK 0xFFFF /* EQ1_B2_PG - [15:0] */
3934 #define WM5100_EQ1_B2_PG_SHIFT 0 /* EQ1_B2_PG - [15:0] */
3935 #define WM5100_EQ1_B2_PG_WIDTH 16 /* EQ1_B2_PG - [15:0] */
3940 #define WM5100_EQ1_B3_A_MASK 0xFFFF /* EQ1_B3_A - [15:0] */
3941 #define WM5100_EQ1_B3_A_SHIFT 0 /* EQ1_B3_A - [15:0] */
3942 #define WM5100_EQ1_B3_A_WIDTH 16 /* EQ1_B3_A - [15:0] */
3947 #define WM5100_EQ1_B3_B_MASK 0xFFFF /* EQ1_B3_B - [15:0] */
3948 #define WM5100_EQ1_B3_B_SHIFT 0 /* EQ1_B3_B - [15:0] */
3949 #define WM5100_EQ1_B3_B_WIDTH 16 /* EQ1_B3_B - [15:0] */
3954 #define WM5100_EQ1_B3_C_MASK 0xFFFF /* EQ1_B3_C - [15:0] */
3955 #define WM5100_EQ1_B3_C_SHIFT 0 /* EQ1_B3_C - [15:0] */
3956 #define WM5100_EQ1_B3_C_WIDTH 16 /* EQ1_B3_C - [15:0] */
3961 #define WM5100_EQ1_B3_PG_MASK 0xFFFF /* EQ1_B3_PG - [15:0] */
3962 #define WM5100_EQ1_B3_PG_SHIFT 0 /* EQ1_B3_PG - [15:0] */
3963 #define WM5100_EQ1_B3_PG_WIDTH 16 /* EQ1_B3_PG - [15:0] */
3968 #define WM5100_EQ1_B4_A_MASK 0xFFFF /* EQ1_B4_A - [15:0] */
3969 #define WM5100_EQ1_B4_A_SHIFT 0 /* EQ1_B4_A - [15:0] */
3970 #define WM5100_EQ1_B4_A_WIDTH 16 /* EQ1_B4_A - [15:0] */
3975 #define WM5100_EQ1_B4_B_MASK 0xFFFF /* EQ1_B4_B - [15:0] */
3976 #define WM5100_EQ1_B4_B_SHIFT 0 /* EQ1_B4_B - [15:0] */
3977 #define WM5100_EQ1_B4_B_WIDTH 16 /* EQ1_B4_B - [15:0] */
3982 #define WM5100_EQ1_B4_C_MASK 0xFFFF /* EQ1_B4_C - [15:0] */
3983 #define WM5100_EQ1_B4_C_SHIFT 0 /* EQ1_B4_C - [15:0] */
3984 #define WM5100_EQ1_B4_C_WIDTH 16 /* EQ1_B4_C - [15:0] */
3989 #define WM5100_EQ1_B4_PG_MASK 0xFFFF /* EQ1_B4_PG - [15:0] */
3990 #define WM5100_EQ1_B4_PG_SHIFT 0 /* EQ1_B4_PG - [15:0] */
3991 #define WM5100_EQ1_B4_PG_WIDTH 16 /* EQ1_B4_PG - [15:0] */
3996 #define WM5100_EQ1_B5_A_MASK 0xFFFF /* EQ1_B5_A - [15:0] */
3997 #define WM5100_EQ1_B5_A_SHIFT 0 /* EQ1_B5_A - [15:0] */
3998 #define WM5100_EQ1_B5_A_WIDTH 16 /* EQ1_B5_A - [15:0] */
4003 #define WM5100_EQ1_B5_B_MASK 0xFFFF /* EQ1_B5_B - [15:0] */
4004 #define WM5100_EQ1_B5_B_SHIFT 0 /* EQ1_B5_B - [15:0] */
4005 #define WM5100_EQ1_B5_B_WIDTH 16 /* EQ1_B5_B - [15:0] */
4010 #define WM5100_EQ1_B5_PG_MASK 0xFFFF /* EQ1_B5_PG - [15:0] */
4011 #define WM5100_EQ1_B5_PG_SHIFT 0 /* EQ1_B5_PG - [15:0] */
4012 #define WM5100_EQ1_B5_PG_WIDTH 16 /* EQ1_B5_PG - [15:0] */
4017 #define WM5100_EQ2_B1_GAIN_MASK 0xF800 /* EQ2_B1_GAIN - [15:11] */
4018 #define WM5100_EQ2_B1_GAIN_SHIFT 11 /* EQ2_B1_GAIN - [15:11] */
4019 #define WM5100_EQ2_B1_GAIN_WIDTH 5 /* EQ2_B1_GAIN - [15:11] */
4034 #define WM5100_EQ2_B4_GAIN_MASK 0xF800 /* EQ2_B4_GAIN - [15:11] */
4035 #define WM5100_EQ2_B4_GAIN_SHIFT 11 /* EQ2_B4_GAIN - [15:11] */
4036 #define WM5100_EQ2_B4_GAIN_WIDTH 5 /* EQ2_B4_GAIN - [15:11] */
4044 #define WM5100_EQ2_B1_A_MASK 0xFFFF /* EQ2_B1_A - [15:0] */
4045 #define WM5100_EQ2_B1_A_SHIFT 0 /* EQ2_B1_A - [15:0] */
4046 #define WM5100_EQ2_B1_A_WIDTH 16 /* EQ2_B1_A - [15:0] */
4051 #define WM5100_EQ2_B1_B_MASK 0xFFFF /* EQ2_B1_B - [15:0] */
4052 #define WM5100_EQ2_B1_B_SHIFT 0 /* EQ2_B1_B - [15:0] */
4053 #define WM5100_EQ2_B1_B_WIDTH 16 /* EQ2_B1_B - [15:0] */
4058 #define WM5100_EQ2_B1_PG_MASK 0xFFFF /* EQ2_B1_PG - [15:0] */
4059 #define WM5100_EQ2_B1_PG_SHIFT 0 /* EQ2_B1_PG - [15:0] */
4060 #define WM5100_EQ2_B1_PG_WIDTH 16 /* EQ2_B1_PG - [15:0] */
4065 #define WM5100_EQ2_B2_A_MASK 0xFFFF /* EQ2_B2_A - [15:0] */
4066 #define WM5100_EQ2_B2_A_SHIFT 0 /* EQ2_B2_A - [15:0] */
4067 #define WM5100_EQ2_B2_A_WIDTH 16 /* EQ2_B2_A - [15:0] */
4072 #define WM5100_EQ2_B2_B_MASK 0xFFFF /* EQ2_B2_B - [15:0] */
4073 #define WM5100_EQ2_B2_B_SHIFT 0 /* EQ2_B2_B - [15:0] */
4074 #define WM5100_EQ2_B2_B_WIDTH 16 /* EQ2_B2_B - [15:0] */
4079 #define WM5100_EQ2_B2_C_MASK 0xFFFF /* EQ2_B2_C - [15:0] */
4080 #define WM5100_EQ2_B2_C_SHIFT 0 /* EQ2_B2_C - [15:0] */
4081 #define WM5100_EQ2_B2_C_WIDTH 16 /* EQ2_B2_C - [15:0] */
4086 #define WM5100_EQ2_B2_PG_MASK 0xFFFF /* EQ2_B2_PG - [15:0] */
4087 #define WM5100_EQ2_B2_PG_SHIFT 0 /* EQ2_B2_PG - [15:0] */
4088 #define WM5100_EQ2_B2_PG_WIDTH 16 /* EQ2_B2_PG - [15:0] */
4093 #define WM5100_EQ2_B3_A_MASK 0xFFFF /* EQ2_B3_A - [15:0] */
4094 #define WM5100_EQ2_B3_A_SHIFT 0 /* EQ2_B3_A - [15:0] */
4095 #define WM5100_EQ2_B3_A_WIDTH 16 /* EQ2_B3_A - [15:0] */
4100 #define WM5100_EQ2_B3_B_MASK 0xFFFF /* EQ2_B3_B - [15:0] */
4101 #define WM5100_EQ2_B3_B_SHIFT 0 /* EQ2_B3_B - [15:0] */
4102 #define WM5100_EQ2_B3_B_WIDTH 16 /* EQ2_B3_B - [15:0] */
4107 #define WM5100_EQ2_B3_C_MASK 0xFFFF /* EQ2_B3_C - [15:0] */
4108 #define WM5100_EQ2_B3_C_SHIFT 0 /* EQ2_B3_C - [15:0] */
4109 #define WM5100_EQ2_B3_C_WIDTH 16 /* EQ2_B3_C - [15:0] */
4114 #define WM5100_EQ2_B3_PG_MASK 0xFFFF /* EQ2_B3_PG - [15:0] */
4115 #define WM5100_EQ2_B3_PG_SHIFT 0 /* EQ2_B3_PG - [15:0] */
4116 #define WM5100_EQ2_B3_PG_WIDTH 16 /* EQ2_B3_PG - [15:0] */
4121 #define WM5100_EQ2_B4_A_MASK 0xFFFF /* EQ2_B4_A - [15:0] */
4122 #define WM5100_EQ2_B4_A_SHIFT 0 /* EQ2_B4_A - [15:0] */
4123 #define WM5100_EQ2_B4_A_WIDTH 16 /* EQ2_B4_A - [15:0] */
4128 #define WM5100_EQ2_B4_B_MASK 0xFFFF /* EQ2_B4_B - [15:0] */
4129 #define WM5100_EQ2_B4_B_SHIFT 0 /* EQ2_B4_B - [15:0] */
4130 #define WM5100_EQ2_B4_B_WIDTH 16 /* EQ2_B4_B - [15:0] */
4135 #define WM5100_EQ2_B4_C_MASK 0xFFFF /* EQ2_B4_C - [15:0] */
4136 #define WM5100_EQ2_B4_C_SHIFT 0 /* EQ2_B4_C - [15:0] */
4137 #define WM5100_EQ2_B4_C_WIDTH 16 /* EQ2_B4_C - [15:0] */
4142 #define WM5100_EQ2_B4_PG_MASK 0xFFFF /* EQ2_B4_PG - [15:0] */
4143 #define WM5100_EQ2_B4_PG_SHIFT 0 /* EQ2_B4_PG - [15:0] */
4144 #define WM5100_EQ2_B4_PG_WIDTH 16 /* EQ2_B4_PG - [15:0] */
4149 #define WM5100_EQ2_B5_A_MASK 0xFFFF /* EQ2_B5_A - [15:0] */
4150 #define WM5100_EQ2_B5_A_SHIFT 0 /* EQ2_B5_A - [15:0] */
4151 #define WM5100_EQ2_B5_A_WIDTH 16 /* EQ2_B5_A - [15:0] */
4156 #define WM5100_EQ2_B5_B_MASK 0xFFFF /* EQ2_B5_B - [15:0] */
4157 #define WM5100_EQ2_B5_B_SHIFT 0 /* EQ2_B5_B - [15:0] */
4158 #define WM5100_EQ2_B5_B_WIDTH 16 /* EQ2_B5_B - [15:0] */
4163 #define WM5100_EQ2_B5_PG_MASK 0xFFFF /* EQ2_B5_PG - [15:0] */
4164 #define WM5100_EQ2_B5_PG_SHIFT 0 /* EQ2_B5_PG - [15:0] */
4165 #define WM5100_EQ2_B5_PG_WIDTH 16 /* EQ2_B5_PG - [15:0] */
4170 #define WM5100_EQ3_B1_GAIN_MASK 0xF800 /* EQ3_B1_GAIN - [15:11] */
4171 #define WM5100_EQ3_B1_GAIN_SHIFT 11 /* EQ3_B1_GAIN - [15:11] */
4172 #define WM5100_EQ3_B1_GAIN_WIDTH 5 /* EQ3_B1_GAIN - [15:11] */
4187 #define WM5100_EQ3_B4_GAIN_MASK 0xF800 /* EQ3_B4_GAIN - [15:11] */
4188 #define WM5100_EQ3_B4_GAIN_SHIFT 11 /* EQ3_B4_GAIN - [15:11] */
4189 #define WM5100_EQ3_B4_GAIN_WIDTH 5 /* EQ3_B4_GAIN - [15:11] */
4197 #define WM5100_EQ3_B1_A_MASK 0xFFFF /* EQ3_B1_A - [15:0] */
4198 #define WM5100_EQ3_B1_A_SHIFT 0 /* EQ3_B1_A - [15:0] */
4199 #define WM5100_EQ3_B1_A_WIDTH 16 /* EQ3_B1_A - [15:0] */
4204 #define WM5100_EQ3_B1_B_MASK 0xFFFF /* EQ3_B1_B - [15:0] */
4205 #define WM5100_EQ3_B1_B_SHIFT 0 /* EQ3_B1_B - [15:0] */
4206 #define WM5100_EQ3_B1_B_WIDTH 16 /* EQ3_B1_B - [15:0] */
4211 #define WM5100_EQ3_B1_PG_MASK 0xFFFF /* EQ3_B1_PG - [15:0] */
4212 #define WM5100_EQ3_B1_PG_SHIFT 0 /* EQ3_B1_PG - [15:0] */
4213 #define WM5100_EQ3_B1_PG_WIDTH 16 /* EQ3_B1_PG - [15:0] */
4218 #define WM5100_EQ3_B2_A_MASK 0xFFFF /* EQ3_B2_A - [15:0] */
4219 #define WM5100_EQ3_B2_A_SHIFT 0 /* EQ3_B2_A - [15:0] */
4220 #define WM5100_EQ3_B2_A_WIDTH 16 /* EQ3_B2_A - [15:0] */
4225 #define WM5100_EQ3_B2_B_MASK 0xFFFF /* EQ3_B2_B - [15:0] */
4226 #define WM5100_EQ3_B2_B_SHIFT 0 /* EQ3_B2_B - [15:0] */
4227 #define WM5100_EQ3_B2_B_WIDTH 16 /* EQ3_B2_B - [15:0] */
4232 #define WM5100_EQ3_B2_C_MASK 0xFFFF /* EQ3_B2_C - [15:0] */
4233 #define WM5100_EQ3_B2_C_SHIFT 0 /* EQ3_B2_C - [15:0] */
4234 #define WM5100_EQ3_B2_C_WIDTH 16 /* EQ3_B2_C - [15:0] */
4239 #define WM5100_EQ3_B2_PG_MASK 0xFFFF /* EQ3_B2_PG - [15:0] */
4240 #define WM5100_EQ3_B2_PG_SHIFT 0 /* EQ3_B2_PG - [15:0] */
4241 #define WM5100_EQ3_B2_PG_WIDTH 16 /* EQ3_B2_PG - [15:0] */
4246 #define WM5100_EQ3_B3_A_MASK 0xFFFF /* EQ3_B3_A - [15:0] */
4247 #define WM5100_EQ3_B3_A_SHIFT 0 /* EQ3_B3_A - [15:0] */
4248 #define WM5100_EQ3_B3_A_WIDTH 16 /* EQ3_B3_A - [15:0] */
4253 #define WM5100_EQ3_B3_B_MASK 0xFFFF /* EQ3_B3_B - [15:0] */
4254 #define WM5100_EQ3_B3_B_SHIFT 0 /* EQ3_B3_B - [15:0] */
4255 #define WM5100_EQ3_B3_B_WIDTH 16 /* EQ3_B3_B - [15:0] */
4260 #define WM5100_EQ3_B3_C_MASK 0xFFFF /* EQ3_B3_C - [15:0] */
4261 #define WM5100_EQ3_B3_C_SHIFT 0 /* EQ3_B3_C - [15:0] */
4262 #define WM5100_EQ3_B3_C_WIDTH 16 /* EQ3_B3_C - [15:0] */
4267 #define WM5100_EQ3_B3_PG_MASK 0xFFFF /* EQ3_B3_PG - [15:0] */
4268 #define WM5100_EQ3_B3_PG_SHIFT 0 /* EQ3_B3_PG - [15:0] */
4269 #define WM5100_EQ3_B3_PG_WIDTH 16 /* EQ3_B3_PG - [15:0] */
4274 #define WM5100_EQ3_B4_A_MASK 0xFFFF /* EQ3_B4_A - [15:0] */
4275 #define WM5100_EQ3_B4_A_SHIFT 0 /* EQ3_B4_A - [15:0] */
4276 #define WM5100_EQ3_B4_A_WIDTH 16 /* EQ3_B4_A - [15:0] */
4281 #define WM5100_EQ3_B4_B_MASK 0xFFFF /* EQ3_B4_B - [15:0] */
4282 #define WM5100_EQ3_B4_B_SHIFT 0 /* EQ3_B4_B - [15:0] */
4283 #define WM5100_EQ3_B4_B_WIDTH 16 /* EQ3_B4_B - [15:0] */
4288 #define WM5100_EQ3_B4_C_MASK 0xFFFF /* EQ3_B4_C - [15:0] */
4289 #define WM5100_EQ3_B4_C_SHIFT 0 /* EQ3_B4_C - [15:0] */
4290 #define WM5100_EQ3_B4_C_WIDTH 16 /* EQ3_B4_C - [15:0] */
4295 #define WM5100_EQ3_B4_PG_MASK 0xFFFF /* EQ3_B4_PG - [15:0] */
4296 #define WM5100_EQ3_B4_PG_SHIFT 0 /* EQ3_B4_PG - [15:0] */
4297 #define WM5100_EQ3_B4_PG_WIDTH 16 /* EQ3_B4_PG - [15:0] */
4302 #define WM5100_EQ3_B5_A_MASK 0xFFFF /* EQ3_B5_A - [15:0] */
4303 #define WM5100_EQ3_B5_A_SHIFT 0 /* EQ3_B5_A - [15:0] */
4304 #define WM5100_EQ3_B5_A_WIDTH 16 /* EQ3_B5_A - [15:0] */
4309 #define WM5100_EQ3_B5_B_MASK 0xFFFF /* EQ3_B5_B - [15:0] */
4310 #define WM5100_EQ3_B5_B_SHIFT 0 /* EQ3_B5_B - [15:0] */
4311 #define WM5100_EQ3_B5_B_WIDTH 16 /* EQ3_B5_B - [15:0] */
4316 #define WM5100_EQ3_B5_PG_MASK 0xFFFF /* EQ3_B5_PG - [15:0] */
4317 #define WM5100_EQ3_B5_PG_SHIFT 0 /* EQ3_B5_PG - [15:0] */
4318 #define WM5100_EQ3_B5_PG_WIDTH 16 /* EQ3_B5_PG - [15:0] */
4323 #define WM5100_EQ4_B1_GAIN_MASK 0xF800 /* EQ4_B1_GAIN - [15:11] */
4324 #define WM5100_EQ4_B1_GAIN_SHIFT 11 /* EQ4_B1_GAIN - [15:11] */
4325 #define WM5100_EQ4_B1_GAIN_WIDTH 5 /* EQ4_B1_GAIN - [15:11] */
4340 #define WM5100_EQ4_B4_GAIN_MASK 0xF800 /* EQ4_B4_GAIN - [15:11] */
4341 #define WM5100_EQ4_B4_GAIN_SHIFT 11 /* EQ4_B4_GAIN - [15:11] */
4342 #define WM5100_EQ4_B4_GAIN_WIDTH 5 /* EQ4_B4_GAIN - [15:11] */
4350 #define WM5100_EQ4_B1_A_MASK 0xFFFF /* EQ4_B1_A - [15:0] */
4351 #define WM5100_EQ4_B1_A_SHIFT 0 /* EQ4_B1_A - [15:0] */
4352 #define WM5100_EQ4_B1_A_WIDTH 16 /* EQ4_B1_A - [15:0] */
4357 #define WM5100_EQ4_B1_B_MASK 0xFFFF /* EQ4_B1_B - [15:0] */
4358 #define WM5100_EQ4_B1_B_SHIFT 0 /* EQ4_B1_B - [15:0] */
4359 #define WM5100_EQ4_B1_B_WIDTH 16 /* EQ4_B1_B - [15:0] */
4364 #define WM5100_EQ4_B1_PG_MASK 0xFFFF /* EQ4_B1_PG - [15:0] */
4365 #define WM5100_EQ4_B1_PG_SHIFT 0 /* EQ4_B1_PG - [15:0] */
4366 #define WM5100_EQ4_B1_PG_WIDTH 16 /* EQ4_B1_PG - [15:0] */
4371 #define WM5100_EQ4_B2_A_MASK 0xFFFF /* EQ4_B2_A - [15:0] */
4372 #define WM5100_EQ4_B2_A_SHIFT 0 /* EQ4_B2_A - [15:0] */
4373 #define WM5100_EQ4_B2_A_WIDTH 16 /* EQ4_B2_A - [15:0] */
4378 #define WM5100_EQ4_B2_B_MASK 0xFFFF /* EQ4_B2_B - [15:0] */
4379 #define WM5100_EQ4_B2_B_SHIFT 0 /* EQ4_B2_B - [15:0] */
4380 #define WM5100_EQ4_B2_B_WIDTH 16 /* EQ4_B2_B - [15:0] */
4385 #define WM5100_EQ4_B2_C_MASK 0xFFFF /* EQ4_B2_C - [15:0] */
4386 #define WM5100_EQ4_B2_C_SHIFT 0 /* EQ4_B2_C - [15:0] */
4387 #define WM5100_EQ4_B2_C_WIDTH 16 /* EQ4_B2_C - [15:0] */
4392 #define WM5100_EQ4_B2_PG_MASK 0xFFFF /* EQ4_B2_PG - [15:0] */
4393 #define WM5100_EQ4_B2_PG_SHIFT 0 /* EQ4_B2_PG - [15:0] */
4394 #define WM5100_EQ4_B2_PG_WIDTH 16 /* EQ4_B2_PG - [15:0] */
4399 #define WM5100_EQ4_B3_A_MASK 0xFFFF /* EQ4_B3_A - [15:0] */
4400 #define WM5100_EQ4_B3_A_SHIFT 0 /* EQ4_B3_A - [15:0] */
4401 #define WM5100_EQ4_B3_A_WIDTH 16 /* EQ4_B3_A - [15:0] */
4406 #define WM5100_EQ4_B3_B_MASK 0xFFFF /* EQ4_B3_B - [15:0] */
4407 #define WM5100_EQ4_B3_B_SHIFT 0 /* EQ4_B3_B - [15:0] */
4408 #define WM5100_EQ4_B3_B_WIDTH 16 /* EQ4_B3_B - [15:0] */
4413 #define WM5100_EQ4_B3_C_MASK 0xFFFF /* EQ4_B3_C - [15:0] */
4414 #define WM5100_EQ4_B3_C_SHIFT 0 /* EQ4_B3_C - [15:0] */
4415 #define WM5100_EQ4_B3_C_WIDTH 16 /* EQ4_B3_C - [15:0] */
4420 #define WM5100_EQ4_B3_PG_MASK 0xFFFF /* EQ4_B3_PG - [15:0] */
4421 #define WM5100_EQ4_B3_PG_SHIFT 0 /* EQ4_B3_PG - [15:0] */
4422 #define WM5100_EQ4_B3_PG_WIDTH 16 /* EQ4_B3_PG - [15:0] */
4427 #define WM5100_EQ4_B4_A_MASK 0xFFFF /* EQ4_B4_A - [15:0] */
4428 #define WM5100_EQ4_B4_A_SHIFT 0 /* EQ4_B4_A - [15:0] */
4429 #define WM5100_EQ4_B4_A_WIDTH 16 /* EQ4_B4_A - [15:0] */
4434 #define WM5100_EQ4_B4_B_MASK 0xFFFF /* EQ4_B4_B - [15:0] */
4435 #define WM5100_EQ4_B4_B_SHIFT 0 /* EQ4_B4_B - [15:0] */
4436 #define WM5100_EQ4_B4_B_WIDTH 16 /* EQ4_B4_B - [15:0] */
4441 #define WM5100_EQ4_B4_C_MASK 0xFFFF /* EQ4_B4_C - [15:0] */
4442 #define WM5100_EQ4_B4_C_SHIFT 0 /* EQ4_B4_C - [15:0] */
4443 #define WM5100_EQ4_B4_C_WIDTH 16 /* EQ4_B4_C - [15:0] */
4448 #define WM5100_EQ4_B4_PG_MASK 0xFFFF /* EQ4_B4_PG - [15:0] */
4449 #define WM5100_EQ4_B4_PG_SHIFT 0 /* EQ4_B4_PG - [15:0] */
4450 #define WM5100_EQ4_B4_PG_WIDTH 16 /* EQ4_B4_PG - [15:0] */
4455 #define WM5100_EQ4_B5_A_MASK 0xFFFF /* EQ4_B5_A - [15:0] */
4456 #define WM5100_EQ4_B5_A_SHIFT 0 /* EQ4_B5_A - [15:0] */
4457 #define WM5100_EQ4_B5_A_WIDTH 16 /* EQ4_B5_A - [15:0] */
4462 #define WM5100_EQ4_B5_B_MASK 0xFFFF /* EQ4_B5_B - [15:0] */
4463 #define WM5100_EQ4_B5_B_SHIFT 0 /* EQ4_B5_B - [15:0] */
4464 #define WM5100_EQ4_B5_B_WIDTH 16 /* EQ4_B5_B - [15:0] */
4469 #define WM5100_EQ4_B5_PG_MASK 0xFFFF /* EQ4_B5_PG - [15:0] */
4470 #define WM5100_EQ4_B5_PG_SHIFT 0 /* EQ4_B5_PG - [15:0] */
4471 #define WM5100_EQ4_B5_PG_WIDTH 16 /* EQ4_B5_PG - [15:0] */
4476 #define WM5100_DRC_SIG_DET_RMS_MASK 0xF800 /* DRC_SIG_DET_RMS - [15:11] */
4477 #define WM5100_DRC_SIG_DET_RMS_SHIFT 11 /* DRC_SIG_DET_RMS - [15:11] */
4478 #define WM5100_DRC_SIG_DET_RMS_WIDTH 5 /* DRC_SIG_DET_RMS - [15:11] */
4534 #define WM5100_DRC_NG_MINGAIN_MASK 0xF000 /* DRC_NG_MINGAIN - [15:12] */
4535 #define WM5100_DRC_NG_MINGAIN_SHIFT 12 /* DRC_NG_MINGAIN - [15:12] */
4536 #define WM5100_DRC_NG_MINGAIN_WIDTH 4 /* DRC_NG_MINGAIN - [15:12] */
4588 #define WM5100_LHPF1_COEFF_MASK 0xFFFF /* LHPF1_COEFF - [15:0] */
4589 #define WM5100_LHPF1_COEFF_SHIFT 0 /* LHPF1_COEFF - [15:0] */
4590 #define WM5100_LHPF1_COEFF_WIDTH 16 /* LHPF1_COEFF - [15:0] */
4607 #define WM5100_LHPF2_COEFF_MASK 0xFFFF /* LHPF2_COEFF - [15:0] */
4608 #define WM5100_LHPF2_COEFF_SHIFT 0 /* LHPF2_COEFF - [15:0] */
4609 #define WM5100_LHPF2_COEFF_WIDTH 16 /* LHPF2_COEFF - [15:0] */
4626 #define WM5100_LHPF3_COEFF_MASK 0xFFFF /* LHPF3_COEFF - [15:0] */
4627 #define WM5100_LHPF3_COEFF_SHIFT 0 /* LHPF3_COEFF - [15:0] */
4628 #define WM5100_LHPF3_COEFF_WIDTH 16 /* LHPF3_COEFF - [15:0] */
4645 #define WM5100_LHPF4_COEFF_MASK 0xFFFF /* LHPF4_COEFF - [15:0] */
4646 #define WM5100_LHPF4_COEFF_SHIFT 0 /* LHPF4_COEFF - [15:0] */
4647 #define WM5100_LHPF4_COEFF_WIDTH 16 /* LHPF4_COEFF - [15:0] */
4652 #define WM5100_DSP2_RATE_MASK 0xC000 /* DSP2_RATE - [15:14] */
4653 #define WM5100_DSP2_RATE_SHIFT 14 /* DSP2_RATE - [15:14] */
4654 #define WM5100_DSP2_RATE_WIDTH 2 /* DSP2_RATE - [15:14] */
4675 #define WM5100_DSP1_RATE_MASK 0xC000 /* DSP1_RATE - [15:14] */
4676 #define WM5100_DSP1_RATE_SHIFT 14 /* DSP1_RATE - [15:14] */
4677 #define WM5100_DSP1_RATE_WIDTH 2 /* DSP1_RATE - [15:14] */
4698 #define WM5100_DSP3_RATE_MASK 0xC000 /* DSP3_RATE - [15:14] */
4699 #define WM5100_DSP3_RATE_SHIFT 14 /* DSP3_RATE - [15:14] */
4700 #define WM5100_DSP3_RATE_WIDTH 2 /* DSP3_RATE - [15:14] */
4728 #define WM5100_DSP1_DM_START_MASK 0xFFFF /* DSP1_DM_START - [15:0] */
4729 #define WM5100_DSP1_DM_START_SHIFT 0 /* DSP1_DM_START - [15:0] */
4730 #define WM5100_DSP1_DM_START_WIDTH 16 /* DSP1_DM_START - [15:0] */
4742 #define WM5100_DSP1_DM_1_MASK 0xFFFF /* DSP1_DM_1 - [15:0] */
4743 #define WM5100_DSP1_DM_1_SHIFT 0 /* DSP1_DM_1 - [15:0] */
4744 #define WM5100_DSP1_DM_1_WIDTH 16 /* DSP1_DM_1 - [15:0] */
4756 #define WM5100_DSP1_DM_254_MASK 0xFFFF /* DSP1_DM_254 - [15:0] */
4757 #define WM5100_DSP1_DM_254_SHIFT 0 /* DSP1_DM_254 - [15:0] */
4758 #define WM5100_DSP1_DM_254_WIDTH 16 /* DSP1_DM_254 - [15:0] */
4770 #define WM5100_DSP1_DM_END_MASK 0xFFFF /* DSP1_DM_END - [15:0] */
4771 #define WM5100_DSP1_DM_END_SHIFT 0 /* DSP1_DM_END - [15:0] */
4772 #define WM5100_DSP1_DM_END_WIDTH 16 /* DSP1_DM_END - [15:0] */
4784 #define WM5100_DSP1_PM_START_1_MASK 0xFFFF /* DSP1_PM_START - [15:0] */
4785 #define WM5100_DSP1_PM_START_1_SHIFT 0 /* DSP1_PM_START - [15:0] */
4786 #define WM5100_DSP1_PM_START_1_WIDTH 16 /* DSP1_PM_START - [15:0] */
4791 #define WM5100_DSP1_PM_START_MASK 0xFFFF /* DSP1_PM_START - [15:0] */
4792 #define WM5100_DSP1_PM_START_SHIFT 0 /* DSP1_PM_START - [15:0] */
4793 #define WM5100_DSP1_PM_START_WIDTH 16 /* DSP1_PM_START - [15:0] */
4805 #define WM5100_DSP1_PM_1_1_MASK 0xFFFF /* DSP1_PM_1 - [15:0] */
4806 #define WM5100_DSP1_PM_1_1_SHIFT 0 /* DSP1_PM_1 - [15:0] */
4807 #define WM5100_DSP1_PM_1_1_WIDTH 16 /* DSP1_PM_1 - [15:0] */
4812 #define WM5100_DSP1_PM_1_MASK 0xFFFF /* DSP1_PM_1 - [15:0] */
4813 #define WM5100_DSP1_PM_1_SHIFT 0 /* DSP1_PM_1 - [15:0] */
4814 #define WM5100_DSP1_PM_1_WIDTH 16 /* DSP1_PM_1 - [15:0] */
4826 #define WM5100_DSP1_PM_510_1_MASK 0xFFFF /* DSP1_PM_510 - [15:0] */
4827 #define WM5100_DSP1_PM_510_1_SHIFT 0 /* DSP1_PM_510 - [15:0] */
4828 #define WM5100_DSP1_PM_510_1_WIDTH 16 /* DSP1_PM_510 - [15:0] */
4833 #define WM5100_DSP1_PM_510_MASK 0xFFFF /* DSP1_PM_510 - [15:0] */
4834 #define WM5100_DSP1_PM_510_SHIFT 0 /* DSP1_PM_510 - [15:0] */
4835 #define WM5100_DSP1_PM_510_WIDTH 16 /* DSP1_PM_510 - [15:0] */
4847 #define WM5100_DSP1_PM_END_1_MASK 0xFFFF /* DSP1_PM_END - [15:0] */
4848 #define WM5100_DSP1_PM_END_1_SHIFT 0 /* DSP1_PM_END - [15:0] */
4849 #define WM5100_DSP1_PM_END_1_WIDTH 16 /* DSP1_PM_END - [15:0] */
4854 #define WM5100_DSP1_PM_END_MASK 0xFFFF /* DSP1_PM_END - [15:0] */
4855 #define WM5100_DSP1_PM_END_SHIFT 0 /* DSP1_PM_END - [15:0] */
4856 #define WM5100_DSP1_PM_END_WIDTH 16 /* DSP1_PM_END - [15:0] */
4868 #define WM5100_DSP1_ZM_START_MASK 0xFFFF /* DSP1_ZM_START - [15:0] */
4869 #define WM5100_DSP1_ZM_START_SHIFT 0 /* DSP1_ZM_START - [15:0] */
4870 #define WM5100_DSP1_ZM_START_WIDTH 16 /* DSP1_ZM_START - [15:0] */
4882 #define WM5100_DSP1_ZM_1_MASK 0xFFFF /* DSP1_ZM_1 - [15:0] */
4883 #define WM5100_DSP1_ZM_1_SHIFT 0 /* DSP1_ZM_1 - [15:0] */
4884 #define WM5100_DSP1_ZM_1_WIDTH 16 /* DSP1_ZM_1 - [15:0] */
4896 #define WM5100_DSP1_ZM_1022_MASK 0xFFFF /* DSP1_ZM_1022 - [15:0] */
4897 #define WM5100_DSP1_ZM_1022_SHIFT 0 /* DSP1_ZM_1022 - [15:0] */
4898 #define WM5100_DSP1_ZM_1022_WIDTH 16 /* DSP1_ZM_1022 - [15:0] */
4910 #define WM5100_DSP1_ZM_END_MASK 0xFFFF /* DSP1_ZM_END - [15:0] */
4911 #define WM5100_DSP1_ZM_END_SHIFT 0 /* DSP1_ZM_END - [15:0] */
4912 #define WM5100_DSP1_ZM_END_WIDTH 16 /* DSP1_ZM_END - [15:0] */
4924 #define WM5100_DSP2_DM_START_MASK 0xFFFF /* DSP2_DM_START - [15:0] */
4925 #define WM5100_DSP2_DM_START_SHIFT 0 /* DSP2_DM_START - [15:0] */
4926 #define WM5100_DSP2_DM_START_WIDTH 16 /* DSP2_DM_START - [15:0] */
4938 #define WM5100_DSP2_DM_1_MASK 0xFFFF /* DSP2_DM_1 - [15:0] */
4939 #define WM5100_DSP2_DM_1_SHIFT 0 /* DSP2_DM_1 - [15:0] */
4940 #define WM5100_DSP2_DM_1_WIDTH 16 /* DSP2_DM_1 - [15:0] */
4952 #define WM5100_DSP2_DM_254_MASK 0xFFFF /* DSP2_DM_254 - [15:0] */
4953 #define WM5100_DSP2_DM_254_SHIFT 0 /* DSP2_DM_254 - [15:0] */
4954 #define WM5100_DSP2_DM_254_WIDTH 16 /* DSP2_DM_254 - [15:0] */
4966 #define WM5100_DSP2_DM_END_MASK 0xFFFF /* DSP2_DM_END - [15:0] */
4967 #define WM5100_DSP2_DM_END_SHIFT 0 /* DSP2_DM_END - [15:0] */
4968 #define WM5100_DSP2_DM_END_WIDTH 16 /* DSP2_DM_END - [15:0] */
4980 #define WM5100_DSP2_PM_START_1_MASK 0xFFFF /* DSP2_PM_START - [15:0] */
4981 #define WM5100_DSP2_PM_START_1_SHIFT 0 /* DSP2_PM_START - [15:0] */
4982 #define WM5100_DSP2_PM_START_1_WIDTH 16 /* DSP2_PM_START - [15:0] */
4987 #define WM5100_DSP2_PM_START_MASK 0xFFFF /* DSP2_PM_START - [15:0] */
4988 #define WM5100_DSP2_PM_START_SHIFT 0 /* DSP2_PM_START - [15:0] */
4989 #define WM5100_DSP2_PM_START_WIDTH 16 /* DSP2_PM_START - [15:0] */
5001 #define WM5100_DSP2_PM_1_1_MASK 0xFFFF /* DSP2_PM_1 - [15:0] */
5002 #define WM5100_DSP2_PM_1_1_SHIFT 0 /* DSP2_PM_1 - [15:0] */
5003 #define WM5100_DSP2_PM_1_1_WIDTH 16 /* DSP2_PM_1 - [15:0] */
5008 #define WM5100_DSP2_PM_1_MASK 0xFFFF /* DSP2_PM_1 - [15:0] */
5009 #define WM5100_DSP2_PM_1_SHIFT 0 /* DSP2_PM_1 - [15:0] */
5010 #define WM5100_DSP2_PM_1_WIDTH 16 /* DSP2_PM_1 - [15:0] */
5022 #define WM5100_DSP2_PM_510_1_MASK 0xFFFF /* DSP2_PM_510 - [15:0] */
5023 #define WM5100_DSP2_PM_510_1_SHIFT 0 /* DSP2_PM_510 - [15:0] */
5024 #define WM5100_DSP2_PM_510_1_WIDTH 16 /* DSP2_PM_510 - [15:0] */
5029 #define WM5100_DSP2_PM_510_MASK 0xFFFF /* DSP2_PM_510 - [15:0] */
5030 #define WM5100_DSP2_PM_510_SHIFT 0 /* DSP2_PM_510 - [15:0] */
5031 #define WM5100_DSP2_PM_510_WIDTH 16 /* DSP2_PM_510 - [15:0] */
5043 #define WM5100_DSP2_PM_END_1_MASK 0xFFFF /* DSP2_PM_END - [15:0] */
5044 #define WM5100_DSP2_PM_END_1_SHIFT 0 /* DSP2_PM_END - [15:0] */
5045 #define WM5100_DSP2_PM_END_1_WIDTH 16 /* DSP2_PM_END - [15:0] */
5050 #define WM5100_DSP2_PM_END_MASK 0xFFFF /* DSP2_PM_END - [15:0] */
5051 #define WM5100_DSP2_PM_END_SHIFT 0 /* DSP2_PM_END - [15:0] */
5052 #define WM5100_DSP2_PM_END_WIDTH 16 /* DSP2_PM_END - [15:0] */
5064 #define WM5100_DSP2_ZM_START_MASK 0xFFFF /* DSP2_ZM_START - [15:0] */
5065 #define WM5100_DSP2_ZM_START_SHIFT 0 /* DSP2_ZM_START - [15:0] */
5066 #define WM5100_DSP2_ZM_START_WIDTH 16 /* DSP2_ZM_START - [15:0] */
5078 #define WM5100_DSP2_ZM_1_MASK 0xFFFF /* DSP2_ZM_1 - [15:0] */
5079 #define WM5100_DSP2_ZM_1_SHIFT 0 /* DSP2_ZM_1 - [15:0] */
5080 #define WM5100_DSP2_ZM_1_WIDTH 16 /* DSP2_ZM_1 - [15:0] */
5092 #define WM5100_DSP2_ZM_1022_MASK 0xFFFF /* DSP2_ZM_1022 - [15:0] */
5093 #define WM5100_DSP2_ZM_1022_SHIFT 0 /* DSP2_ZM_1022 - [15:0] */
5094 #define WM5100_DSP2_ZM_1022_WIDTH 16 /* DSP2_ZM_1022 - [15:0] */
5106 #define WM5100_DSP2_ZM_END_MASK 0xFFFF /* DSP2_ZM_END - [15:0] */
5107 #define WM5100_DSP2_ZM_END_SHIFT 0 /* DSP2_ZM_END - [15:0] */
5108 #define WM5100_DSP2_ZM_END_WIDTH 16 /* DSP2_ZM_END - [15:0] */
5120 #define WM5100_DSP3_DM_START_MASK 0xFFFF /* DSP3_DM_START - [15:0] */
5121 #define WM5100_DSP3_DM_START_SHIFT 0 /* DSP3_DM_START - [15:0] */
5122 #define WM5100_DSP3_DM_START_WIDTH 16 /* DSP3_DM_START - [15:0] */
5134 #define WM5100_DSP3_DM_1_MASK 0xFFFF /* DSP3_DM_1 - [15:0] */
5135 #define WM5100_DSP3_DM_1_SHIFT 0 /* DSP3_DM_1 - [15:0] */
5136 #define WM5100_DSP3_DM_1_WIDTH 16 /* DSP3_DM_1 - [15:0] */
5148 #define WM5100_DSP3_DM_254_MASK 0xFFFF /* DSP3_DM_254 - [15:0] */
5149 #define WM5100_DSP3_DM_254_SHIFT 0 /* DSP3_DM_254 - [15:0] */
5150 #define WM5100_DSP3_DM_254_WIDTH 16 /* DSP3_DM_254 - [15:0] */
5162 #define WM5100_DSP3_DM_END_MASK 0xFFFF /* DSP3_DM_END - [15:0] */
5163 #define WM5100_DSP3_DM_END_SHIFT 0 /* DSP3_DM_END - [15:0] */
5164 #define WM5100_DSP3_DM_END_WIDTH 16 /* DSP3_DM_END - [15:0] */
5176 #define WM5100_DSP3_PM_START_1_MASK 0xFFFF /* DSP3_PM_START - [15:0] */
5177 #define WM5100_DSP3_PM_START_1_SHIFT 0 /* DSP3_PM_START - [15:0] */
5178 #define WM5100_DSP3_PM_START_1_WIDTH 16 /* DSP3_PM_START - [15:0] */
5183 #define WM5100_DSP3_PM_START_MASK 0xFFFF /* DSP3_PM_START - [15:0] */
5184 #define WM5100_DSP3_PM_START_SHIFT 0 /* DSP3_PM_START - [15:0] */
5185 #define WM5100_DSP3_PM_START_WIDTH 16 /* DSP3_PM_START - [15:0] */
5197 #define WM5100_DSP3_PM_1_1_MASK 0xFFFF /* DSP3_PM_1 - [15:0] */
5198 #define WM5100_DSP3_PM_1_1_SHIFT 0 /* DSP3_PM_1 - [15:0] */
5199 #define WM5100_DSP3_PM_1_1_WIDTH 16 /* DSP3_PM_1 - [15:0] */
5204 #define WM5100_DSP3_PM_1_MASK 0xFFFF /* DSP3_PM_1 - [15:0] */
5205 #define WM5100_DSP3_PM_1_SHIFT 0 /* DSP3_PM_1 - [15:0] */
5206 #define WM5100_DSP3_PM_1_WIDTH 16 /* DSP3_PM_1 - [15:0] */
5218 #define WM5100_DSP3_PM_510_1_MASK 0xFFFF /* DSP3_PM_510 - [15:0] */
5219 #define WM5100_DSP3_PM_510_1_SHIFT 0 /* DSP3_PM_510 - [15:0] */
5220 #define WM5100_DSP3_PM_510_1_WIDTH 16 /* DSP3_PM_510 - [15:0] */
5225 #define WM5100_DSP3_PM_510_MASK 0xFFFF /* DSP3_PM_510 - [15:0] */
5226 #define WM5100_DSP3_PM_510_SHIFT 0 /* DSP3_PM_510 - [15:0] */
5227 #define WM5100_DSP3_PM_510_WIDTH 16 /* DSP3_PM_510 - [15:0] */
5239 #define WM5100_DSP3_PM_END_1_MASK 0xFFFF /* DSP3_PM_END - [15:0] */
5240 #define WM5100_DSP3_PM_END_1_SHIFT 0 /* DSP3_PM_END - [15:0] */
5241 #define WM5100_DSP3_PM_END_1_WIDTH 16 /* DSP3_PM_END - [15:0] */
5246 #define WM5100_DSP3_PM_END_MASK 0xFFFF /* DSP3_PM_END - [15:0] */
5247 #define WM5100_DSP3_PM_END_SHIFT 0 /* DSP3_PM_END - [15:0] */
5248 #define WM5100_DSP3_PM_END_WIDTH 16 /* DSP3_PM_END - [15:0] */
5260 #define WM5100_DSP3_ZM_START_MASK 0xFFFF /* DSP3_ZM_START - [15:0] */
5261 #define WM5100_DSP3_ZM_START_SHIFT 0 /* DSP3_ZM_START - [15:0] */
5262 #define WM5100_DSP3_ZM_START_WIDTH 16 /* DSP3_ZM_START - [15:0] */
5274 #define WM5100_DSP3_ZM_1_MASK 0xFFFF /* DSP3_ZM_1 - [15:0] */
5275 #define WM5100_DSP3_ZM_1_SHIFT 0 /* DSP3_ZM_1 - [15:0] */
5276 #define WM5100_DSP3_ZM_1_WIDTH 16 /* DSP3_ZM_1 - [15:0] */
5288 #define WM5100_DSP3_ZM_1022_MASK 0xFFFF /* DSP3_ZM_1022 - [15:0] */
5289 #define WM5100_DSP3_ZM_1022_SHIFT 0 /* DSP3_ZM_1022 - [15:0] */
5290 #define WM5100_DSP3_ZM_1022_WIDTH 16 /* DSP3_ZM_1022 - [15:0] */
5302 #define WM5100_DSP3_ZM_END_MASK 0xFFFF /* DSP3_ZM_END - [15:0] */
5303 #define WM5100_DSP3_ZM_END_SHIFT 0 /* DSP3_ZM_END - [15:0] */
5304 #define WM5100_DSP3_ZM_END_WIDTH 16 /* DSP3_ZM_END - [15:0] */