Lines Matching +full:0 +full:x409
14 #define WM2200_CLKSRC_MCLK1 0
19 #define WM2200_FLL_SRC_MCLK1 0
26 #define WM2200_SOFTWARE_RESET 0x00
27 #define WM2200_DEVICE_REVISION 0x01
28 #define WM2200_TONE_GENERATOR_1 0x0B
29 #define WM2200_CLOCKING_3 0x102
30 #define WM2200_CLOCKING_4 0x103
31 #define WM2200_FLL_CONTROL_1 0x111
32 #define WM2200_FLL_CONTROL_2 0x112
33 #define WM2200_FLL_CONTROL_3 0x113
34 #define WM2200_FLL_CONTROL_4 0x114
35 #define WM2200_FLL_CONTROL_6 0x116
36 #define WM2200_FLL_CONTROL_7 0x117
37 #define WM2200_FLL_EFS_1 0x119
38 #define WM2200_FLL_EFS_2 0x11A
39 #define WM2200_MIC_CHARGE_PUMP_1 0x200
40 #define WM2200_MIC_CHARGE_PUMP_2 0x201
41 #define WM2200_DM_CHARGE_PUMP_1 0x202
42 #define WM2200_MIC_BIAS_CTRL_1 0x20C
43 #define WM2200_MIC_BIAS_CTRL_2 0x20D
44 #define WM2200_EAR_PIECE_CTRL_1 0x20F
45 #define WM2200_EAR_PIECE_CTRL_2 0x210
46 #define WM2200_INPUT_ENABLES 0x301
47 #define WM2200_IN1L_CONTROL 0x302
48 #define WM2200_IN1R_CONTROL 0x303
49 #define WM2200_IN2L_CONTROL 0x304
50 #define WM2200_IN2R_CONTROL 0x305
51 #define WM2200_IN3L_CONTROL 0x306
52 #define WM2200_IN3R_CONTROL 0x307
53 #define WM2200_RXANC_SRC 0x30A
54 #define WM2200_INPUT_VOLUME_RAMP 0x30B
55 #define WM2200_ADC_DIGITAL_VOLUME_1L 0x30C
56 #define WM2200_ADC_DIGITAL_VOLUME_1R 0x30D
57 #define WM2200_ADC_DIGITAL_VOLUME_2L 0x30E
58 #define WM2200_ADC_DIGITAL_VOLUME_2R 0x30F
59 #define WM2200_ADC_DIGITAL_VOLUME_3L 0x310
60 #define WM2200_ADC_DIGITAL_VOLUME_3R 0x311
61 #define WM2200_OUTPUT_ENABLES 0x400
62 #define WM2200_DAC_VOLUME_LIMIT_1L 0x401
63 #define WM2200_DAC_VOLUME_LIMIT_1R 0x402
64 #define WM2200_DAC_VOLUME_LIMIT_2L 0x403
65 #define WM2200_DAC_VOLUME_LIMIT_2R 0x404
66 #define WM2200_DAC_AEC_CONTROL_1 0x409
67 #define WM2200_OUTPUT_VOLUME_RAMP 0x40A
68 #define WM2200_DAC_DIGITAL_VOLUME_1L 0x40B
69 #define WM2200_DAC_DIGITAL_VOLUME_1R 0x40C
70 #define WM2200_DAC_DIGITAL_VOLUME_2L 0x40D
71 #define WM2200_DAC_DIGITAL_VOLUME_2R 0x40E
72 #define WM2200_PDM_1 0x417
73 #define WM2200_PDM_2 0x418
74 #define WM2200_AUDIO_IF_1_1 0x500
75 #define WM2200_AUDIO_IF_1_2 0x501
76 #define WM2200_AUDIO_IF_1_3 0x502
77 #define WM2200_AUDIO_IF_1_4 0x503
78 #define WM2200_AUDIO_IF_1_5 0x504
79 #define WM2200_AUDIO_IF_1_6 0x505
80 #define WM2200_AUDIO_IF_1_7 0x506
81 #define WM2200_AUDIO_IF_1_8 0x507
82 #define WM2200_AUDIO_IF_1_9 0x508
83 #define WM2200_AUDIO_IF_1_10 0x509
84 #define WM2200_AUDIO_IF_1_11 0x50A
85 #define WM2200_AUDIO_IF_1_12 0x50B
86 #define WM2200_AUDIO_IF_1_13 0x50C
87 #define WM2200_AUDIO_IF_1_14 0x50D
88 #define WM2200_AUDIO_IF_1_15 0x50E
89 #define WM2200_AUDIO_IF_1_16 0x50F
90 #define WM2200_AUDIO_IF_1_17 0x510
91 #define WM2200_AUDIO_IF_1_18 0x511
92 #define WM2200_AUDIO_IF_1_19 0x512
93 #define WM2200_AUDIO_IF_1_20 0x513
94 #define WM2200_AUDIO_IF_1_21 0x514
95 #define WM2200_AUDIO_IF_1_22 0x515
96 #define WM2200_OUT1LMIX_INPUT_1_SOURCE 0x600
97 #define WM2200_OUT1LMIX_INPUT_1_VOLUME 0x601
98 #define WM2200_OUT1LMIX_INPUT_2_SOURCE 0x602
99 #define WM2200_OUT1LMIX_INPUT_2_VOLUME 0x603
100 #define WM2200_OUT1LMIX_INPUT_3_SOURCE 0x604
101 #define WM2200_OUT1LMIX_INPUT_3_VOLUME 0x605
102 #define WM2200_OUT1LMIX_INPUT_4_SOURCE 0x606
103 #define WM2200_OUT1LMIX_INPUT_4_VOLUME 0x607
104 #define WM2200_OUT1RMIX_INPUT_1_SOURCE 0x608
105 #define WM2200_OUT1RMIX_INPUT_1_VOLUME 0x609
106 #define WM2200_OUT1RMIX_INPUT_2_SOURCE 0x60A
107 #define WM2200_OUT1RMIX_INPUT_2_VOLUME 0x60B
108 #define WM2200_OUT1RMIX_INPUT_3_SOURCE 0x60C
109 #define WM2200_OUT1RMIX_INPUT_3_VOLUME 0x60D
110 #define WM2200_OUT1RMIX_INPUT_4_SOURCE 0x60E
111 #define WM2200_OUT1RMIX_INPUT_4_VOLUME 0x60F
112 #define WM2200_OUT2LMIX_INPUT_1_SOURCE 0x610
113 #define WM2200_OUT2LMIX_INPUT_1_VOLUME 0x611
114 #define WM2200_OUT2LMIX_INPUT_2_SOURCE 0x612
115 #define WM2200_OUT2LMIX_INPUT_2_VOLUME 0x613
116 #define WM2200_OUT2LMIX_INPUT_3_SOURCE 0x614
117 #define WM2200_OUT2LMIX_INPUT_3_VOLUME 0x615
118 #define WM2200_OUT2LMIX_INPUT_4_SOURCE 0x616
119 #define WM2200_OUT2LMIX_INPUT_4_VOLUME 0x617
120 #define WM2200_OUT2RMIX_INPUT_1_SOURCE 0x618
121 #define WM2200_OUT2RMIX_INPUT_1_VOLUME 0x619
122 #define WM2200_OUT2RMIX_INPUT_2_SOURCE 0x61A
123 #define WM2200_OUT2RMIX_INPUT_2_VOLUME 0x61B
124 #define WM2200_OUT2RMIX_INPUT_3_SOURCE 0x61C
125 #define WM2200_OUT2RMIX_INPUT_3_VOLUME 0x61D
126 #define WM2200_OUT2RMIX_INPUT_4_SOURCE 0x61E
127 #define WM2200_OUT2RMIX_INPUT_4_VOLUME 0x61F
128 #define WM2200_AIF1TX1MIX_INPUT_1_SOURCE 0x620
129 #define WM2200_AIF1TX1MIX_INPUT_1_VOLUME 0x621
130 #define WM2200_AIF1TX1MIX_INPUT_2_SOURCE 0x622
131 #define WM2200_AIF1TX1MIX_INPUT_2_VOLUME 0x623
132 #define WM2200_AIF1TX1MIX_INPUT_3_SOURCE 0x624
133 #define WM2200_AIF1TX1MIX_INPUT_3_VOLUME 0x625
134 #define WM2200_AIF1TX1MIX_INPUT_4_SOURCE 0x626
135 #define WM2200_AIF1TX1MIX_INPUT_4_VOLUME 0x627
136 #define WM2200_AIF1TX2MIX_INPUT_1_SOURCE 0x628
137 #define WM2200_AIF1TX2MIX_INPUT_1_VOLUME 0x629
138 #define WM2200_AIF1TX2MIX_INPUT_2_SOURCE 0x62A
139 #define WM2200_AIF1TX2MIX_INPUT_2_VOLUME 0x62B
140 #define WM2200_AIF1TX2MIX_INPUT_3_SOURCE 0x62C
141 #define WM2200_AIF1TX2MIX_INPUT_3_VOLUME 0x62D
142 #define WM2200_AIF1TX2MIX_INPUT_4_SOURCE 0x62E
143 #define WM2200_AIF1TX2MIX_INPUT_4_VOLUME 0x62F
144 #define WM2200_AIF1TX3MIX_INPUT_1_SOURCE 0x630
145 #define WM2200_AIF1TX3MIX_INPUT_1_VOLUME 0x631
146 #define WM2200_AIF1TX3MIX_INPUT_2_SOURCE 0x632
147 #define WM2200_AIF1TX3MIX_INPUT_2_VOLUME 0x633
148 #define WM2200_AIF1TX3MIX_INPUT_3_SOURCE 0x634
149 #define WM2200_AIF1TX3MIX_INPUT_3_VOLUME 0x635
150 #define WM2200_AIF1TX3MIX_INPUT_4_SOURCE 0x636
151 #define WM2200_AIF1TX3MIX_INPUT_4_VOLUME 0x637
152 #define WM2200_AIF1TX4MIX_INPUT_1_SOURCE 0x638
153 #define WM2200_AIF1TX4MIX_INPUT_1_VOLUME 0x639
154 #define WM2200_AIF1TX4MIX_INPUT_2_SOURCE 0x63A
155 #define WM2200_AIF1TX4MIX_INPUT_2_VOLUME 0x63B
156 #define WM2200_AIF1TX4MIX_INPUT_3_SOURCE 0x63C
157 #define WM2200_AIF1TX4MIX_INPUT_3_VOLUME 0x63D
158 #define WM2200_AIF1TX4MIX_INPUT_4_SOURCE 0x63E
159 #define WM2200_AIF1TX4MIX_INPUT_4_VOLUME 0x63F
160 #define WM2200_AIF1TX5MIX_INPUT_1_SOURCE 0x640
161 #define WM2200_AIF1TX5MIX_INPUT_1_VOLUME 0x641
162 #define WM2200_AIF1TX5MIX_INPUT_2_SOURCE 0x642
163 #define WM2200_AIF1TX5MIX_INPUT_2_VOLUME 0x643
164 #define WM2200_AIF1TX5MIX_INPUT_3_SOURCE 0x644
165 #define WM2200_AIF1TX5MIX_INPUT_3_VOLUME 0x645
166 #define WM2200_AIF1TX5MIX_INPUT_4_SOURCE 0x646
167 #define WM2200_AIF1TX5MIX_INPUT_4_VOLUME 0x647
168 #define WM2200_AIF1TX6MIX_INPUT_1_SOURCE 0x648
169 #define WM2200_AIF1TX6MIX_INPUT_1_VOLUME 0x649
170 #define WM2200_AIF1TX6MIX_INPUT_2_SOURCE 0x64A
171 #define WM2200_AIF1TX6MIX_INPUT_2_VOLUME 0x64B
172 #define WM2200_AIF1TX6MIX_INPUT_3_SOURCE 0x64C
173 #define WM2200_AIF1TX6MIX_INPUT_3_VOLUME 0x64D
174 #define WM2200_AIF1TX6MIX_INPUT_4_SOURCE 0x64E
175 #define WM2200_AIF1TX6MIX_INPUT_4_VOLUME 0x64F
176 #define WM2200_EQLMIX_INPUT_1_SOURCE 0x650
177 #define WM2200_EQLMIX_INPUT_1_VOLUME 0x651
178 #define WM2200_EQLMIX_INPUT_2_SOURCE 0x652
179 #define WM2200_EQLMIX_INPUT_2_VOLUME 0x653
180 #define WM2200_EQLMIX_INPUT_3_SOURCE 0x654
181 #define WM2200_EQLMIX_INPUT_3_VOLUME 0x655
182 #define WM2200_EQLMIX_INPUT_4_SOURCE 0x656
183 #define WM2200_EQLMIX_INPUT_4_VOLUME 0x657
184 #define WM2200_EQRMIX_INPUT_1_SOURCE 0x658
185 #define WM2200_EQRMIX_INPUT_1_VOLUME 0x659
186 #define WM2200_EQRMIX_INPUT_2_SOURCE 0x65A
187 #define WM2200_EQRMIX_INPUT_2_VOLUME 0x65B
188 #define WM2200_EQRMIX_INPUT_3_SOURCE 0x65C
189 #define WM2200_EQRMIX_INPUT_3_VOLUME 0x65D
190 #define WM2200_EQRMIX_INPUT_4_SOURCE 0x65E
191 #define WM2200_EQRMIX_INPUT_4_VOLUME 0x65F
192 #define WM2200_LHPF1MIX_INPUT_1_SOURCE 0x660
193 #define WM2200_LHPF1MIX_INPUT_1_VOLUME 0x661
194 #define WM2200_LHPF1MIX_INPUT_2_SOURCE 0x662
195 #define WM2200_LHPF1MIX_INPUT_2_VOLUME 0x663
196 #define WM2200_LHPF1MIX_INPUT_3_SOURCE 0x664
197 #define WM2200_LHPF1MIX_INPUT_3_VOLUME 0x665
198 #define WM2200_LHPF1MIX_INPUT_4_SOURCE 0x666
199 #define WM2200_LHPF1MIX_INPUT_4_VOLUME 0x667
200 #define WM2200_LHPF2MIX_INPUT_1_SOURCE 0x668
201 #define WM2200_LHPF2MIX_INPUT_1_VOLUME 0x669
202 #define WM2200_LHPF2MIX_INPUT_2_SOURCE 0x66A
203 #define WM2200_LHPF2MIX_INPUT_2_VOLUME 0x66B
204 #define WM2200_LHPF2MIX_INPUT_3_SOURCE 0x66C
205 #define WM2200_LHPF2MIX_INPUT_3_VOLUME 0x66D
206 #define WM2200_LHPF2MIX_INPUT_4_SOURCE 0x66E
207 #define WM2200_LHPF2MIX_INPUT_4_VOLUME 0x66F
208 #define WM2200_DSP1LMIX_INPUT_1_SOURCE 0x670
209 #define WM2200_DSP1LMIX_INPUT_1_VOLUME 0x671
210 #define WM2200_DSP1LMIX_INPUT_2_SOURCE 0x672
211 #define WM2200_DSP1LMIX_INPUT_2_VOLUME 0x673
212 #define WM2200_DSP1LMIX_INPUT_3_SOURCE 0x674
213 #define WM2200_DSP1LMIX_INPUT_3_VOLUME 0x675
214 #define WM2200_DSP1LMIX_INPUT_4_SOURCE 0x676
215 #define WM2200_DSP1LMIX_INPUT_4_VOLUME 0x677
216 #define WM2200_DSP1RMIX_INPUT_1_SOURCE 0x678
217 #define WM2200_DSP1RMIX_INPUT_1_VOLUME 0x679
218 #define WM2200_DSP1RMIX_INPUT_2_SOURCE 0x67A
219 #define WM2200_DSP1RMIX_INPUT_2_VOLUME 0x67B
220 #define WM2200_DSP1RMIX_INPUT_3_SOURCE 0x67C
221 #define WM2200_DSP1RMIX_INPUT_3_VOLUME 0x67D
222 #define WM2200_DSP1RMIX_INPUT_4_SOURCE 0x67E
223 #define WM2200_DSP1RMIX_INPUT_4_VOLUME 0x67F
224 #define WM2200_DSP1AUX1MIX_INPUT_1_SOURCE 0x680
225 #define WM2200_DSP1AUX2MIX_INPUT_1_SOURCE 0x681
226 #define WM2200_DSP1AUX3MIX_INPUT_1_SOURCE 0x682
227 #define WM2200_DSP1AUX4MIX_INPUT_1_SOURCE 0x683
228 #define WM2200_DSP1AUX5MIX_INPUT_1_SOURCE 0x684
229 #define WM2200_DSP1AUX6MIX_INPUT_1_SOURCE 0x685
230 #define WM2200_DSP2LMIX_INPUT_1_SOURCE 0x686
231 #define WM2200_DSP2LMIX_INPUT_1_VOLUME 0x687
232 #define WM2200_DSP2LMIX_INPUT_2_SOURCE 0x688
233 #define WM2200_DSP2LMIX_INPUT_2_VOLUME 0x689
234 #define WM2200_DSP2LMIX_INPUT_3_SOURCE 0x68A
235 #define WM2200_DSP2LMIX_INPUT_3_VOLUME 0x68B
236 #define WM2200_DSP2LMIX_INPUT_4_SOURCE 0x68C
237 #define WM2200_DSP2LMIX_INPUT_4_VOLUME 0x68D
238 #define WM2200_DSP2RMIX_INPUT_1_SOURCE 0x68E
239 #define WM2200_DSP2RMIX_INPUT_1_VOLUME 0x68F
240 #define WM2200_DSP2RMIX_INPUT_2_SOURCE 0x690
241 #define WM2200_DSP2RMIX_INPUT_2_VOLUME 0x691
242 #define WM2200_DSP2RMIX_INPUT_3_SOURCE 0x692
243 #define WM2200_DSP2RMIX_INPUT_3_VOLUME 0x693
244 #define WM2200_DSP2RMIX_INPUT_4_SOURCE 0x694
245 #define WM2200_DSP2RMIX_INPUT_4_VOLUME 0x695
246 #define WM2200_DSP2AUX1MIX_INPUT_1_SOURCE 0x696
247 #define WM2200_DSP2AUX2MIX_INPUT_1_SOURCE 0x697
248 #define WM2200_DSP2AUX3MIX_INPUT_1_SOURCE 0x698
249 #define WM2200_DSP2AUX4MIX_INPUT_1_SOURCE 0x699
250 #define WM2200_DSP2AUX5MIX_INPUT_1_SOURCE 0x69A
251 #define WM2200_DSP2AUX6MIX_INPUT_1_SOURCE 0x69B
252 #define WM2200_GPIO_CTRL_1 0x700
253 #define WM2200_GPIO_CTRL_2 0x701
254 #define WM2200_GPIO_CTRL_3 0x702
255 #define WM2200_GPIO_CTRL_4 0x703
256 #define WM2200_ADPS1_IRQ0 0x707
257 #define WM2200_ADPS1_IRQ1 0x708
258 #define WM2200_MISC_PAD_CTRL_1 0x709
259 #define WM2200_INTERRUPT_STATUS_1 0x800
260 #define WM2200_INTERRUPT_STATUS_1_MASK 0x801
261 #define WM2200_INTERRUPT_STATUS_2 0x802
262 #define WM2200_INTERRUPT_RAW_STATUS_2 0x803
263 #define WM2200_INTERRUPT_STATUS_2_MASK 0x804
264 #define WM2200_INTERRUPT_CONTROL 0x808
265 #define WM2200_EQL_1 0x900
266 #define WM2200_EQL_2 0x901
267 #define WM2200_EQL_3 0x902
268 #define WM2200_EQL_4 0x903
269 #define WM2200_EQL_5 0x904
270 #define WM2200_EQL_6 0x905
271 #define WM2200_EQL_7 0x906
272 #define WM2200_EQL_8 0x907
273 #define WM2200_EQL_9 0x908
274 #define WM2200_EQL_10 0x909
275 #define WM2200_EQL_11 0x90A
276 #define WM2200_EQL_12 0x90B
277 #define WM2200_EQL_13 0x90C
278 #define WM2200_EQL_14 0x90D
279 #define WM2200_EQL_15 0x90E
280 #define WM2200_EQL_16 0x90F
281 #define WM2200_EQL_17 0x910
282 #define WM2200_EQL_18 0x911
283 #define WM2200_EQL_19 0x912
284 #define WM2200_EQL_20 0x913
285 #define WM2200_EQR_1 0x916
286 #define WM2200_EQR_2 0x917
287 #define WM2200_EQR_3 0x918
288 #define WM2200_EQR_4 0x919
289 #define WM2200_EQR_5 0x91A
290 #define WM2200_EQR_6 0x91B
291 #define WM2200_EQR_7 0x91C
292 #define WM2200_EQR_8 0x91D
293 #define WM2200_EQR_9 0x91E
294 #define WM2200_EQR_10 0x91F
295 #define WM2200_EQR_11 0x920
296 #define WM2200_EQR_12 0x921
297 #define WM2200_EQR_13 0x922
298 #define WM2200_EQR_14 0x923
299 #define WM2200_EQR_15 0x924
300 #define WM2200_EQR_16 0x925
301 #define WM2200_EQR_17 0x926
302 #define WM2200_EQR_18 0x927
303 #define WM2200_EQR_19 0x928
304 #define WM2200_EQR_20 0x929
305 #define WM2200_HPLPF1_1 0x93E
306 #define WM2200_HPLPF1_2 0x93F
307 #define WM2200_HPLPF2_1 0x942
308 #define WM2200_HPLPF2_2 0x943
309 #define WM2200_DSP1_CONTROL_1 0xA00
310 #define WM2200_DSP1_CONTROL_2 0xA02
311 #define WM2200_DSP1_CONTROL_3 0xA03
312 #define WM2200_DSP1_CONTROL_4 0xA04
313 #define WM2200_DSP1_CONTROL_5 0xA06
314 #define WM2200_DSP1_CONTROL_6 0xA07
315 #define WM2200_DSP1_CONTROL_7 0xA08
316 #define WM2200_DSP1_CONTROL_8 0xA09
317 #define WM2200_DSP1_CONTROL_9 0xA0A
318 #define WM2200_DSP1_CONTROL_10 0xA0B
319 #define WM2200_DSP1_CONTROL_11 0xA0C
320 #define WM2200_DSP1_CONTROL_12 0xA0D
321 #define WM2200_DSP1_CONTROL_13 0xA0F
322 #define WM2200_DSP1_CONTROL_14 0xA10
323 #define WM2200_DSP1_CONTROL_15 0xA11
324 #define WM2200_DSP1_CONTROL_16 0xA12
325 #define WM2200_DSP1_CONTROL_17 0xA13
326 #define WM2200_DSP1_CONTROL_18 0xA14
327 #define WM2200_DSP1_CONTROL_19 0xA16
328 #define WM2200_DSP1_CONTROL_20 0xA17
329 #define WM2200_DSP1_CONTROL_21 0xA18
330 #define WM2200_DSP1_CONTROL_22 0xA1A
331 #define WM2200_DSP1_CONTROL_23 0xA1B
332 #define WM2200_DSP1_CONTROL_24 0xA1C
333 #define WM2200_DSP1_CONTROL_25 0xA1E
334 #define WM2200_DSP1_CONTROL_26 0xA20
335 #define WM2200_DSP1_CONTROL_27 0xA21
336 #define WM2200_DSP1_CONTROL_28 0xA22
337 #define WM2200_DSP1_CONTROL_29 0xA23
338 #define WM2200_DSP1_CONTROL_30 0xA24
339 #define WM2200_DSP1_CONTROL_31 0xA26
340 #define WM2200_DSP2_CONTROL_1 0xB00
341 #define WM2200_DSP2_CONTROL_2 0xB02
342 #define WM2200_DSP2_CONTROL_3 0xB03
343 #define WM2200_DSP2_CONTROL_4 0xB04
344 #define WM2200_DSP2_CONTROL_5 0xB06
345 #define WM2200_DSP2_CONTROL_6 0xB07
346 #define WM2200_DSP2_CONTROL_7 0xB08
347 #define WM2200_DSP2_CONTROL_8 0xB09
348 #define WM2200_DSP2_CONTROL_9 0xB0A
349 #define WM2200_DSP2_CONTROL_10 0xB0B
350 #define WM2200_DSP2_CONTROL_11 0xB0C
351 #define WM2200_DSP2_CONTROL_12 0xB0D
352 #define WM2200_DSP2_CONTROL_13 0xB0F
353 #define WM2200_DSP2_CONTROL_14 0xB10
354 #define WM2200_DSP2_CONTROL_15 0xB11
355 #define WM2200_DSP2_CONTROL_16 0xB12
356 #define WM2200_DSP2_CONTROL_17 0xB13
357 #define WM2200_DSP2_CONTROL_18 0xB14
358 #define WM2200_DSP2_CONTROL_19 0xB16
359 #define WM2200_DSP2_CONTROL_20 0xB17
360 #define WM2200_DSP2_CONTROL_21 0xB18
361 #define WM2200_DSP2_CONTROL_22 0xB1A
362 #define WM2200_DSP2_CONTROL_23 0xB1B
363 #define WM2200_DSP2_CONTROL_24 0xB1C
364 #define WM2200_DSP2_CONTROL_25 0xB1E
365 #define WM2200_DSP2_CONTROL_26 0xB20
366 #define WM2200_DSP2_CONTROL_27 0xB21
367 #define WM2200_DSP2_CONTROL_28 0xB22
368 #define WM2200_DSP2_CONTROL_29 0xB23
369 #define WM2200_DSP2_CONTROL_30 0xB24
370 #define WM2200_DSP2_CONTROL_31 0xB26
371 #define WM2200_ANC_CTRL1 0xD00
372 #define WM2200_ANC_CTRL2 0xD01
373 #define WM2200_ANC_CTRL3 0xD02
374 #define WM2200_ANC_CTRL7 0xD08
375 #define WM2200_ANC_CTRL8 0xD09
376 #define WM2200_ANC_CTRL9 0xD0A
377 #define WM2200_ANC_CTRL10 0xD0B
378 #define WM2200_ANC_CTRL11 0xD0C
379 #define WM2200_ANC_CTRL12 0xD0D
380 #define WM2200_ANC_CTRL13 0xD0E
381 #define WM2200_ANC_CTRL14 0xD0F
382 #define WM2200_ANC_CTRL15 0xD10
383 #define WM2200_ANC_CTRL16 0xD11
384 #define WM2200_ANC_CTRL17 0xD12
385 #define WM2200_ANC_CTRL18 0xD15
386 #define WM2200_ANC_CTRL19 0xD16
387 #define WM2200_ANC_CTRL20 0xD17
388 #define WM2200_ANC_CTRL21 0xD18
389 #define WM2200_ANC_CTRL22 0xD19
390 #define WM2200_ANC_CTRL23 0xD1A
391 #define WM2200_ANC_CTRL24 0xD1B
392 #define WM2200_ANC_CTRL25 0xD1C
393 #define WM2200_ANC_CTRL26 0xD1D
394 #define WM2200_ANC_CTRL27 0xD1E
395 #define WM2200_ANC_CTRL28 0xD1F
396 #define WM2200_ANC_CTRL29 0xD20
397 #define WM2200_ANC_CTRL30 0xD21
398 #define WM2200_ANC_CTRL31 0xD23
399 #define WM2200_ANC_CTRL32 0xD24
400 #define WM2200_ANC_CTRL33 0xD25
401 #define WM2200_ANC_CTRL34 0xD27
402 #define WM2200_ANC_CTRL35 0xD28
403 #define WM2200_ANC_CTRL36 0xD29
404 #define WM2200_ANC_CTRL37 0xD2A
405 #define WM2200_ANC_CTRL38 0xD2B
406 #define WM2200_ANC_CTRL39 0xD2C
407 #define WM2200_ANC_CTRL40 0xD2D
408 #define WM2200_ANC_CTRL41 0xD2E
409 #define WM2200_ANC_CTRL42 0xD2F
410 #define WM2200_ANC_CTRL43 0xD30
411 #define WM2200_ANC_CTRL44 0xD31
412 #define WM2200_ANC_CTRL45 0xD32
413 #define WM2200_ANC_CTRL46 0xD33
414 #define WM2200_ANC_CTRL47 0xD34
415 #define WM2200_ANC_CTRL48 0xD35
416 #define WM2200_ANC_CTRL49 0xD36
417 #define WM2200_ANC_CTRL50 0xD37
418 #define WM2200_ANC_CTRL51 0xD38
419 #define WM2200_ANC_CTRL52 0xD39
420 #define WM2200_ANC_CTRL53 0xD3A
421 #define WM2200_ANC_CTRL54 0xD3B
422 #define WM2200_ANC_CTRL55 0xD3C
423 #define WM2200_ANC_CTRL56 0xD3D
424 #define WM2200_ANC_CTRL57 0xD3E
425 #define WM2200_ANC_CTRL58 0xD3F
426 #define WM2200_ANC_CTRL59 0xD40
427 #define WM2200_ANC_CTRL60 0xD41
428 #define WM2200_ANC_CTRL61 0xD42
429 #define WM2200_ANC_CTRL62 0xD43
430 #define WM2200_ANC_CTRL63 0xD44
431 #define WM2200_ANC_CTRL64 0xD45
432 #define WM2200_ANC_CTRL65 0xD46
433 #define WM2200_ANC_CTRL66 0xD47
434 #define WM2200_ANC_CTRL67 0xD48
435 #define WM2200_ANC_CTRL68 0xD49
436 #define WM2200_ANC_CTRL69 0xD4A
437 #define WM2200_ANC_CTRL70 0xD4B
438 #define WM2200_ANC_CTRL71 0xD4C
439 #define WM2200_ANC_CTRL72 0xD4D
440 #define WM2200_ANC_CTRL73 0xD4E
441 #define WM2200_ANC_CTRL74 0xD4F
442 #define WM2200_ANC_CTRL75 0xD50
443 #define WM2200_ANC_CTRL76 0xD51
444 #define WM2200_ANC_CTRL77 0xD52
445 #define WM2200_ANC_CTRL78 0xD53
446 #define WM2200_ANC_CTRL79 0xD54
447 #define WM2200_ANC_CTRL80 0xD55
448 #define WM2200_ANC_CTRL81 0xD56
449 #define WM2200_ANC_CTRL82 0xD57
450 #define WM2200_ANC_CTRL83 0xD58
451 #define WM2200_ANC_CTRL84 0xD5B
452 #define WM2200_ANC_CTRL85 0xD5C
453 #define WM2200_ANC_CTRL86 0xD5F
454 #define WM2200_ANC_CTRL87 0xD60
455 #define WM2200_ANC_CTRL88 0xD61
456 #define WM2200_ANC_CTRL89 0xD62
457 #define WM2200_ANC_CTRL90 0xD63
458 #define WM2200_ANC_CTRL91 0xD64
459 #define WM2200_ANC_CTRL92 0xD65
460 #define WM2200_ANC_CTRL93 0xD66
461 #define WM2200_ANC_CTRL94 0xD67
462 #define WM2200_ANC_CTRL95 0xD68
463 #define WM2200_ANC_CTRL96 0xD69
464 #define WM2200_DSP1_DM_0 0x3000
465 #define WM2200_DSP1_DM_1 0x3001
466 #define WM2200_DSP1_DM_2 0x3002
467 #define WM2200_DSP1_DM_3 0x3003
468 #define WM2200_DSP1_DM_2044 0x37FC
469 #define WM2200_DSP1_DM_2045 0x37FD
470 #define WM2200_DSP1_DM_2046 0x37FE
471 #define WM2200_DSP1_DM_2047 0x37FF
472 #define WM2200_DSP1_PM_0 0x3800
473 #define WM2200_DSP1_PM_1 0x3801
474 #define WM2200_DSP1_PM_2 0x3802
475 #define WM2200_DSP1_PM_3 0x3803
476 #define WM2200_DSP1_PM_4 0x3804
477 #define WM2200_DSP1_PM_5 0x3805
478 #define WM2200_DSP1_PM_762 0x3AFA
479 #define WM2200_DSP1_PM_763 0x3AFB
480 #define WM2200_DSP1_PM_764 0x3AFC
481 #define WM2200_DSP1_PM_765 0x3AFD
482 #define WM2200_DSP1_PM_766 0x3AFE
483 #define WM2200_DSP1_PM_767 0x3AFF
484 #define WM2200_DSP1_ZM_0 0x3C00
485 #define WM2200_DSP1_ZM_1 0x3C01
486 #define WM2200_DSP1_ZM_2 0x3C02
487 #define WM2200_DSP1_ZM_3 0x3C03
488 #define WM2200_DSP1_ZM_1020 0x3FFC
489 #define WM2200_DSP1_ZM_1021 0x3FFD
490 #define WM2200_DSP1_ZM_1022 0x3FFE
491 #define WM2200_DSP1_ZM_1023 0x3FFF
492 #define WM2200_DSP2_DM_0 0x4000
493 #define WM2200_DSP2_DM_1 0x4001
494 #define WM2200_DSP2_DM_2 0x4002
495 #define WM2200_DSP2_DM_3 0x4003
496 #define WM2200_DSP2_DM_2044 0x47FC
497 #define WM2200_DSP2_DM_2045 0x47FD
498 #define WM2200_DSP2_DM_2046 0x47FE
499 #define WM2200_DSP2_DM_2047 0x47FF
500 #define WM2200_DSP2_PM_0 0x4800
501 #define WM2200_DSP2_PM_1 0x4801
502 #define WM2200_DSP2_PM_2 0x4802
503 #define WM2200_DSP2_PM_3 0x4803
504 #define WM2200_DSP2_PM_4 0x4804
505 #define WM2200_DSP2_PM_5 0x4805
506 #define WM2200_DSP2_PM_762 0x4AFA
507 #define WM2200_DSP2_PM_763 0x4AFB
508 #define WM2200_DSP2_PM_764 0x4AFC
509 #define WM2200_DSP2_PM_765 0x4AFD
510 #define WM2200_DSP2_PM_766 0x4AFE
511 #define WM2200_DSP2_PM_767 0x4AFF
512 #define WM2200_DSP2_ZM_0 0x4C00
513 #define WM2200_DSP2_ZM_1 0x4C01
514 #define WM2200_DSP2_ZM_2 0x4C02
515 #define WM2200_DSP2_ZM_3 0x4C03
516 #define WM2200_DSP2_ZM_1020 0x4FFC
517 #define WM2200_DSP2_ZM_1021 0x4FFD
518 #define WM2200_DSP2_ZM_1022 0x4FFE
519 #define WM2200_DSP2_ZM_1023 0x4FFF
522 #define WM2200_MAX_REGISTER 0x4FFF
529 * R0 (0x00) - software reset
531 #define WM2200_SW_RESET_CHIP_ID1_MASK 0xFFFF /* SW_RESET_CHIP_ID1 - [15:0] */
532 #define WM2200_SW_RESET_CHIP_ID1_SHIFT 0 /* SW_RESET_CHIP_ID1 - [15:0] */
533 #define WM2200_SW_RESET_CHIP_ID1_WIDTH 16 /* SW_RESET_CHIP_ID1 - [15:0] */
536 * R1 (0x01) - Device Revision
538 #define WM2200_DEVICE_REVISION_MASK 0x000F /* DEVICE_REVISION - [3:0] */
539 #define WM2200_DEVICE_REVISION_SHIFT 0 /* DEVICE_REVISION - [3:0] */
540 #define WM2200_DEVICE_REVISION_WIDTH 4 /* DEVICE_REVISION - [3:0] */
543 * R11 (0x0B) - Tone Generator 1
545 #define WM2200_TONE_ENA 0x0001 /* TONE_ENA */
546 #define WM2200_TONE_ENA_MASK 0x0001 /* TONE_ENA */
547 #define WM2200_TONE_ENA_SHIFT 0 /* TONE_ENA */
551 * R258 (0x102) - Clocking 3
553 #define WM2200_SYSCLK_FREQ_MASK 0x0700 /* SYSCLK_FREQ - [10:8] */
556 #define WM2200_SYSCLK_ENA 0x0040 /* SYSCLK_ENA */
557 #define WM2200_SYSCLK_ENA_MASK 0x0040 /* SYSCLK_ENA */
560 #define WM2200_SYSCLK_SRC_MASK 0x000F /* SYSCLK_SRC - [3:0] */
561 #define WM2200_SYSCLK_SRC_SHIFT 0 /* SYSCLK_SRC - [3:0] */
562 #define WM2200_SYSCLK_SRC_WIDTH 4 /* SYSCLK_SRC - [3:0] */
565 * R259 (0x103) - Clocking 4
567 #define WM2200_SAMPLE_RATE_1_MASK 0x001F /* SAMPLE_RATE_1 - [4:0] */
568 #define WM2200_SAMPLE_RATE_1_SHIFT 0 /* SAMPLE_RATE_1 - [4:0] */
569 #define WM2200_SAMPLE_RATE_1_WIDTH 5 /* SAMPLE_RATE_1 - [4:0] */
572 * R273 (0x111) - FLL Control 1
574 #define WM2200_FLL_ENA 0x0001 /* FLL_ENA */
575 #define WM2200_FLL_ENA_MASK 0x0001 /* FLL_ENA */
576 #define WM2200_FLL_ENA_SHIFT 0 /* FLL_ENA */
580 * R274 (0x112) - FLL Control 2
582 #define WM2200_FLL_OUTDIV_MASK 0x3F00 /* FLL_OUTDIV - [13:8] */
585 #define WM2200_FLL_FRATIO_MASK 0x0007 /* FLL_FRATIO - [2:0] */
586 #define WM2200_FLL_FRATIO_SHIFT 0 /* FLL_FRATIO - [2:0] */
587 #define WM2200_FLL_FRATIO_WIDTH 3 /* FLL_FRATIO - [2:0] */
590 * R275 (0x113) - FLL Control 3
592 #define WM2200_FLL_FRACN_ENA 0x0001 /* FLL_FRACN_ENA */
593 #define WM2200_FLL_FRACN_ENA_MASK 0x0001 /* FLL_FRACN_ENA */
594 #define WM2200_FLL_FRACN_ENA_SHIFT 0 /* FLL_FRACN_ENA */
598 * R276 (0x114) - FLL Control 4
600 #define WM2200_FLL_THETA_MASK 0xFFFF /* FLL_THETA - [15:0] */
601 #define WM2200_FLL_THETA_SHIFT 0 /* FLL_THETA - [15:0] */
602 #define WM2200_FLL_THETA_WIDTH 16 /* FLL_THETA - [15:0] */
605 * R278 (0x116) - FLL Control 6
607 #define WM2200_FLL_N_MASK 0x03FF /* FLL_N - [9:0] */
608 #define WM2200_FLL_N_SHIFT 0 /* FLL_N - [9:0] */
609 #define WM2200_FLL_N_WIDTH 10 /* FLL_N - [9:0] */
612 * R279 (0x117) - FLL Control 7
614 #define WM2200_FLL_CLK_REF_DIV_MASK 0x0030 /* FLL_CLK_REF_DIV - [5:4] */
617 #define WM2200_FLL_CLK_REF_SRC_MASK 0x0003 /* FLL_CLK_REF_SRC - [1:0] */
618 #define WM2200_FLL_CLK_REF_SRC_SHIFT 0 /* FLL_CLK_REF_SRC - [1:0] */
619 #define WM2200_FLL_CLK_REF_SRC_WIDTH 2 /* FLL_CLK_REF_SRC - [1:0] */
622 * R281 (0x119) - FLL EFS 1
624 #define WM2200_FLL_LAMBDA_MASK 0xFFFF /* FLL_LAMBDA - [15:0] */
625 #define WM2200_FLL_LAMBDA_SHIFT 0 /* FLL_LAMBDA - [15:0] */
626 #define WM2200_FLL_LAMBDA_WIDTH 16 /* FLL_LAMBDA - [15:0] */
629 * R282 (0x11A) - FLL EFS 2
631 #define WM2200_FLL_EFS_ENA 0x0001 /* FLL_EFS_ENA */
632 #define WM2200_FLL_EFS_ENA_MASK 0x0001 /* FLL_EFS_ENA */
633 #define WM2200_FLL_EFS_ENA_SHIFT 0 /* FLL_EFS_ENA */
637 * R512 (0x200) - Mic Charge Pump 1
639 #define WM2200_CPMIC_BYPASS_MODE 0x0020 /* CPMIC_BYPASS_MODE */
640 #define WM2200_CPMIC_BYPASS_MODE_MASK 0x0020 /* CPMIC_BYPASS_MODE */
643 #define WM2200_CPMIC_ENA 0x0001 /* CPMIC_ENA */
644 #define WM2200_CPMIC_ENA_MASK 0x0001 /* CPMIC_ENA */
645 #define WM2200_CPMIC_ENA_SHIFT 0 /* CPMIC_ENA */
649 * R513 (0x201) - Mic Charge Pump 2
651 #define WM2200_CPMIC_LDO_VSEL_OVERRIDE_MASK 0xF800 /* CPMIC_LDO_VSEL_OVERRIDE - [15:11] */
656 * R514 (0x202) - DM Charge Pump 1
658 #define WM2200_CPDM_ENA 0x0001 /* CPDM_ENA */
659 #define WM2200_CPDM_ENA_MASK 0x0001 /* CPDM_ENA */
660 #define WM2200_CPDM_ENA_SHIFT 0 /* CPDM_ENA */
664 * R524 (0x20C) - Mic Bias Ctrl 1
666 #define WM2200_MICB1_DISCH 0x0040 /* MICB1_DISCH */
667 #define WM2200_MICB1_DISCH_MASK 0x0040 /* MICB1_DISCH */
670 #define WM2200_MICB1_RATE 0x0020 /* MICB1_RATE */
671 #define WM2200_MICB1_RATE_MASK 0x0020 /* MICB1_RATE */
674 #define WM2200_MICB1_LVL_MASK 0x001C /* MICB1_LVL - [4:2] */
677 #define WM2200_MICB1_MODE 0x0002 /* MICB1_MODE */
678 #define WM2200_MICB1_MODE_MASK 0x0002 /* MICB1_MODE */
681 #define WM2200_MICB1_ENA 0x0001 /* MICB1_ENA */
682 #define WM2200_MICB1_ENA_MASK 0x0001 /* MICB1_ENA */
683 #define WM2200_MICB1_ENA_SHIFT 0 /* MICB1_ENA */
687 * R525 (0x20D) - Mic Bias Ctrl 2
689 #define WM2200_MICB2_DISCH 0x0040 /* MICB2_DISCH */
690 #define WM2200_MICB2_DISCH_MASK 0x0040 /* MICB2_DISCH */
693 #define WM2200_MICB2_RATE 0x0020 /* MICB2_RATE */
694 #define WM2200_MICB2_RATE_MASK 0x0020 /* MICB2_RATE */
697 #define WM2200_MICB2_LVL_MASK 0x001C /* MICB2_LVL - [4:2] */
700 #define WM2200_MICB2_MODE 0x0002 /* MICB2_MODE */
701 #define WM2200_MICB2_MODE_MASK 0x0002 /* MICB2_MODE */
704 #define WM2200_MICB2_ENA 0x0001 /* MICB2_ENA */
705 #define WM2200_MICB2_ENA_MASK 0x0001 /* MICB2_ENA */
706 #define WM2200_MICB2_ENA_SHIFT 0 /* MICB2_ENA */
710 * R527 (0x20F) - Ear Piece Ctrl 1
712 #define WM2200_EPD_LP_ENA 0x4000 /* EPD_LP_ENA */
713 #define WM2200_EPD_LP_ENA_MASK 0x4000 /* EPD_LP_ENA */
716 #define WM2200_EPD_OUTP_LP_ENA 0x2000 /* EPD_OUTP_LP_ENA */
717 #define WM2200_EPD_OUTP_LP_ENA_MASK 0x2000 /* EPD_OUTP_LP_ENA */
720 #define WM2200_EPD_RMV_SHRT_LP 0x1000 /* EPD_RMV_SHRT_LP */
721 #define WM2200_EPD_RMV_SHRT_LP_MASK 0x1000 /* EPD_RMV_SHRT_LP */
724 #define WM2200_EPD_LN_ENA 0x0800 /* EPD_LN_ENA */
725 #define WM2200_EPD_LN_ENA_MASK 0x0800 /* EPD_LN_ENA */
728 #define WM2200_EPD_OUTP_LN_ENA 0x0400 /* EPD_OUTP_LN_ENA */
729 #define WM2200_EPD_OUTP_LN_ENA_MASK 0x0400 /* EPD_OUTP_LN_ENA */
732 #define WM2200_EPD_RMV_SHRT_LN 0x0200 /* EPD_RMV_SHRT_LN */
733 #define WM2200_EPD_RMV_SHRT_LN_MASK 0x0200 /* EPD_RMV_SHRT_LN */
738 * R528 (0x210) - Ear Piece Ctrl 2
740 #define WM2200_EPD_RP_ENA 0x4000 /* EPD_RP_ENA */
741 #define WM2200_EPD_RP_ENA_MASK 0x4000 /* EPD_RP_ENA */
744 #define WM2200_EPD_OUTP_RP_ENA 0x2000 /* EPD_OUTP_RP_ENA */
745 #define WM2200_EPD_OUTP_RP_ENA_MASK 0x2000 /* EPD_OUTP_RP_ENA */
748 #define WM2200_EPD_RMV_SHRT_RP 0x1000 /* EPD_RMV_SHRT_RP */
749 #define WM2200_EPD_RMV_SHRT_RP_MASK 0x1000 /* EPD_RMV_SHRT_RP */
752 #define WM2200_EPD_RN_ENA 0x0800 /* EPD_RN_ENA */
753 #define WM2200_EPD_RN_ENA_MASK 0x0800 /* EPD_RN_ENA */
756 #define WM2200_EPD_OUTP_RN_ENA 0x0400 /* EPD_OUTP_RN_ENA */
757 #define WM2200_EPD_OUTP_RN_ENA_MASK 0x0400 /* EPD_OUTP_RN_ENA */
760 #define WM2200_EPD_RMV_SHRT_RN 0x0200 /* EPD_RMV_SHRT_RN */
761 #define WM2200_EPD_RMV_SHRT_RN_MASK 0x0200 /* EPD_RMV_SHRT_RN */
766 * R769 (0x301) - Input Enables
768 #define WM2200_IN3L_ENA 0x0020 /* IN3L_ENA */
769 #define WM2200_IN3L_ENA_MASK 0x0020 /* IN3L_ENA */
772 #define WM2200_IN3R_ENA 0x0010 /* IN3R_ENA */
773 #define WM2200_IN3R_ENA_MASK 0x0010 /* IN3R_ENA */
776 #define WM2200_IN2L_ENA 0x0008 /* IN2L_ENA */
777 #define WM2200_IN2L_ENA_MASK 0x0008 /* IN2L_ENA */
780 #define WM2200_IN2R_ENA 0x0004 /* IN2R_ENA */
781 #define WM2200_IN2R_ENA_MASK 0x0004 /* IN2R_ENA */
784 #define WM2200_IN1L_ENA 0x0002 /* IN1L_ENA */
785 #define WM2200_IN1L_ENA_MASK 0x0002 /* IN1L_ENA */
788 #define WM2200_IN1R_ENA 0x0001 /* IN1R_ENA */
789 #define WM2200_IN1R_ENA_MASK 0x0001 /* IN1R_ENA */
790 #define WM2200_IN1R_ENA_SHIFT 0 /* IN1R_ENA */
794 * R770 (0x302) - IN1L Control
796 #define WM2200_IN1_OSR 0x2000 /* IN1_OSR */
797 #define WM2200_IN1_OSR_MASK 0x2000 /* IN1_OSR */
800 #define WM2200_IN1_DMIC_SUP_MASK 0x1800 /* IN1_DMIC_SUP - [12:11] */
803 #define WM2200_IN1_MODE_MASK 0x0600 /* IN1_MODE - [10:9] */
806 #define WM2200_IN1L_PGA_VOL_MASK 0x00FE /* IN1L_PGA_VOL - [7:1] */
811 * R771 (0x303) - IN1R Control
813 #define WM2200_IN1R_PGA_VOL_MASK 0x00FE /* IN1R_PGA_VOL - [7:1] */
818 * R772 (0x304) - IN2L Control
820 #define WM2200_IN2_OSR 0x2000 /* IN2_OSR */
821 #define WM2200_IN2_OSR_MASK 0x2000 /* IN2_OSR */
824 #define WM2200_IN2_DMIC_SUP_MASK 0x1800 /* IN2_DMIC_SUP - [12:11] */
827 #define WM2200_IN2_MODE_MASK 0x0600 /* IN2_MODE - [10:9] */
830 #define WM2200_IN2L_PGA_VOL_MASK 0x00FE /* IN2L_PGA_VOL - [7:1] */
835 * R773 (0x305) - IN2R Control
837 #define WM2200_IN2R_PGA_VOL_MASK 0x00FE /* IN2R_PGA_VOL - [7:1] */
842 * R774 (0x306) - IN3L Control
844 #define WM2200_IN3_OSR 0x2000 /* IN3_OSR */
845 #define WM2200_IN3_OSR_MASK 0x2000 /* IN3_OSR */
848 #define WM2200_IN3_DMIC_SUP_MASK 0x1800 /* IN3_DMIC_SUP - [12:11] */
851 #define WM2200_IN3_MODE_MASK 0x0600 /* IN3_MODE - [10:9] */
854 #define WM2200_IN3L_PGA_VOL_MASK 0x00FE /* IN3L_PGA_VOL - [7:1] */
859 * R775 (0x307) - IN3R Control
861 #define WM2200_IN3R_PGA_VOL_MASK 0x00FE /* IN3R_PGA_VOL - [7:1] */
866 * R778 (0x30A) - RXANC_SRC
868 #define WM2200_IN_RXANC_SEL_MASK 0x0007 /* IN_RXANC_SEL - [2:0] */
869 #define WM2200_IN_RXANC_SEL_SHIFT 0 /* IN_RXANC_SEL - [2:0] */
870 #define WM2200_IN_RXANC_SEL_WIDTH 3 /* IN_RXANC_SEL - [2:0] */
873 * R779 (0x30B) - Input Volume Ramp
875 #define WM2200_IN_VD_RAMP_MASK 0x0070 /* IN_VD_RAMP - [6:4] */
878 #define WM2200_IN_VI_RAMP_MASK 0x0007 /* IN_VI_RAMP - [2:0] */
879 #define WM2200_IN_VI_RAMP_SHIFT 0 /* IN_VI_RAMP - [2:0] */
880 #define WM2200_IN_VI_RAMP_WIDTH 3 /* IN_VI_RAMP - [2:0] */
883 * R780 (0x30C) - ADC Digital Volume 1L
885 #define WM2200_IN_VU 0x0200 /* IN_VU */
886 #define WM2200_IN_VU_MASK 0x0200 /* IN_VU */
889 #define WM2200_IN1L_MUTE 0x0100 /* IN1L_MUTE */
890 #define WM2200_IN1L_MUTE_MASK 0x0100 /* IN1L_MUTE */
893 #define WM2200_IN1L_DIG_VOL_MASK 0x00FF /* IN1L_DIG_VOL - [7:0] */
894 #define WM2200_IN1L_DIG_VOL_SHIFT 0 /* IN1L_DIG_VOL - [7:0] */
895 #define WM2200_IN1L_DIG_VOL_WIDTH 8 /* IN1L_DIG_VOL - [7:0] */
898 * R781 (0x30D) - ADC Digital Volume 1R
900 #define WM2200_IN_VU 0x0200 /* IN_VU */
901 #define WM2200_IN_VU_MASK 0x0200 /* IN_VU */
904 #define WM2200_IN1R_MUTE 0x0100 /* IN1R_MUTE */
905 #define WM2200_IN1R_MUTE_MASK 0x0100 /* IN1R_MUTE */
908 #define WM2200_IN1R_DIG_VOL_MASK 0x00FF /* IN1R_DIG_VOL - [7:0] */
909 #define WM2200_IN1R_DIG_VOL_SHIFT 0 /* IN1R_DIG_VOL - [7:0] */
910 #define WM2200_IN1R_DIG_VOL_WIDTH 8 /* IN1R_DIG_VOL - [7:0] */
913 * R782 (0x30E) - ADC Digital Volume 2L
915 #define WM2200_IN_VU 0x0200 /* IN_VU */
916 #define WM2200_IN_VU_MASK 0x0200 /* IN_VU */
919 #define WM2200_IN2L_MUTE 0x0100 /* IN2L_MUTE */
920 #define WM2200_IN2L_MUTE_MASK 0x0100 /* IN2L_MUTE */
923 #define WM2200_IN2L_DIG_VOL_MASK 0x00FF /* IN2L_DIG_VOL - [7:0] */
924 #define WM2200_IN2L_DIG_VOL_SHIFT 0 /* IN2L_DIG_VOL - [7:0] */
925 #define WM2200_IN2L_DIG_VOL_WIDTH 8 /* IN2L_DIG_VOL - [7:0] */
928 * R783 (0x30F) - ADC Digital Volume 2R
930 #define WM2200_IN_VU 0x0200 /* IN_VU */
931 #define WM2200_IN_VU_MASK 0x0200 /* IN_VU */
934 #define WM2200_IN2R_MUTE 0x0100 /* IN2R_MUTE */
935 #define WM2200_IN2R_MUTE_MASK 0x0100 /* IN2R_MUTE */
938 #define WM2200_IN2R_DIG_VOL_MASK 0x00FF /* IN2R_DIG_VOL - [7:0] */
939 #define WM2200_IN2R_DIG_VOL_SHIFT 0 /* IN2R_DIG_VOL - [7:0] */
940 #define WM2200_IN2R_DIG_VOL_WIDTH 8 /* IN2R_DIG_VOL - [7:0] */
943 * R784 (0x310) - ADC Digital Volume 3L
945 #define WM2200_IN_VU 0x0200 /* IN_VU */
946 #define WM2200_IN_VU_MASK 0x0200 /* IN_VU */
949 #define WM2200_IN3L_MUTE 0x0100 /* IN3L_MUTE */
950 #define WM2200_IN3L_MUTE_MASK 0x0100 /* IN3L_MUTE */
953 #define WM2200_IN3L_DIG_VOL_MASK 0x00FF /* IN3L_DIG_VOL - [7:0] */
954 #define WM2200_IN3L_DIG_VOL_SHIFT 0 /* IN3L_DIG_VOL - [7:0] */
955 #define WM2200_IN3L_DIG_VOL_WIDTH 8 /* IN3L_DIG_VOL - [7:0] */
958 * R785 (0x311) - ADC Digital Volume 3R
960 #define WM2200_IN_VU 0x0200 /* IN_VU */
961 #define WM2200_IN_VU_MASK 0x0200 /* IN_VU */
964 #define WM2200_IN3R_MUTE 0x0100 /* IN3R_MUTE */
965 #define WM2200_IN3R_MUTE_MASK 0x0100 /* IN3R_MUTE */
968 #define WM2200_IN3R_DIG_VOL_MASK 0x00FF /* IN3R_DIG_VOL - [7:0] */
969 #define WM2200_IN3R_DIG_VOL_SHIFT 0 /* IN3R_DIG_VOL - [7:0] */
970 #define WM2200_IN3R_DIG_VOL_WIDTH 8 /* IN3R_DIG_VOL - [7:0] */
973 * R1024 (0x400) - Output Enables
975 #define WM2200_OUT2L_ENA 0x0008 /* OUT2L_ENA */
976 #define WM2200_OUT2L_ENA_MASK 0x0008 /* OUT2L_ENA */
979 #define WM2200_OUT2R_ENA 0x0004 /* OUT2R_ENA */
980 #define WM2200_OUT2R_ENA_MASK 0x0004 /* OUT2R_ENA */
983 #define WM2200_OUT1L_ENA 0x0002 /* OUT1L_ENA */
984 #define WM2200_OUT1L_ENA_MASK 0x0002 /* OUT1L_ENA */
987 #define WM2200_OUT1R_ENA 0x0001 /* OUT1R_ENA */
988 #define WM2200_OUT1R_ENA_MASK 0x0001 /* OUT1R_ENA */
989 #define WM2200_OUT1R_ENA_SHIFT 0 /* OUT1R_ENA */
993 * R1025 (0x401) - DAC Volume Limit 1L
995 #define WM2200_OUT1_OSR 0x2000 /* OUT1_OSR */
996 #define WM2200_OUT1_OSR_MASK 0x2000 /* OUT1_OSR */
999 #define WM2200_OUT1L_ANC_SRC 0x0800 /* OUT1L_ANC_SRC */
1000 #define WM2200_OUT1L_ANC_SRC_MASK 0x0800 /* OUT1L_ANC_SRC */
1003 #define WM2200_OUT1L_PGA_VOL_MASK 0x00FE /* OUT1L_PGA_VOL - [7:1] */
1008 * R1026 (0x402) - DAC Volume Limit 1R
1010 #define WM2200_OUT1R_ANC_SRC 0x0800 /* OUT1R_ANC_SRC */
1011 #define WM2200_OUT1R_ANC_SRC_MASK 0x0800 /* OUT1R_ANC_SRC */
1014 #define WM2200_OUT1R_PGA_VOL_MASK 0x00FE /* OUT1R_PGA_VOL - [7:1] */
1019 * R1027 (0x403) - DAC Volume Limit 2L
1021 #define WM2200_OUT2_OSR 0x2000 /* OUT2_OSR */
1022 #define WM2200_OUT2_OSR_MASK 0x2000 /* OUT2_OSR */
1025 #define WM2200_OUT2L_ANC_SRC 0x0800 /* OUT2L_ANC_SRC */
1026 #define WM2200_OUT2L_ANC_SRC_MASK 0x0800 /* OUT2L_ANC_SRC */
1031 * R1028 (0x404) - DAC Volume Limit 2R
1033 #define WM2200_OUT2R_ANC_SRC 0x0800 /* OUT2R_ANC_SRC */
1034 #define WM2200_OUT2R_ANC_SRC_MASK 0x0800 /* OUT2R_ANC_SRC */
1039 * R1033 (0x409) - DAC AEC Control 1
1041 #define WM2200_AEC_LOOPBACK_ENA 0x0004 /* AEC_LOOPBACK_ENA */
1042 #define WM2200_AEC_LOOPBACK_ENA_MASK 0x0004 /* AEC_LOOPBACK_ENA */
1045 #define WM2200_AEC_LOOPBACK_SRC_MASK 0x0003 /* AEC_LOOPBACK_SRC - [1:0] */
1046 #define WM2200_AEC_LOOPBACK_SRC_SHIFT 0 /* AEC_LOOPBACK_SRC - [1:0] */
1047 #define WM2200_AEC_LOOPBACK_SRC_WIDTH 2 /* AEC_LOOPBACK_SRC - [1:0] */
1050 * R1034 (0x40A) - Output Volume Ramp
1052 #define WM2200_OUT_VD_RAMP_MASK 0x0070 /* OUT_VD_RAMP - [6:4] */
1055 #define WM2200_OUT_VI_RAMP_MASK 0x0007 /* OUT_VI_RAMP - [2:0] */
1056 #define WM2200_OUT_VI_RAMP_SHIFT 0 /* OUT_VI_RAMP - [2:0] */
1057 #define WM2200_OUT_VI_RAMP_WIDTH 3 /* OUT_VI_RAMP - [2:0] */
1060 * R1035 (0x40B) - DAC Digital Volume 1L
1062 #define WM2200_OUT_VU 0x0200 /* OUT_VU */
1063 #define WM2200_OUT_VU_MASK 0x0200 /* OUT_VU */
1066 #define WM2200_OUT1L_MUTE 0x0100 /* OUT1L_MUTE */
1067 #define WM2200_OUT1L_MUTE_MASK 0x0100 /* OUT1L_MUTE */
1070 #define WM2200_OUT1L_VOL_MASK 0x00FF /* OUT1L_VOL - [7:0] */
1071 #define WM2200_OUT1L_VOL_SHIFT 0 /* OUT1L_VOL - [7:0] */
1072 #define WM2200_OUT1L_VOL_WIDTH 8 /* OUT1L_VOL - [7:0] */
1075 * R1036 (0x40C) - DAC Digital Volume 1R
1077 #define WM2200_OUT_VU 0x0200 /* OUT_VU */
1078 #define WM2200_OUT_VU_MASK 0x0200 /* OUT_VU */
1081 #define WM2200_OUT1R_MUTE 0x0100 /* OUT1R_MUTE */
1082 #define WM2200_OUT1R_MUTE_MASK 0x0100 /* OUT1R_MUTE */
1085 #define WM2200_OUT1R_VOL_MASK 0x00FF /* OUT1R_VOL - [7:0] */
1086 #define WM2200_OUT1R_VOL_SHIFT 0 /* OUT1R_VOL - [7:0] */
1087 #define WM2200_OUT1R_VOL_WIDTH 8 /* OUT1R_VOL - [7:0] */
1090 * R1037 (0x40D) - DAC Digital Volume 2L
1092 #define WM2200_OUT_VU 0x0200 /* OUT_VU */
1093 #define WM2200_OUT_VU_MASK 0x0200 /* OUT_VU */
1096 #define WM2200_OUT2L_MUTE 0x0100 /* OUT2L_MUTE */
1097 #define WM2200_OUT2L_MUTE_MASK 0x0100 /* OUT2L_MUTE */
1100 #define WM2200_OUT2L_VOL_MASK 0x00FF /* OUT2L_VOL - [7:0] */
1101 #define WM2200_OUT2L_VOL_SHIFT 0 /* OUT2L_VOL - [7:0] */
1102 #define WM2200_OUT2L_VOL_WIDTH 8 /* OUT2L_VOL - [7:0] */
1105 * R1038 (0x40E) - DAC Digital Volume 2R
1107 #define WM2200_OUT_VU 0x0200 /* OUT_VU */
1108 #define WM2200_OUT_VU_MASK 0x0200 /* OUT_VU */
1111 #define WM2200_OUT2R_MUTE 0x0100 /* OUT2R_MUTE */
1112 #define WM2200_OUT2R_MUTE_MASK 0x0100 /* OUT2R_MUTE */
1115 #define WM2200_OUT2R_VOL_MASK 0x00FF /* OUT2R_VOL - [7:0] */
1116 #define WM2200_OUT2R_VOL_SHIFT 0 /* OUT2R_VOL - [7:0] */
1117 #define WM2200_OUT2R_VOL_WIDTH 8 /* OUT2R_VOL - [7:0] */
1120 * R1047 (0x417) - PDM 1
1122 #define WM2200_SPK1R_MUTE 0x2000 /* SPK1R_MUTE */
1123 #define WM2200_SPK1R_MUTE_MASK 0x2000 /* SPK1R_MUTE */
1126 #define WM2200_SPK1L_MUTE 0x1000 /* SPK1L_MUTE */
1127 #define WM2200_SPK1L_MUTE_MASK 0x1000 /* SPK1L_MUTE */
1130 #define WM2200_SPK1_MUTE_ENDIAN 0x0100 /* SPK1_MUTE_ENDIAN */
1131 #define WM2200_SPK1_MUTE_ENDIAN_MASK 0x0100 /* SPK1_MUTE_ENDIAN */
1134 #define WM2200_SPK1_MUTE_SEQL_MASK 0x00FF /* SPK1_MUTE_SEQL - [7:0] */
1135 #define WM2200_SPK1_MUTE_SEQL_SHIFT 0 /* SPK1_MUTE_SEQL - [7:0] */
1136 #define WM2200_SPK1_MUTE_SEQL_WIDTH 8 /* SPK1_MUTE_SEQL - [7:0] */
1139 * R1048 (0x418) - PDM 2
1141 #define WM2200_SPK1_FMT 0x0001 /* SPK1_FMT */
1142 #define WM2200_SPK1_FMT_MASK 0x0001 /* SPK1_FMT */
1143 #define WM2200_SPK1_FMT_SHIFT 0 /* SPK1_FMT */
1147 * R1280 (0x500) - Audio IF 1_1
1149 #define WM2200_AIF1_BCLK_INV 0x0040 /* AIF1_BCLK_INV */
1150 #define WM2200_AIF1_BCLK_INV_MASK 0x0040 /* AIF1_BCLK_INV */
1153 #define WM2200_AIF1_BCLK_FRC 0x0020 /* AIF1_BCLK_FRC */
1154 #define WM2200_AIF1_BCLK_FRC_MASK 0x0020 /* AIF1_BCLK_FRC */
1157 #define WM2200_AIF1_BCLK_MSTR 0x0010 /* AIF1_BCLK_MSTR */
1158 #define WM2200_AIF1_BCLK_MSTR_MASK 0x0010 /* AIF1_BCLK_MSTR */
1161 #define WM2200_AIF1_BCLK_DIV_MASK 0x000F /* AIF1_BCLK_DIV - [3:0] */
1162 #define WM2200_AIF1_BCLK_DIV_SHIFT 0 /* AIF1_BCLK_DIV - [3:0] */
1163 #define WM2200_AIF1_BCLK_DIV_WIDTH 4 /* AIF1_BCLK_DIV - [3:0] */
1166 * R1281 (0x501) - Audio IF 1_2
1168 #define WM2200_AIF1TX_DAT_TRI 0x0020 /* AIF1TX_DAT_TRI */
1169 #define WM2200_AIF1TX_DAT_TRI_MASK 0x0020 /* AIF1TX_DAT_TRI */
1172 #define WM2200_AIF1TX_LRCLK_SRC 0x0008 /* AIF1TX_LRCLK_SRC */
1173 #define WM2200_AIF1TX_LRCLK_SRC_MASK 0x0008 /* AIF1TX_LRCLK_SRC */
1176 #define WM2200_AIF1TX_LRCLK_INV 0x0004 /* AIF1TX_LRCLK_INV */
1177 #define WM2200_AIF1TX_LRCLK_INV_MASK 0x0004 /* AIF1TX_LRCLK_INV */
1180 #define WM2200_AIF1TX_LRCLK_FRC 0x0002 /* AIF1TX_LRCLK_FRC */
1181 #define WM2200_AIF1TX_LRCLK_FRC_MASK 0x0002 /* AIF1TX_LRCLK_FRC */
1184 #define WM2200_AIF1TX_LRCLK_MSTR 0x0001 /* AIF1TX_LRCLK_MSTR */
1185 #define WM2200_AIF1TX_LRCLK_MSTR_MASK 0x0001 /* AIF1TX_LRCLK_MSTR */
1186 #define WM2200_AIF1TX_LRCLK_MSTR_SHIFT 0 /* AIF1TX_LRCLK_MSTR */
1190 * R1282 (0x502) - Audio IF 1_3
1192 #define WM2200_AIF1RX_LRCLK_INV 0x0004 /* AIF1RX_LRCLK_INV */
1193 #define WM2200_AIF1RX_LRCLK_INV_MASK 0x0004 /* AIF1RX_LRCLK_INV */
1196 #define WM2200_AIF1RX_LRCLK_FRC 0x0002 /* AIF1RX_LRCLK_FRC */
1197 #define WM2200_AIF1RX_LRCLK_FRC_MASK 0x0002 /* AIF1RX_LRCLK_FRC */
1200 #define WM2200_AIF1RX_LRCLK_MSTR 0x0001 /* AIF1RX_LRCLK_MSTR */
1201 #define WM2200_AIF1RX_LRCLK_MSTR_MASK 0x0001 /* AIF1RX_LRCLK_MSTR */
1202 #define WM2200_AIF1RX_LRCLK_MSTR_SHIFT 0 /* AIF1RX_LRCLK_MSTR */
1206 * R1283 (0x503) - Audio IF 1_4
1208 #define WM2200_AIF1_TRI 0x0040 /* AIF1_TRI */
1209 #define WM2200_AIF1_TRI_MASK 0x0040 /* AIF1_TRI */
1214 * R1284 (0x504) - Audio IF 1_5
1216 #define WM2200_AIF1_FMT_MASK 0x0007 /* AIF1_FMT - [2:0] */
1217 #define WM2200_AIF1_FMT_SHIFT 0 /* AIF1_FMT - [2:0] */
1218 #define WM2200_AIF1_FMT_WIDTH 3 /* AIF1_FMT - [2:0] */
1221 * R1285 (0x505) - Audio IF 1_6
1223 #define WM2200_AIF1TX_BCPF_MASK 0x07FF /* AIF1TX_BCPF - [10:0] */
1224 #define WM2200_AIF1TX_BCPF_SHIFT 0 /* AIF1TX_BCPF - [10:0] */
1225 #define WM2200_AIF1TX_BCPF_WIDTH 11 /* AIF1TX_BCPF - [10:0] */
1228 * R1286 (0x506) - Audio IF 1_7
1230 #define WM2200_AIF1RX_BCPF_MASK 0x07FF /* AIF1RX_BCPF - [10:0] */
1231 #define WM2200_AIF1RX_BCPF_SHIFT 0 /* AIF1RX_BCPF - [10:0] */
1232 #define WM2200_AIF1RX_BCPF_WIDTH 11 /* AIF1RX_BCPF - [10:0] */
1235 * R1287 (0x507) - Audio IF 1_8
1237 #define WM2200_AIF1TX_WL_MASK 0x3F00 /* AIF1TX_WL - [13:8] */
1240 #define WM2200_AIF1TX_SLOT_LEN_MASK 0x00FF /* AIF1TX_SLOT_LEN - [7:0] */
1241 #define WM2200_AIF1TX_SLOT_LEN_SHIFT 0 /* AIF1TX_SLOT_LEN - [7:0] */
1242 #define WM2200_AIF1TX_SLOT_LEN_WIDTH 8 /* AIF1TX_SLOT_LEN - [7:0] */
1245 * R1288 (0x508) - Audio IF 1_9
1247 #define WM2200_AIF1RX_WL_MASK 0x3F00 /* AIF1RX_WL - [13:8] */
1250 #define WM2200_AIF1RX_SLOT_LEN_MASK 0x00FF /* AIF1RX_SLOT_LEN - [7:0] */
1251 #define WM2200_AIF1RX_SLOT_LEN_SHIFT 0 /* AIF1RX_SLOT_LEN - [7:0] */
1252 #define WM2200_AIF1RX_SLOT_LEN_WIDTH 8 /* AIF1RX_SLOT_LEN - [7:0] */
1255 * R1289 (0x509) - Audio IF 1_10
1257 #define WM2200_AIF1TX1_SLOT_MASK 0x003F /* AIF1TX1_SLOT - [5:0] */
1258 #define WM2200_AIF1TX1_SLOT_SHIFT 0 /* AIF1TX1_SLOT - [5:0] */
1259 #define WM2200_AIF1TX1_SLOT_WIDTH 6 /* AIF1TX1_SLOT - [5:0] */
1262 * R1290 (0x50A) - Audio IF 1_11
1264 #define WM2200_AIF1TX2_SLOT_MASK 0x003F /* AIF1TX2_SLOT - [5:0] */
1265 #define WM2200_AIF1TX2_SLOT_SHIFT 0 /* AIF1TX2_SLOT - [5:0] */
1266 #define WM2200_AIF1TX2_SLOT_WIDTH 6 /* AIF1TX2_SLOT - [5:0] */
1269 * R1291 (0x50B) - Audio IF 1_12
1271 #define WM2200_AIF1TX3_SLOT_MASK 0x003F /* AIF1TX3_SLOT - [5:0] */
1272 #define WM2200_AIF1TX3_SLOT_SHIFT 0 /* AIF1TX3_SLOT - [5:0] */
1273 #define WM2200_AIF1TX3_SLOT_WIDTH 6 /* AIF1TX3_SLOT - [5:0] */
1276 * R1292 (0x50C) - Audio IF 1_13
1278 #define WM2200_AIF1TX4_SLOT_MASK 0x003F /* AIF1TX4_SLOT - [5:0] */
1279 #define WM2200_AIF1TX4_SLOT_SHIFT 0 /* AIF1TX4_SLOT - [5:0] */
1280 #define WM2200_AIF1TX4_SLOT_WIDTH 6 /* AIF1TX4_SLOT - [5:0] */
1283 * R1293 (0x50D) - Audio IF 1_14
1285 #define WM2200_AIF1TX5_SLOT_MASK 0x003F /* AIF1TX5_SLOT - [5:0] */
1286 #define WM2200_AIF1TX5_SLOT_SHIFT 0 /* AIF1TX5_SLOT - [5:0] */
1287 #define WM2200_AIF1TX5_SLOT_WIDTH 6 /* AIF1TX5_SLOT - [5:0] */
1290 * R1294 (0x50E) - Audio IF 1_15
1292 #define WM2200_AIF1TX6_SLOT_MASK 0x003F /* AIF1TX6_SLOT - [5:0] */
1293 #define WM2200_AIF1TX6_SLOT_SHIFT 0 /* AIF1TX6_SLOT - [5:0] */
1294 #define WM2200_AIF1TX6_SLOT_WIDTH 6 /* AIF1TX6_SLOT - [5:0] */
1297 * R1295 (0x50F) - Audio IF 1_16
1299 #define WM2200_AIF1RX1_SLOT_MASK 0x003F /* AIF1RX1_SLOT - [5:0] */
1300 #define WM2200_AIF1RX1_SLOT_SHIFT 0 /* AIF1RX1_SLOT - [5:0] */
1301 #define WM2200_AIF1RX1_SLOT_WIDTH 6 /* AIF1RX1_SLOT - [5:0] */
1304 * R1296 (0x510) - Audio IF 1_17
1306 #define WM2200_AIF1RX2_SLOT_MASK 0x003F /* AIF1RX2_SLOT - [5:0] */
1307 #define WM2200_AIF1RX2_SLOT_SHIFT 0 /* AIF1RX2_SLOT - [5:0] */
1308 #define WM2200_AIF1RX2_SLOT_WIDTH 6 /* AIF1RX2_SLOT - [5:0] */
1311 * R1297 (0x511) - Audio IF 1_18
1313 #define WM2200_AIF1RX3_SLOT_MASK 0x003F /* AIF1RX3_SLOT - [5:0] */
1314 #define WM2200_AIF1RX3_SLOT_SHIFT 0 /* AIF1RX3_SLOT - [5:0] */
1315 #define WM2200_AIF1RX3_SLOT_WIDTH 6 /* AIF1RX3_SLOT - [5:0] */
1318 * R1298 (0x512) - Audio IF 1_19
1320 #define WM2200_AIF1RX4_SLOT_MASK 0x003F /* AIF1RX4_SLOT - [5:0] */
1321 #define WM2200_AIF1RX4_SLOT_SHIFT 0 /* AIF1RX4_SLOT - [5:0] */
1322 #define WM2200_AIF1RX4_SLOT_WIDTH 6 /* AIF1RX4_SLOT - [5:0] */
1325 * R1299 (0x513) - Audio IF 1_20
1327 #define WM2200_AIF1RX5_SLOT_MASK 0x003F /* AIF1RX5_SLOT - [5:0] */
1328 #define WM2200_AIF1RX5_SLOT_SHIFT 0 /* AIF1RX5_SLOT - [5:0] */
1329 #define WM2200_AIF1RX5_SLOT_WIDTH 6 /* AIF1RX5_SLOT - [5:0] */
1332 * R1300 (0x514) - Audio IF 1_21
1334 #define WM2200_AIF1RX6_SLOT_MASK 0x003F /* AIF1RX6_SLOT - [5:0] */
1335 #define WM2200_AIF1RX6_SLOT_SHIFT 0 /* AIF1RX6_SLOT - [5:0] */
1336 #define WM2200_AIF1RX6_SLOT_WIDTH 6 /* AIF1RX6_SLOT - [5:0] */
1339 * R1301 (0x515) - Audio IF 1_22
1341 #define WM2200_AIF1RX6_ENA 0x0800 /* AIF1RX6_ENA */
1342 #define WM2200_AIF1RX6_ENA_MASK 0x0800 /* AIF1RX6_ENA */
1345 #define WM2200_AIF1RX5_ENA 0x0400 /* AIF1RX5_ENA */
1346 #define WM2200_AIF1RX5_ENA_MASK 0x0400 /* AIF1RX5_ENA */
1349 #define WM2200_AIF1RX4_ENA 0x0200 /* AIF1RX4_ENA */
1350 #define WM2200_AIF1RX4_ENA_MASK 0x0200 /* AIF1RX4_ENA */
1353 #define WM2200_AIF1RX3_ENA 0x0100 /* AIF1RX3_ENA */
1354 #define WM2200_AIF1RX3_ENA_MASK 0x0100 /* AIF1RX3_ENA */
1357 #define WM2200_AIF1RX2_ENA 0x0080 /* AIF1RX2_ENA */
1358 #define WM2200_AIF1RX2_ENA_MASK 0x0080 /* AIF1RX2_ENA */
1361 #define WM2200_AIF1RX1_ENA 0x0040 /* AIF1RX1_ENA */
1362 #define WM2200_AIF1RX1_ENA_MASK 0x0040 /* AIF1RX1_ENA */
1365 #define WM2200_AIF1TX6_ENA 0x0020 /* AIF1TX6_ENA */
1366 #define WM2200_AIF1TX6_ENA_MASK 0x0020 /* AIF1TX6_ENA */
1369 #define WM2200_AIF1TX5_ENA 0x0010 /* AIF1TX5_ENA */
1370 #define WM2200_AIF1TX5_ENA_MASK 0x0010 /* AIF1TX5_ENA */
1373 #define WM2200_AIF1TX4_ENA 0x0008 /* AIF1TX4_ENA */
1374 #define WM2200_AIF1TX4_ENA_MASK 0x0008 /* AIF1TX4_ENA */
1377 #define WM2200_AIF1TX3_ENA 0x0004 /* AIF1TX3_ENA */
1378 #define WM2200_AIF1TX3_ENA_MASK 0x0004 /* AIF1TX3_ENA */
1381 #define WM2200_AIF1TX2_ENA 0x0002 /* AIF1TX2_ENA */
1382 #define WM2200_AIF1TX2_ENA_MASK 0x0002 /* AIF1TX2_ENA */
1385 #define WM2200_AIF1TX1_ENA 0x0001 /* AIF1TX1_ENA */
1386 #define WM2200_AIF1TX1_ENA_MASK 0x0001 /* AIF1TX1_ENA */
1387 #define WM2200_AIF1TX1_ENA_SHIFT 0 /* AIF1TX1_ENA */
1391 * R1536 (0x600) - OUT1LMIX Input 1 Source
1393 #define WM2200_OUT1LMIX_SRC1_MASK 0x007F /* OUT1LMIX_SRC1 - [6:0] */
1394 #define WM2200_OUT1LMIX_SRC1_SHIFT 0 /* OUT1LMIX_SRC1 - [6:0] */
1395 #define WM2200_OUT1LMIX_SRC1_WIDTH 7 /* OUT1LMIX_SRC1 - [6:0] */
1398 * R1537 (0x601) - OUT1LMIX Input 1 Volume
1400 #define WM2200_OUT1LMIX_VOL1_MASK 0x00FE /* OUT1LMIX_VOL1 - [7:1] */
1405 * R1538 (0x602) - OUT1LMIX Input 2 Source
1407 #define WM2200_OUT1LMIX_SRC2_MASK 0x007F /* OUT1LMIX_SRC2 - [6:0] */
1408 #define WM2200_OUT1LMIX_SRC2_SHIFT 0 /* OUT1LMIX_SRC2 - [6:0] */
1409 #define WM2200_OUT1LMIX_SRC2_WIDTH 7 /* OUT1LMIX_SRC2 - [6:0] */
1412 * R1539 (0x603) - OUT1LMIX Input 2 Volume
1414 #define WM2200_OUT1LMIX_VOL2_MASK 0x00FE /* OUT1LMIX_VOL2 - [7:1] */
1419 * R1540 (0x604) - OUT1LMIX Input 3 Source
1421 #define WM2200_OUT1LMIX_SRC3_MASK 0x007F /* OUT1LMIX_SRC3 - [6:0] */
1422 #define WM2200_OUT1LMIX_SRC3_SHIFT 0 /* OUT1LMIX_SRC3 - [6:0] */
1423 #define WM2200_OUT1LMIX_SRC3_WIDTH 7 /* OUT1LMIX_SRC3 - [6:0] */
1426 * R1541 (0x605) - OUT1LMIX Input 3 Volume
1428 #define WM2200_OUT1LMIX_VOL3_MASK 0x00FE /* OUT1LMIX_VOL3 - [7:1] */
1433 * R1542 (0x606) - OUT1LMIX Input 4 Source
1435 #define WM2200_OUT1LMIX_SRC4_MASK 0x007F /* OUT1LMIX_SRC4 - [6:0] */
1436 #define WM2200_OUT1LMIX_SRC4_SHIFT 0 /* OUT1LMIX_SRC4 - [6:0] */
1437 #define WM2200_OUT1LMIX_SRC4_WIDTH 7 /* OUT1LMIX_SRC4 - [6:0] */
1440 * R1543 (0x607) - OUT1LMIX Input 4 Volume
1442 #define WM2200_OUT1LMIX_VOL4_MASK 0x00FE /* OUT1LMIX_VOL4 - [7:1] */
1447 * R1544 (0x608) - OUT1RMIX Input 1 Source
1449 #define WM2200_OUT1RMIX_SRC1_MASK 0x007F /* OUT1RMIX_SRC1 - [6:0] */
1450 #define WM2200_OUT1RMIX_SRC1_SHIFT 0 /* OUT1RMIX_SRC1 - [6:0] */
1451 #define WM2200_OUT1RMIX_SRC1_WIDTH 7 /* OUT1RMIX_SRC1 - [6:0] */
1454 * R1545 (0x609) - OUT1RMIX Input 1 Volume
1456 #define WM2200_OUT1RMIX_VOL1_MASK 0x00FE /* OUT1RMIX_VOL1 - [7:1] */
1461 * R1546 (0x60A) - OUT1RMIX Input 2 Source
1463 #define WM2200_OUT1RMIX_SRC2_MASK 0x007F /* OUT1RMIX_SRC2 - [6:0] */
1464 #define WM2200_OUT1RMIX_SRC2_SHIFT 0 /* OUT1RMIX_SRC2 - [6:0] */
1465 #define WM2200_OUT1RMIX_SRC2_WIDTH 7 /* OUT1RMIX_SRC2 - [6:0] */
1468 * R1547 (0x60B) - OUT1RMIX Input 2 Volume
1470 #define WM2200_OUT1RMIX_VOL2_MASK 0x00FE /* OUT1RMIX_VOL2 - [7:1] */
1475 * R1548 (0x60C) - OUT1RMIX Input 3 Source
1477 #define WM2200_OUT1RMIX_SRC3_MASK 0x007F /* OUT1RMIX_SRC3 - [6:0] */
1478 #define WM2200_OUT1RMIX_SRC3_SHIFT 0 /* OUT1RMIX_SRC3 - [6:0] */
1479 #define WM2200_OUT1RMIX_SRC3_WIDTH 7 /* OUT1RMIX_SRC3 - [6:0] */
1482 * R1549 (0x60D) - OUT1RMIX Input 3 Volume
1484 #define WM2200_OUT1RMIX_VOL3_MASK 0x00FE /* OUT1RMIX_VOL3 - [7:1] */
1489 * R1550 (0x60E) - OUT1RMIX Input 4 Source
1491 #define WM2200_OUT1RMIX_SRC4_MASK 0x007F /* OUT1RMIX_SRC4 - [6:0] */
1492 #define WM2200_OUT1RMIX_SRC4_SHIFT 0 /* OUT1RMIX_SRC4 - [6:0] */
1493 #define WM2200_OUT1RMIX_SRC4_WIDTH 7 /* OUT1RMIX_SRC4 - [6:0] */
1496 * R1551 (0x60F) - OUT1RMIX Input 4 Volume
1498 #define WM2200_OUT1RMIX_VOL4_MASK 0x00FE /* OUT1RMIX_VOL4 - [7:1] */
1503 * R1552 (0x610) - OUT2LMIX Input 1 Source
1505 #define WM2200_OUT2LMIX_SRC1_MASK 0x007F /* OUT2LMIX_SRC1 - [6:0] */
1506 #define WM2200_OUT2LMIX_SRC1_SHIFT 0 /* OUT2LMIX_SRC1 - [6:0] */
1507 #define WM2200_OUT2LMIX_SRC1_WIDTH 7 /* OUT2LMIX_SRC1 - [6:0] */
1510 * R1553 (0x611) - OUT2LMIX Input 1 Volume
1512 #define WM2200_OUT2LMIX_VOL1_MASK 0x00FE /* OUT2LMIX_VOL1 - [7:1] */
1517 * R1554 (0x612) - OUT2LMIX Input 2 Source
1519 #define WM2200_OUT2LMIX_SRC2_MASK 0x007F /* OUT2LMIX_SRC2 - [6:0] */
1520 #define WM2200_OUT2LMIX_SRC2_SHIFT 0 /* OUT2LMIX_SRC2 - [6:0] */
1521 #define WM2200_OUT2LMIX_SRC2_WIDTH 7 /* OUT2LMIX_SRC2 - [6:0] */
1524 * R1555 (0x613) - OUT2LMIX Input 2 Volume
1526 #define WM2200_OUT2LMIX_VOL2_MASK 0x00FE /* OUT2LMIX_VOL2 - [7:1] */
1531 * R1556 (0x614) - OUT2LMIX Input 3 Source
1533 #define WM2200_OUT2LMIX_SRC3_MASK 0x007F /* OUT2LMIX_SRC3 - [6:0] */
1534 #define WM2200_OUT2LMIX_SRC3_SHIFT 0 /* OUT2LMIX_SRC3 - [6:0] */
1535 #define WM2200_OUT2LMIX_SRC3_WIDTH 7 /* OUT2LMIX_SRC3 - [6:0] */
1538 * R1557 (0x615) - OUT2LMIX Input 3 Volume
1540 #define WM2200_OUT2LMIX_VOL3_MASK 0x00FE /* OUT2LMIX_VOL3 - [7:1] */
1545 * R1558 (0x616) - OUT2LMIX Input 4 Source
1547 #define WM2200_OUT2LMIX_SRC4_MASK 0x007F /* OUT2LMIX_SRC4 - [6:0] */
1548 #define WM2200_OUT2LMIX_SRC4_SHIFT 0 /* OUT2LMIX_SRC4 - [6:0] */
1549 #define WM2200_OUT2LMIX_SRC4_WIDTH 7 /* OUT2LMIX_SRC4 - [6:0] */
1552 * R1559 (0x617) - OUT2LMIX Input 4 Volume
1554 #define WM2200_OUT2LMIX_VOL4_MASK 0x00FE /* OUT2LMIX_VOL4 - [7:1] */
1559 * R1560 (0x618) - OUT2RMIX Input 1 Source
1561 #define WM2200_OUT2RMIX_SRC1_MASK 0x007F /* OUT2RMIX_SRC1 - [6:0] */
1562 #define WM2200_OUT2RMIX_SRC1_SHIFT 0 /* OUT2RMIX_SRC1 - [6:0] */
1563 #define WM2200_OUT2RMIX_SRC1_WIDTH 7 /* OUT2RMIX_SRC1 - [6:0] */
1566 * R1561 (0x619) - OUT2RMIX Input 1 Volume
1568 #define WM2200_OUT2RMIX_VOL1_MASK 0x00FE /* OUT2RMIX_VOL1 - [7:1] */
1573 * R1562 (0x61A) - OUT2RMIX Input 2 Source
1575 #define WM2200_OUT2RMIX_SRC2_MASK 0x007F /* OUT2RMIX_SRC2 - [6:0] */
1576 #define WM2200_OUT2RMIX_SRC2_SHIFT 0 /* OUT2RMIX_SRC2 - [6:0] */
1577 #define WM2200_OUT2RMIX_SRC2_WIDTH 7 /* OUT2RMIX_SRC2 - [6:0] */
1580 * R1563 (0x61B) - OUT2RMIX Input 2 Volume
1582 #define WM2200_OUT2RMIX_VOL2_MASK 0x00FE /* OUT2RMIX_VOL2 - [7:1] */
1587 * R1564 (0x61C) - OUT2RMIX Input 3 Source
1589 #define WM2200_OUT2RMIX_SRC3_MASK 0x007F /* OUT2RMIX_SRC3 - [6:0] */
1590 #define WM2200_OUT2RMIX_SRC3_SHIFT 0 /* OUT2RMIX_SRC3 - [6:0] */
1591 #define WM2200_OUT2RMIX_SRC3_WIDTH 7 /* OUT2RMIX_SRC3 - [6:0] */
1594 * R1565 (0x61D) - OUT2RMIX Input 3 Volume
1596 #define WM2200_OUT2RMIX_VOL3_MASK 0x00FE /* OUT2RMIX_VOL3 - [7:1] */
1601 * R1566 (0x61E) - OUT2RMIX Input 4 Source
1603 #define WM2200_OUT2RMIX_SRC4_MASK 0x007F /* OUT2RMIX_SRC4 - [6:0] */
1604 #define WM2200_OUT2RMIX_SRC4_SHIFT 0 /* OUT2RMIX_SRC4 - [6:0] */
1605 #define WM2200_OUT2RMIX_SRC4_WIDTH 7 /* OUT2RMIX_SRC4 - [6:0] */
1608 * R1567 (0x61F) - OUT2RMIX Input 4 Volume
1610 #define WM2200_OUT2RMIX_VOL4_MASK 0x00FE /* OUT2RMIX_VOL4 - [7:1] */
1615 * R1568 (0x620) - AIF1TX1MIX Input 1 Source
1617 #define WM2200_AIF1TX1MIX_SRC1_MASK 0x007F /* AIF1TX1MIX_SRC1 - [6:0] */
1618 #define WM2200_AIF1TX1MIX_SRC1_SHIFT 0 /* AIF1TX1MIX_SRC1 - [6:0] */
1619 #define WM2200_AIF1TX1MIX_SRC1_WIDTH 7 /* AIF1TX1MIX_SRC1 - [6:0] */
1622 * R1569 (0x621) - AIF1TX1MIX Input 1 Volume
1624 #define WM2200_AIF1TX1MIX_VOL1_MASK 0x00FE /* AIF1TX1MIX_VOL1 - [7:1] */
1629 * R1570 (0x622) - AIF1TX1MIX Input 2 Source
1631 #define WM2200_AIF1TX1MIX_SRC2_MASK 0x007F /* AIF1TX1MIX_SRC2 - [6:0] */
1632 #define WM2200_AIF1TX1MIX_SRC2_SHIFT 0 /* AIF1TX1MIX_SRC2 - [6:0] */
1633 #define WM2200_AIF1TX1MIX_SRC2_WIDTH 7 /* AIF1TX1MIX_SRC2 - [6:0] */
1636 * R1571 (0x623) - AIF1TX1MIX Input 2 Volume
1638 #define WM2200_AIF1TX1MIX_VOL2_MASK 0x00FE /* AIF1TX1MIX_VOL2 - [7:1] */
1643 * R1572 (0x624) - AIF1TX1MIX Input 3 Source
1645 #define WM2200_AIF1TX1MIX_SRC3_MASK 0x007F /* AIF1TX1MIX_SRC3 - [6:0] */
1646 #define WM2200_AIF1TX1MIX_SRC3_SHIFT 0 /* AIF1TX1MIX_SRC3 - [6:0] */
1647 #define WM2200_AIF1TX1MIX_SRC3_WIDTH 7 /* AIF1TX1MIX_SRC3 - [6:0] */
1650 * R1573 (0x625) - AIF1TX1MIX Input 3 Volume
1652 #define WM2200_AIF1TX1MIX_VOL3_MASK 0x00FE /* AIF1TX1MIX_VOL3 - [7:1] */
1657 * R1574 (0x626) - AIF1TX1MIX Input 4 Source
1659 #define WM2200_AIF1TX1MIX_SRC4_MASK 0x007F /* AIF1TX1MIX_SRC4 - [6:0] */
1660 #define WM2200_AIF1TX1MIX_SRC4_SHIFT 0 /* AIF1TX1MIX_SRC4 - [6:0] */
1661 #define WM2200_AIF1TX1MIX_SRC4_WIDTH 7 /* AIF1TX1MIX_SRC4 - [6:0] */
1664 * R1575 (0x627) - AIF1TX1MIX Input 4 Volume
1666 #define WM2200_AIF1TX1MIX_VOL4_MASK 0x00FE /* AIF1TX1MIX_VOL4 - [7:1] */
1671 * R1576 (0x628) - AIF1TX2MIX Input 1 Source
1673 #define WM2200_AIF1TX2MIX_SRC1_MASK 0x007F /* AIF1TX2MIX_SRC1 - [6:0] */
1674 #define WM2200_AIF1TX2MIX_SRC1_SHIFT 0 /* AIF1TX2MIX_SRC1 - [6:0] */
1675 #define WM2200_AIF1TX2MIX_SRC1_WIDTH 7 /* AIF1TX2MIX_SRC1 - [6:0] */
1678 * R1577 (0x629) - AIF1TX2MIX Input 1 Volume
1680 #define WM2200_AIF1TX2MIX_VOL1_MASK 0x00FE /* AIF1TX2MIX_VOL1 - [7:1] */
1685 * R1578 (0x62A) - AIF1TX2MIX Input 2 Source
1687 #define WM2200_AIF1TX2MIX_SRC2_MASK 0x007F /* AIF1TX2MIX_SRC2 - [6:0] */
1688 #define WM2200_AIF1TX2MIX_SRC2_SHIFT 0 /* AIF1TX2MIX_SRC2 - [6:0] */
1689 #define WM2200_AIF1TX2MIX_SRC2_WIDTH 7 /* AIF1TX2MIX_SRC2 - [6:0] */
1692 * R1579 (0x62B) - AIF1TX2MIX Input 2 Volume
1694 #define WM2200_AIF1TX2MIX_VOL2_MASK 0x00FE /* AIF1TX2MIX_VOL2 - [7:1] */
1699 * R1580 (0x62C) - AIF1TX2MIX Input 3 Source
1701 #define WM2200_AIF1TX2MIX_SRC3_MASK 0x007F /* AIF1TX2MIX_SRC3 - [6:0] */
1702 #define WM2200_AIF1TX2MIX_SRC3_SHIFT 0 /* AIF1TX2MIX_SRC3 - [6:0] */
1703 #define WM2200_AIF1TX2MIX_SRC3_WIDTH 7 /* AIF1TX2MIX_SRC3 - [6:0] */
1706 * R1581 (0x62D) - AIF1TX2MIX Input 3 Volume
1708 #define WM2200_AIF1TX2MIX_VOL3_MASK 0x00FE /* AIF1TX2MIX_VOL3 - [7:1] */
1713 * R1582 (0x62E) - AIF1TX2MIX Input 4 Source
1715 #define WM2200_AIF1TX2MIX_SRC4_MASK 0x007F /* AIF1TX2MIX_SRC4 - [6:0] */
1716 #define WM2200_AIF1TX2MIX_SRC4_SHIFT 0 /* AIF1TX2MIX_SRC4 - [6:0] */
1717 #define WM2200_AIF1TX2MIX_SRC4_WIDTH 7 /* AIF1TX2MIX_SRC4 - [6:0] */
1720 * R1583 (0x62F) - AIF1TX2MIX Input 4 Volume
1722 #define WM2200_AIF1TX2MIX_VOL4_MASK 0x00FE /* AIF1TX2MIX_VOL4 - [7:1] */
1727 * R1584 (0x630) - AIF1TX3MIX Input 1 Source
1729 #define WM2200_AIF1TX3MIX_SRC1_MASK 0x007F /* AIF1TX3MIX_SRC1 - [6:0] */
1730 #define WM2200_AIF1TX3MIX_SRC1_SHIFT 0 /* AIF1TX3MIX_SRC1 - [6:0] */
1731 #define WM2200_AIF1TX3MIX_SRC1_WIDTH 7 /* AIF1TX3MIX_SRC1 - [6:0] */
1734 * R1585 (0x631) - AIF1TX3MIX Input 1 Volume
1736 #define WM2200_AIF1TX3MIX_VOL1_MASK 0x00FE /* AIF1TX3MIX_VOL1 - [7:1] */
1741 * R1586 (0x632) - AIF1TX3MIX Input 2 Source
1743 #define WM2200_AIF1TX3MIX_SRC2_MASK 0x007F /* AIF1TX3MIX_SRC2 - [6:0] */
1744 #define WM2200_AIF1TX3MIX_SRC2_SHIFT 0 /* AIF1TX3MIX_SRC2 - [6:0] */
1745 #define WM2200_AIF1TX3MIX_SRC2_WIDTH 7 /* AIF1TX3MIX_SRC2 - [6:0] */
1748 * R1587 (0x633) - AIF1TX3MIX Input 2 Volume
1750 #define WM2200_AIF1TX3MIX_VOL2_MASK 0x00FE /* AIF1TX3MIX_VOL2 - [7:1] */
1755 * R1588 (0x634) - AIF1TX3MIX Input 3 Source
1757 #define WM2200_AIF1TX3MIX_SRC3_MASK 0x007F /* AIF1TX3MIX_SRC3 - [6:0] */
1758 #define WM2200_AIF1TX3MIX_SRC3_SHIFT 0 /* AIF1TX3MIX_SRC3 - [6:0] */
1759 #define WM2200_AIF1TX3MIX_SRC3_WIDTH 7 /* AIF1TX3MIX_SRC3 - [6:0] */
1762 * R1589 (0x635) - AIF1TX3MIX Input 3 Volume
1764 #define WM2200_AIF1TX3MIX_VOL3_MASK 0x00FE /* AIF1TX3MIX_VOL3 - [7:1] */
1769 * R1590 (0x636) - AIF1TX3MIX Input 4 Source
1771 #define WM2200_AIF1TX3MIX_SRC4_MASK 0x007F /* AIF1TX3MIX_SRC4 - [6:0] */
1772 #define WM2200_AIF1TX3MIX_SRC4_SHIFT 0 /* AIF1TX3MIX_SRC4 - [6:0] */
1773 #define WM2200_AIF1TX3MIX_SRC4_WIDTH 7 /* AIF1TX3MIX_SRC4 - [6:0] */
1776 * R1591 (0x637) - AIF1TX3MIX Input 4 Volume
1778 #define WM2200_AIF1TX3MIX_VOL4_MASK 0x00FE /* AIF1TX3MIX_VOL4 - [7:1] */
1783 * R1592 (0x638) - AIF1TX4MIX Input 1 Source
1785 #define WM2200_AIF1TX4MIX_SRC1_MASK 0x007F /* AIF1TX4MIX_SRC1 - [6:0] */
1786 #define WM2200_AIF1TX4MIX_SRC1_SHIFT 0 /* AIF1TX4MIX_SRC1 - [6:0] */
1787 #define WM2200_AIF1TX4MIX_SRC1_WIDTH 7 /* AIF1TX4MIX_SRC1 - [6:0] */
1790 * R1593 (0x639) - AIF1TX4MIX Input 1 Volume
1792 #define WM2200_AIF1TX4MIX_VOL1_MASK 0x00FE /* AIF1TX4MIX_VOL1 - [7:1] */
1797 * R1594 (0x63A) - AIF1TX4MIX Input 2 Source
1799 #define WM2200_AIF1TX4MIX_SRC2_MASK 0x007F /* AIF1TX4MIX_SRC2 - [6:0] */
1800 #define WM2200_AIF1TX4MIX_SRC2_SHIFT 0 /* AIF1TX4MIX_SRC2 - [6:0] */
1801 #define WM2200_AIF1TX4MIX_SRC2_WIDTH 7 /* AIF1TX4MIX_SRC2 - [6:0] */
1804 * R1595 (0x63B) - AIF1TX4MIX Input 2 Volume
1806 #define WM2200_AIF1TX4MIX_VOL2_MASK 0x00FE /* AIF1TX4MIX_VOL2 - [7:1] */
1811 * R1596 (0x63C) - AIF1TX4MIX Input 3 Source
1813 #define WM2200_AIF1TX4MIX_SRC3_MASK 0x007F /* AIF1TX4MIX_SRC3 - [6:0] */
1814 #define WM2200_AIF1TX4MIX_SRC3_SHIFT 0 /* AIF1TX4MIX_SRC3 - [6:0] */
1815 #define WM2200_AIF1TX4MIX_SRC3_WIDTH 7 /* AIF1TX4MIX_SRC3 - [6:0] */
1818 * R1597 (0x63D) - AIF1TX4MIX Input 3 Volume
1820 #define WM2200_AIF1TX4MIX_VOL3_MASK 0x00FE /* AIF1TX4MIX_VOL3 - [7:1] */
1825 * R1598 (0x63E) - AIF1TX4MIX Input 4 Source
1827 #define WM2200_AIF1TX4MIX_SRC4_MASK 0x007F /* AIF1TX4MIX_SRC4 - [6:0] */
1828 #define WM2200_AIF1TX4MIX_SRC4_SHIFT 0 /* AIF1TX4MIX_SRC4 - [6:0] */
1829 #define WM2200_AIF1TX4MIX_SRC4_WIDTH 7 /* AIF1TX4MIX_SRC4 - [6:0] */
1832 * R1599 (0x63F) - AIF1TX4MIX Input 4 Volume
1834 #define WM2200_AIF1TX4MIX_VOL4_MASK 0x00FE /* AIF1TX4MIX_VOL4 - [7:1] */
1839 * R1600 (0x640) - AIF1TX5MIX Input 1 Source
1841 #define WM2200_AIF1TX5MIX_SRC1_MASK 0x007F /* AIF1TX5MIX_SRC1 - [6:0] */
1842 #define WM2200_AIF1TX5MIX_SRC1_SHIFT 0 /* AIF1TX5MIX_SRC1 - [6:0] */
1843 #define WM2200_AIF1TX5MIX_SRC1_WIDTH 7 /* AIF1TX5MIX_SRC1 - [6:0] */
1846 * R1601 (0x641) - AIF1TX5MIX Input 1 Volume
1848 #define WM2200_AIF1TX5MIX_VOL1_MASK 0x00FE /* AIF1TX5MIX_VOL1 - [7:1] */
1853 * R1602 (0x642) - AIF1TX5MIX Input 2 Source
1855 #define WM2200_AIF1TX5MIX_SRC2_MASK 0x007F /* AIF1TX5MIX_SRC2 - [6:0] */
1856 #define WM2200_AIF1TX5MIX_SRC2_SHIFT 0 /* AIF1TX5MIX_SRC2 - [6:0] */
1857 #define WM2200_AIF1TX5MIX_SRC2_WIDTH 7 /* AIF1TX5MIX_SRC2 - [6:0] */
1860 * R1603 (0x643) - AIF1TX5MIX Input 2 Volume
1862 #define WM2200_AIF1TX5MIX_VOL2_MASK 0x00FE /* AIF1TX5MIX_VOL2 - [7:1] */
1867 * R1604 (0x644) - AIF1TX5MIX Input 3 Source
1869 #define WM2200_AIF1TX5MIX_SRC3_MASK 0x007F /* AIF1TX5MIX_SRC3 - [6:0] */
1870 #define WM2200_AIF1TX5MIX_SRC3_SHIFT 0 /* AIF1TX5MIX_SRC3 - [6:0] */
1871 #define WM2200_AIF1TX5MIX_SRC3_WIDTH 7 /* AIF1TX5MIX_SRC3 - [6:0] */
1874 * R1605 (0x645) - AIF1TX5MIX Input 3 Volume
1876 #define WM2200_AIF1TX5MIX_VOL3_MASK 0x00FE /* AIF1TX5MIX_VOL3 - [7:1] */
1881 * R1606 (0x646) - AIF1TX5MIX Input 4 Source
1883 #define WM2200_AIF1TX5MIX_SRC4_MASK 0x007F /* AIF1TX5MIX_SRC4 - [6:0] */
1884 #define WM2200_AIF1TX5MIX_SRC4_SHIFT 0 /* AIF1TX5MIX_SRC4 - [6:0] */
1885 #define WM2200_AIF1TX5MIX_SRC4_WIDTH 7 /* AIF1TX5MIX_SRC4 - [6:0] */
1888 * R1607 (0x647) - AIF1TX5MIX Input 4 Volume
1890 #define WM2200_AIF1TX5MIX_VOL4_MASK 0x00FE /* AIF1TX5MIX_VOL4 - [7:1] */
1895 * R1608 (0x648) - AIF1TX6MIX Input 1 Source
1897 #define WM2200_AIF1TX6MIX_SRC1_MASK 0x007F /* AIF1TX6MIX_SRC1 - [6:0] */
1898 #define WM2200_AIF1TX6MIX_SRC1_SHIFT 0 /* AIF1TX6MIX_SRC1 - [6:0] */
1899 #define WM2200_AIF1TX6MIX_SRC1_WIDTH 7 /* AIF1TX6MIX_SRC1 - [6:0] */
1902 * R1609 (0x649) - AIF1TX6MIX Input 1 Volume
1904 #define WM2200_AIF1TX6MIX_VOL1_MASK 0x00FE /* AIF1TX6MIX_VOL1 - [7:1] */
1909 * R1610 (0x64A) - AIF1TX6MIX Input 2 Source
1911 #define WM2200_AIF1TX6MIX_SRC2_MASK 0x007F /* AIF1TX6MIX_SRC2 - [6:0] */
1912 #define WM2200_AIF1TX6MIX_SRC2_SHIFT 0 /* AIF1TX6MIX_SRC2 - [6:0] */
1913 #define WM2200_AIF1TX6MIX_SRC2_WIDTH 7 /* AIF1TX6MIX_SRC2 - [6:0] */
1916 * R1611 (0x64B) - AIF1TX6MIX Input 2 Volume
1918 #define WM2200_AIF1TX6MIX_VOL2_MASK 0x00FE /* AIF1TX6MIX_VOL2 - [7:1] */
1923 * R1612 (0x64C) - AIF1TX6MIX Input 3 Source
1925 #define WM2200_AIF1TX6MIX_SRC3_MASK 0x007F /* AIF1TX6MIX_SRC3 - [6:0] */
1926 #define WM2200_AIF1TX6MIX_SRC3_SHIFT 0 /* AIF1TX6MIX_SRC3 - [6:0] */
1927 #define WM2200_AIF1TX6MIX_SRC3_WIDTH 7 /* AIF1TX6MIX_SRC3 - [6:0] */
1930 * R1613 (0x64D) - AIF1TX6MIX Input 3 Volume
1932 #define WM2200_AIF1TX6MIX_VOL3_MASK 0x00FE /* AIF1TX6MIX_VOL3 - [7:1] */
1937 * R1614 (0x64E) - AIF1TX6MIX Input 4 Source
1939 #define WM2200_AIF1TX6MIX_SRC4_MASK 0x007F /* AIF1TX6MIX_SRC4 - [6:0] */
1940 #define WM2200_AIF1TX6MIX_SRC4_SHIFT 0 /* AIF1TX6MIX_SRC4 - [6:0] */
1941 #define WM2200_AIF1TX6MIX_SRC4_WIDTH 7 /* AIF1TX6MIX_SRC4 - [6:0] */
1944 * R1615 (0x64F) - AIF1TX6MIX Input 4 Volume
1946 #define WM2200_AIF1TX6MIX_VOL4_MASK 0x00FE /* AIF1TX6MIX_VOL4 - [7:1] */
1951 * R1616 (0x650) - EQLMIX Input 1 Source
1953 #define WM2200_EQLMIX_SRC1_MASK 0x007F /* EQLMIX_SRC1 - [6:0] */
1954 #define WM2200_EQLMIX_SRC1_SHIFT 0 /* EQLMIX_SRC1 - [6:0] */
1955 #define WM2200_EQLMIX_SRC1_WIDTH 7 /* EQLMIX_SRC1 - [6:0] */
1958 * R1617 (0x651) - EQLMIX Input 1 Volume
1960 #define WM2200_EQLMIX_VOL1_MASK 0x00FE /* EQLMIX_VOL1 - [7:1] */
1965 * R1618 (0x652) - EQLMIX Input 2 Source
1967 #define WM2200_EQLMIX_SRC2_MASK 0x007F /* EQLMIX_SRC2 - [6:0] */
1968 #define WM2200_EQLMIX_SRC2_SHIFT 0 /* EQLMIX_SRC2 - [6:0] */
1969 #define WM2200_EQLMIX_SRC2_WIDTH 7 /* EQLMIX_SRC2 - [6:0] */
1972 * R1619 (0x653) - EQLMIX Input 2 Volume
1974 #define WM2200_EQLMIX_VOL2_MASK 0x00FE /* EQLMIX_VOL2 - [7:1] */
1979 * R1620 (0x654) - EQLMIX Input 3 Source
1981 #define WM2200_EQLMIX_SRC3_MASK 0x007F /* EQLMIX_SRC3 - [6:0] */
1982 #define WM2200_EQLMIX_SRC3_SHIFT 0 /* EQLMIX_SRC3 - [6:0] */
1983 #define WM2200_EQLMIX_SRC3_WIDTH 7 /* EQLMIX_SRC3 - [6:0] */
1986 * R1621 (0x655) - EQLMIX Input 3 Volume
1988 #define WM2200_EQLMIX_VOL3_MASK 0x00FE /* EQLMIX_VOL3 - [7:1] */
1993 * R1622 (0x656) - EQLMIX Input 4 Source
1995 #define WM2200_EQLMIX_SRC4_MASK 0x007F /* EQLMIX_SRC4 - [6:0] */
1996 #define WM2200_EQLMIX_SRC4_SHIFT 0 /* EQLMIX_SRC4 - [6:0] */
1997 #define WM2200_EQLMIX_SRC4_WIDTH 7 /* EQLMIX_SRC4 - [6:0] */
2000 * R1623 (0x657) - EQLMIX Input 4 Volume
2002 #define WM2200_EQLMIX_VOL4_MASK 0x00FE /* EQLMIX_VOL4 - [7:1] */
2007 * R1624 (0x658) - EQRMIX Input 1 Source
2009 #define WM2200_EQRMIX_SRC1_MASK 0x007F /* EQRMIX_SRC1 - [6:0] */
2010 #define WM2200_EQRMIX_SRC1_SHIFT 0 /* EQRMIX_SRC1 - [6:0] */
2011 #define WM2200_EQRMIX_SRC1_WIDTH 7 /* EQRMIX_SRC1 - [6:0] */
2014 * R1625 (0x659) - EQRMIX Input 1 Volume
2016 #define WM2200_EQRMIX_VOL1_MASK 0x00FE /* EQRMIX_VOL1 - [7:1] */
2021 * R1626 (0x65A) - EQRMIX Input 2 Source
2023 #define WM2200_EQRMIX_SRC2_MASK 0x007F /* EQRMIX_SRC2 - [6:0] */
2024 #define WM2200_EQRMIX_SRC2_SHIFT 0 /* EQRMIX_SRC2 - [6:0] */
2025 #define WM2200_EQRMIX_SRC2_WIDTH 7 /* EQRMIX_SRC2 - [6:0] */
2028 * R1627 (0x65B) - EQRMIX Input 2 Volume
2030 #define WM2200_EQRMIX_VOL2_MASK 0x00FE /* EQRMIX_VOL2 - [7:1] */
2035 * R1628 (0x65C) - EQRMIX Input 3 Source
2037 #define WM2200_EQRMIX_SRC3_MASK 0x007F /* EQRMIX_SRC3 - [6:0] */
2038 #define WM2200_EQRMIX_SRC3_SHIFT 0 /* EQRMIX_SRC3 - [6:0] */
2039 #define WM2200_EQRMIX_SRC3_WIDTH 7 /* EQRMIX_SRC3 - [6:0] */
2042 * R1629 (0x65D) - EQRMIX Input 3 Volume
2044 #define WM2200_EQRMIX_VOL3_MASK 0x00FE /* EQRMIX_VOL3 - [7:1] */
2049 * R1630 (0x65E) - EQRMIX Input 4 Source
2051 #define WM2200_EQRMIX_SRC4_MASK 0x007F /* EQRMIX_SRC4 - [6:0] */
2052 #define WM2200_EQRMIX_SRC4_SHIFT 0 /* EQRMIX_SRC4 - [6:0] */
2053 #define WM2200_EQRMIX_SRC4_WIDTH 7 /* EQRMIX_SRC4 - [6:0] */
2056 * R1631 (0x65F) - EQRMIX Input 4 Volume
2058 #define WM2200_EQRMIX_VOL4_MASK 0x00FE /* EQRMIX_VOL4 - [7:1] */
2063 * R1632 (0x660) - LHPF1MIX Input 1 Source
2065 #define WM2200_LHPF1MIX_SRC1_MASK 0x007F /* LHPF1MIX_SRC1 - [6:0] */
2066 #define WM2200_LHPF1MIX_SRC1_SHIFT 0 /* LHPF1MIX_SRC1 - [6:0] */
2067 #define WM2200_LHPF1MIX_SRC1_WIDTH 7 /* LHPF1MIX_SRC1 - [6:0] */
2070 * R1633 (0x661) - LHPF1MIX Input 1 Volume
2072 #define WM2200_LHPF1MIX_VOL1_MASK 0x00FE /* LHPF1MIX_VOL1 - [7:1] */
2077 * R1634 (0x662) - LHPF1MIX Input 2 Source
2079 #define WM2200_LHPF1MIX_SRC2_MASK 0x007F /* LHPF1MIX_SRC2 - [6:0] */
2080 #define WM2200_LHPF1MIX_SRC2_SHIFT 0 /* LHPF1MIX_SRC2 - [6:0] */
2081 #define WM2200_LHPF1MIX_SRC2_WIDTH 7 /* LHPF1MIX_SRC2 - [6:0] */
2084 * R1635 (0x663) - LHPF1MIX Input 2 Volume
2086 #define WM2200_LHPF1MIX_VOL2_MASK 0x00FE /* LHPF1MIX_VOL2 - [7:1] */
2091 * R1636 (0x664) - LHPF1MIX Input 3 Source
2093 #define WM2200_LHPF1MIX_SRC3_MASK 0x007F /* LHPF1MIX_SRC3 - [6:0] */
2094 #define WM2200_LHPF1MIX_SRC3_SHIFT 0 /* LHPF1MIX_SRC3 - [6:0] */
2095 #define WM2200_LHPF1MIX_SRC3_WIDTH 7 /* LHPF1MIX_SRC3 - [6:0] */
2098 * R1637 (0x665) - LHPF1MIX Input 3 Volume
2100 #define WM2200_LHPF1MIX_VOL3_MASK 0x00FE /* LHPF1MIX_VOL3 - [7:1] */
2105 * R1638 (0x666) - LHPF1MIX Input 4 Source
2107 #define WM2200_LHPF1MIX_SRC4_MASK 0x007F /* LHPF1MIX_SRC4 - [6:0] */
2108 #define WM2200_LHPF1MIX_SRC4_SHIFT 0 /* LHPF1MIX_SRC4 - [6:0] */
2109 #define WM2200_LHPF1MIX_SRC4_WIDTH 7 /* LHPF1MIX_SRC4 - [6:0] */
2112 * R1639 (0x667) - LHPF1MIX Input 4 Volume
2114 #define WM2200_LHPF1MIX_VOL4_MASK 0x00FE /* LHPF1MIX_VOL4 - [7:1] */
2119 * R1640 (0x668) - LHPF2MIX Input 1 Source
2121 #define WM2200_LHPF2MIX_SRC1_MASK 0x007F /* LHPF2MIX_SRC1 - [6:0] */
2122 #define WM2200_LHPF2MIX_SRC1_SHIFT 0 /* LHPF2MIX_SRC1 - [6:0] */
2123 #define WM2200_LHPF2MIX_SRC1_WIDTH 7 /* LHPF2MIX_SRC1 - [6:0] */
2126 * R1641 (0x669) - LHPF2MIX Input 1 Volume
2128 #define WM2200_LHPF2MIX_VOL1_MASK 0x00FE /* LHPF2MIX_VOL1 - [7:1] */
2133 * R1642 (0x66A) - LHPF2MIX Input 2 Source
2135 #define WM2200_LHPF2MIX_SRC2_MASK 0x007F /* LHPF2MIX_SRC2 - [6:0] */
2136 #define WM2200_LHPF2MIX_SRC2_SHIFT 0 /* LHPF2MIX_SRC2 - [6:0] */
2137 #define WM2200_LHPF2MIX_SRC2_WIDTH 7 /* LHPF2MIX_SRC2 - [6:0] */
2140 * R1643 (0x66B) - LHPF2MIX Input 2 Volume
2142 #define WM2200_LHPF2MIX_VOL2_MASK 0x00FE /* LHPF2MIX_VOL2 - [7:1] */
2147 * R1644 (0x66C) - LHPF2MIX Input 3 Source
2149 #define WM2200_LHPF2MIX_SRC3_MASK 0x007F /* LHPF2MIX_SRC3 - [6:0] */
2150 #define WM2200_LHPF2MIX_SRC3_SHIFT 0 /* LHPF2MIX_SRC3 - [6:0] */
2151 #define WM2200_LHPF2MIX_SRC3_WIDTH 7 /* LHPF2MIX_SRC3 - [6:0] */
2154 * R1645 (0x66D) - LHPF2MIX Input 3 Volume
2156 #define WM2200_LHPF2MIX_VOL3_MASK 0x00FE /* LHPF2MIX_VOL3 - [7:1] */
2161 * R1646 (0x66E) - LHPF2MIX Input 4 Source
2163 #define WM2200_LHPF2MIX_SRC4_MASK 0x007F /* LHPF2MIX_SRC4 - [6:0] */
2164 #define WM2200_LHPF2MIX_SRC4_SHIFT 0 /* LHPF2MIX_SRC4 - [6:0] */
2165 #define WM2200_LHPF2MIX_SRC4_WIDTH 7 /* LHPF2MIX_SRC4 - [6:0] */
2168 * R1647 (0x66F) - LHPF2MIX Input 4 Volume
2170 #define WM2200_LHPF2MIX_VOL4_MASK 0x00FE /* LHPF2MIX_VOL4 - [7:1] */
2175 * R1648 (0x670) - DSP1LMIX Input 1 Source
2177 #define WM2200_DSP1LMIX_SRC1_MASK 0x007F /* DSP1LMIX_SRC1 - [6:0] */
2178 #define WM2200_DSP1LMIX_SRC1_SHIFT 0 /* DSP1LMIX_SRC1 - [6:0] */
2179 #define WM2200_DSP1LMIX_SRC1_WIDTH 7 /* DSP1LMIX_SRC1 - [6:0] */
2182 * R1649 (0x671) - DSP1LMIX Input 1 Volume
2184 #define WM2200_DSP1LMIX_VOL1_MASK 0x00FE /* DSP1LMIX_VOL1 - [7:1] */
2189 * R1650 (0x672) - DSP1LMIX Input 2 Source
2191 #define WM2200_DSP1LMIX_SRC2_MASK 0x007F /* DSP1LMIX_SRC2 - [6:0] */
2192 #define WM2200_DSP1LMIX_SRC2_SHIFT 0 /* DSP1LMIX_SRC2 - [6:0] */
2193 #define WM2200_DSP1LMIX_SRC2_WIDTH 7 /* DSP1LMIX_SRC2 - [6:0] */
2196 * R1651 (0x673) - DSP1LMIX Input 2 Volume
2198 #define WM2200_DSP1LMIX_VOL2_MASK 0x00FE /* DSP1LMIX_VOL2 - [7:1] */
2203 * R1652 (0x674) - DSP1LMIX Input 3 Source
2205 #define WM2200_DSP1LMIX_SRC3_MASK 0x007F /* DSP1LMIX_SRC3 - [6:0] */
2206 #define WM2200_DSP1LMIX_SRC3_SHIFT 0 /* DSP1LMIX_SRC3 - [6:0] */
2207 #define WM2200_DSP1LMIX_SRC3_WIDTH 7 /* DSP1LMIX_SRC3 - [6:0] */
2210 * R1653 (0x675) - DSP1LMIX Input 3 Volume
2212 #define WM2200_DSP1LMIX_VOL3_MASK 0x00FE /* DSP1LMIX_VOL3 - [7:1] */
2217 * R1654 (0x676) - DSP1LMIX Input 4 Source
2219 #define WM2200_DSP1LMIX_SRC4_MASK 0x007F /* DSP1LMIX_SRC4 - [6:0] */
2220 #define WM2200_DSP1LMIX_SRC4_SHIFT 0 /* DSP1LMIX_SRC4 - [6:0] */
2221 #define WM2200_DSP1LMIX_SRC4_WIDTH 7 /* DSP1LMIX_SRC4 - [6:0] */
2224 * R1655 (0x677) - DSP1LMIX Input 4 Volume
2226 #define WM2200_DSP1LMIX_VOL4_MASK 0x00FE /* DSP1LMIX_VOL4 - [7:1] */
2231 * R1656 (0x678) - DSP1RMIX Input 1 Source
2233 #define WM2200_DSP1RMIX_SRC1_MASK 0x007F /* DSP1RMIX_SRC1 - [6:0] */
2234 #define WM2200_DSP1RMIX_SRC1_SHIFT 0 /* DSP1RMIX_SRC1 - [6:0] */
2235 #define WM2200_DSP1RMIX_SRC1_WIDTH 7 /* DSP1RMIX_SRC1 - [6:0] */
2238 * R1657 (0x679) - DSP1RMIX Input 1 Volume
2240 #define WM2200_DSP1RMIX_VOL1_MASK 0x00FE /* DSP1RMIX_VOL1 - [7:1] */
2245 * R1658 (0x67A) - DSP1RMIX Input 2 Source
2247 #define WM2200_DSP1RMIX_SRC2_MASK 0x007F /* DSP1RMIX_SRC2 - [6:0] */
2248 #define WM2200_DSP1RMIX_SRC2_SHIFT 0 /* DSP1RMIX_SRC2 - [6:0] */
2249 #define WM2200_DSP1RMIX_SRC2_WIDTH 7 /* DSP1RMIX_SRC2 - [6:0] */
2252 * R1659 (0x67B) - DSP1RMIX Input 2 Volume
2254 #define WM2200_DSP1RMIX_VOL2_MASK 0x00FE /* DSP1RMIX_VOL2 - [7:1] */
2259 * R1660 (0x67C) - DSP1RMIX Input 3 Source
2261 #define WM2200_DSP1RMIX_SRC3_MASK 0x007F /* DSP1RMIX_SRC3 - [6:0] */
2262 #define WM2200_DSP1RMIX_SRC3_SHIFT 0 /* DSP1RMIX_SRC3 - [6:0] */
2263 #define WM2200_DSP1RMIX_SRC3_WIDTH 7 /* DSP1RMIX_SRC3 - [6:0] */
2266 * R1661 (0x67D) - DSP1RMIX Input 3 Volume
2268 #define WM2200_DSP1RMIX_VOL3_MASK 0x00FE /* DSP1RMIX_VOL3 - [7:1] */
2273 * R1662 (0x67E) - DSP1RMIX Input 4 Source
2275 #define WM2200_DSP1RMIX_SRC4_MASK 0x007F /* DSP1RMIX_SRC4 - [6:0] */
2276 #define WM2200_DSP1RMIX_SRC4_SHIFT 0 /* DSP1RMIX_SRC4 - [6:0] */
2277 #define WM2200_DSP1RMIX_SRC4_WIDTH 7 /* DSP1RMIX_SRC4 - [6:0] */
2280 * R1663 (0x67F) - DSP1RMIX Input 4 Volume
2282 #define WM2200_DSP1RMIX_VOL4_MASK 0x00FE /* DSP1RMIX_VOL4 - [7:1] */
2287 * R1664 (0x680) - DSP1AUX1MIX Input 1 Source
2289 #define WM2200_DSP1AUX1MIX_SRC1_MASK 0x007F /* DSP1AUX1MIX_SRC1 - [6:0] */
2290 #define WM2200_DSP1AUX1MIX_SRC1_SHIFT 0 /* DSP1AUX1MIX_SRC1 - [6:0] */
2291 #define WM2200_DSP1AUX1MIX_SRC1_WIDTH 7 /* DSP1AUX1MIX_SRC1 - [6:0] */
2294 * R1665 (0x681) - DSP1AUX2MIX Input 1 Source
2296 #define WM2200_DSP1AUX2MIX_SRC1_MASK 0x007F /* DSP1AUX2MIX_SRC1 - [6:0] */
2297 #define WM2200_DSP1AUX2MIX_SRC1_SHIFT 0 /* DSP1AUX2MIX_SRC1 - [6:0] */
2298 #define WM2200_DSP1AUX2MIX_SRC1_WIDTH 7 /* DSP1AUX2MIX_SRC1 - [6:0] */
2301 * R1666 (0x682) - DSP1AUX3MIX Input 1 Source
2303 #define WM2200_DSP1AUX3MIX_SRC1_MASK 0x007F /* DSP1AUX3MIX_SRC1 - [6:0] */
2304 #define WM2200_DSP1AUX3MIX_SRC1_SHIFT 0 /* DSP1AUX3MIX_SRC1 - [6:0] */
2305 #define WM2200_DSP1AUX3MIX_SRC1_WIDTH 7 /* DSP1AUX3MIX_SRC1 - [6:0] */
2308 * R1667 (0x683) - DSP1AUX4MIX Input 1 Source
2310 #define WM2200_DSP1AUX4MIX_SRC1_MASK 0x007F /* DSP1AUX4MIX_SRC1 - [6:0] */
2311 #define WM2200_DSP1AUX4MIX_SRC1_SHIFT 0 /* DSP1AUX4MIX_SRC1 - [6:0] */
2312 #define WM2200_DSP1AUX4MIX_SRC1_WIDTH 7 /* DSP1AUX4MIX_SRC1 - [6:0] */
2315 * R1668 (0x684) - DSP1AUX5MIX Input 1 Source
2317 #define WM2200_DSP1AUX5MIX_SRC1_MASK 0x007F /* DSP1AUX5MIX_SRC1 - [6:0] */
2318 #define WM2200_DSP1AUX5MIX_SRC1_SHIFT 0 /* DSP1AUX5MIX_SRC1 - [6:0] */
2319 #define WM2200_DSP1AUX5MIX_SRC1_WIDTH 7 /* DSP1AUX5MIX_SRC1 - [6:0] */
2322 * R1669 (0x685) - DSP1AUX6MIX Input 1 Source
2324 #define WM2200_DSP1AUX6MIX_SRC1_MASK 0x007F /* DSP1AUX6MIX_SRC1 - [6:0] */
2325 #define WM2200_DSP1AUX6MIX_SRC1_SHIFT 0 /* DSP1AUX6MIX_SRC1 - [6:0] */
2326 #define WM2200_DSP1AUX6MIX_SRC1_WIDTH 7 /* DSP1AUX6MIX_SRC1 - [6:0] */
2329 * R1670 (0x686) - DSP2LMIX Input 1 Source
2331 #define WM2200_DSP2LMIX_SRC1_MASK 0x007F /* DSP2LMIX_SRC1 - [6:0] */
2332 #define WM2200_DSP2LMIX_SRC1_SHIFT 0 /* DSP2LMIX_SRC1 - [6:0] */
2333 #define WM2200_DSP2LMIX_SRC1_WIDTH 7 /* DSP2LMIX_SRC1 - [6:0] */
2336 * R1671 (0x687) - DSP2LMIX Input 1 Volume
2338 #define WM2200_DSP2LMIX_VOL1_MASK 0x00FE /* DSP2LMIX_VOL1 - [7:1] */
2343 * R1672 (0x688) - DSP2LMIX Input 2 Source
2345 #define WM2200_DSP2LMIX_SRC2_MASK 0x007F /* DSP2LMIX_SRC2 - [6:0] */
2346 #define WM2200_DSP2LMIX_SRC2_SHIFT 0 /* DSP2LMIX_SRC2 - [6:0] */
2347 #define WM2200_DSP2LMIX_SRC2_WIDTH 7 /* DSP2LMIX_SRC2 - [6:0] */
2350 * R1673 (0x689) - DSP2LMIX Input 2 Volume
2352 #define WM2200_DSP2LMIX_VOL2_MASK 0x00FE /* DSP2LMIX_VOL2 - [7:1] */
2357 * R1674 (0x68A) - DSP2LMIX Input 3 Source
2359 #define WM2200_DSP2LMIX_SRC3_MASK 0x007F /* DSP2LMIX_SRC3 - [6:0] */
2360 #define WM2200_DSP2LMIX_SRC3_SHIFT 0 /* DSP2LMIX_SRC3 - [6:0] */
2361 #define WM2200_DSP2LMIX_SRC3_WIDTH 7 /* DSP2LMIX_SRC3 - [6:0] */
2364 * R1675 (0x68B) - DSP2LMIX Input 3 Volume
2366 #define WM2200_DSP2LMIX_VOL3_MASK 0x00FE /* DSP2LMIX_VOL3 - [7:1] */
2371 * R1676 (0x68C) - DSP2LMIX Input 4 Source
2373 #define WM2200_DSP2LMIX_SRC4_MASK 0x007F /* DSP2LMIX_SRC4 - [6:0] */
2374 #define WM2200_DSP2LMIX_SRC4_SHIFT 0 /* DSP2LMIX_SRC4 - [6:0] */
2375 #define WM2200_DSP2LMIX_SRC4_WIDTH 7 /* DSP2LMIX_SRC4 - [6:0] */
2378 * R1677 (0x68D) - DSP2LMIX Input 4 Volume
2380 #define WM2200_DSP2LMIX_VOL4_MASK 0x00FE /* DSP2LMIX_VOL4 - [7:1] */
2385 * R1678 (0x68E) - DSP2RMIX Input 1 Source
2387 #define WM2200_DSP2RMIX_SRC1_MASK 0x007F /* DSP2RMIX_SRC1 - [6:0] */
2388 #define WM2200_DSP2RMIX_SRC1_SHIFT 0 /* DSP2RMIX_SRC1 - [6:0] */
2389 #define WM2200_DSP2RMIX_SRC1_WIDTH 7 /* DSP2RMIX_SRC1 - [6:0] */
2392 * R1679 (0x68F) - DSP2RMIX Input 1 Volume
2394 #define WM2200_DSP2RMIX_VOL1_MASK 0x00FE /* DSP2RMIX_VOL1 - [7:1] */
2399 * R1680 (0x690) - DSP2RMIX Input 2 Source
2401 #define WM2200_DSP2RMIX_SRC2_MASK 0x007F /* DSP2RMIX_SRC2 - [6:0] */
2402 #define WM2200_DSP2RMIX_SRC2_SHIFT 0 /* DSP2RMIX_SRC2 - [6:0] */
2403 #define WM2200_DSP2RMIX_SRC2_WIDTH 7 /* DSP2RMIX_SRC2 - [6:0] */
2406 * R1681 (0x691) - DSP2RMIX Input 2 Volume
2408 #define WM2200_DSP2RMIX_VOL2_MASK 0x00FE /* DSP2RMIX_VOL2 - [7:1] */
2413 * R1682 (0x692) - DSP2RMIX Input 3 Source
2415 #define WM2200_DSP2RMIX_SRC3_MASK 0x007F /* DSP2RMIX_SRC3 - [6:0] */
2416 #define WM2200_DSP2RMIX_SRC3_SHIFT 0 /* DSP2RMIX_SRC3 - [6:0] */
2417 #define WM2200_DSP2RMIX_SRC3_WIDTH 7 /* DSP2RMIX_SRC3 - [6:0] */
2420 * R1683 (0x693) - DSP2RMIX Input 3 Volume
2422 #define WM2200_DSP2RMIX_VOL3_MASK 0x00FE /* DSP2RMIX_VOL3 - [7:1] */
2427 * R1684 (0x694) - DSP2RMIX Input 4 Source
2429 #define WM2200_DSP2RMIX_SRC4_MASK 0x007F /* DSP2RMIX_SRC4 - [6:0] */
2430 #define WM2200_DSP2RMIX_SRC4_SHIFT 0 /* DSP2RMIX_SRC4 - [6:0] */
2431 #define WM2200_DSP2RMIX_SRC4_WIDTH 7 /* DSP2RMIX_SRC4 - [6:0] */
2434 * R1685 (0x695) - DSP2RMIX Input 4 Volume
2436 #define WM2200_DSP2RMIX_VOL4_MASK 0x00FE /* DSP2RMIX_VOL4 - [7:1] */
2441 * R1686 (0x696) - DSP2AUX1MIX Input 1 Source
2443 #define WM2200_DSP2AUX1MIX_SRC1_MASK 0x007F /* DSP2AUX1MIX_SRC1 - [6:0] */
2444 #define WM2200_DSP2AUX1MIX_SRC1_SHIFT 0 /* DSP2AUX1MIX_SRC1 - [6:0] */
2445 #define WM2200_DSP2AUX1MIX_SRC1_WIDTH 7 /* DSP2AUX1MIX_SRC1 - [6:0] */
2448 * R1687 (0x697) - DSP2AUX2MIX Input 1 Source
2450 #define WM2200_DSP2AUX2MIX_SRC1_MASK 0x007F /* DSP2AUX2MIX_SRC1 - [6:0] */
2451 #define WM2200_DSP2AUX2MIX_SRC1_SHIFT 0 /* DSP2AUX2MIX_SRC1 - [6:0] */
2452 #define WM2200_DSP2AUX2MIX_SRC1_WIDTH 7 /* DSP2AUX2MIX_SRC1 - [6:0] */
2455 * R1688 (0x698) - DSP2AUX3MIX Input 1 Source
2457 #define WM2200_DSP2AUX3MIX_SRC1_MASK 0x007F /* DSP2AUX3MIX_SRC1 - [6:0] */
2458 #define WM2200_DSP2AUX3MIX_SRC1_SHIFT 0 /* DSP2AUX3MIX_SRC1 - [6:0] */
2459 #define WM2200_DSP2AUX3MIX_SRC1_WIDTH 7 /* DSP2AUX3MIX_SRC1 - [6:0] */
2462 * R1689 (0x699) - DSP2AUX4MIX Input 1 Source
2464 #define WM2200_DSP2AUX4MIX_SRC1_MASK 0x007F /* DSP2AUX4MIX_SRC1 - [6:0] */
2465 #define WM2200_DSP2AUX4MIX_SRC1_SHIFT 0 /* DSP2AUX4MIX_SRC1 - [6:0] */
2466 #define WM2200_DSP2AUX4MIX_SRC1_WIDTH 7 /* DSP2AUX4MIX_SRC1 - [6:0] */
2469 * R1690 (0x69A) - DSP2AUX5MIX Input 1 Source
2471 #define WM2200_DSP2AUX5MIX_SRC1_MASK 0x007F /* DSP2AUX5MIX_SRC1 - [6:0] */
2472 #define WM2200_DSP2AUX5MIX_SRC1_SHIFT 0 /* DSP2AUX5MIX_SRC1 - [6:0] */
2473 #define WM2200_DSP2AUX5MIX_SRC1_WIDTH 7 /* DSP2AUX5MIX_SRC1 - [6:0] */
2476 * R1691 (0x69B) - DSP2AUX6MIX Input 1 Source
2478 #define WM2200_DSP2AUX6MIX_SRC1_MASK 0x007F /* DSP2AUX6MIX_SRC1 - [6:0] */
2479 #define WM2200_DSP2AUX6MIX_SRC1_SHIFT 0 /* DSP2AUX6MIX_SRC1 - [6:0] */
2480 #define WM2200_DSP2AUX6MIX_SRC1_WIDTH 7 /* DSP2AUX6MIX_SRC1 - [6:0] */
2483 * R1792 (0x700) - GPIO CTRL 1
2485 #define WM2200_GP1_DIR 0x8000 /* GP1_DIR */
2486 #define WM2200_GP1_DIR_MASK 0x8000 /* GP1_DIR */
2489 #define WM2200_GP1_PU 0x4000 /* GP1_PU */
2490 #define WM2200_GP1_PU_MASK 0x4000 /* GP1_PU */
2493 #define WM2200_GP1_PD 0x2000 /* GP1_PD */
2494 #define WM2200_GP1_PD_MASK 0x2000 /* GP1_PD */
2497 #define WM2200_GP1_POL 0x0400 /* GP1_POL */
2498 #define WM2200_GP1_POL_MASK 0x0400 /* GP1_POL */
2501 #define WM2200_GP1_OP_CFG 0x0200 /* GP1_OP_CFG */
2502 #define WM2200_GP1_OP_CFG_MASK 0x0200 /* GP1_OP_CFG */
2505 #define WM2200_GP1_DB 0x0100 /* GP1_DB */
2506 #define WM2200_GP1_DB_MASK 0x0100 /* GP1_DB */
2509 #define WM2200_GP1_LVL 0x0040 /* GP1_LVL */
2510 #define WM2200_GP1_LVL_MASK 0x0040 /* GP1_LVL */
2513 #define WM2200_GP1_FN_MASK 0x003F /* GP1_FN - [5:0] */
2514 #define WM2200_GP1_FN_SHIFT 0 /* GP1_FN - [5:0] */
2515 #define WM2200_GP1_FN_WIDTH 6 /* GP1_FN - [5:0] */
2518 * R1793 (0x701) - GPIO CTRL 2
2520 #define WM2200_GP2_DIR 0x8000 /* GP2_DIR */
2521 #define WM2200_GP2_DIR_MASK 0x8000 /* GP2_DIR */
2524 #define WM2200_GP2_PU 0x4000 /* GP2_PU */
2525 #define WM2200_GP2_PU_MASK 0x4000 /* GP2_PU */
2528 #define WM2200_GP2_PD 0x2000 /* GP2_PD */
2529 #define WM2200_GP2_PD_MASK 0x2000 /* GP2_PD */
2532 #define WM2200_GP2_POL 0x0400 /* GP2_POL */
2533 #define WM2200_GP2_POL_MASK 0x0400 /* GP2_POL */
2536 #define WM2200_GP2_OP_CFG 0x0200 /* GP2_OP_CFG */
2537 #define WM2200_GP2_OP_CFG_MASK 0x0200 /* GP2_OP_CFG */
2540 #define WM2200_GP2_DB 0x0100 /* GP2_DB */
2541 #define WM2200_GP2_DB_MASK 0x0100 /* GP2_DB */
2544 #define WM2200_GP2_LVL 0x0040 /* GP2_LVL */
2545 #define WM2200_GP2_LVL_MASK 0x0040 /* GP2_LVL */
2548 #define WM2200_GP2_FN_MASK 0x003F /* GP2_FN - [5:0] */
2549 #define WM2200_GP2_FN_SHIFT 0 /* GP2_FN - [5:0] */
2550 #define WM2200_GP2_FN_WIDTH 6 /* GP2_FN - [5:0] */
2553 * R1794 (0x702) - GPIO CTRL 3
2555 #define WM2200_GP3_DIR 0x8000 /* GP3_DIR */
2556 #define WM2200_GP3_DIR_MASK 0x8000 /* GP3_DIR */
2559 #define WM2200_GP3_PU 0x4000 /* GP3_PU */
2560 #define WM2200_GP3_PU_MASK 0x4000 /* GP3_PU */
2563 #define WM2200_GP3_PD 0x2000 /* GP3_PD */
2564 #define WM2200_GP3_PD_MASK 0x2000 /* GP3_PD */
2567 #define WM2200_GP3_POL 0x0400 /* GP3_POL */
2568 #define WM2200_GP3_POL_MASK 0x0400 /* GP3_POL */
2571 #define WM2200_GP3_OP_CFG 0x0200 /* GP3_OP_CFG */
2572 #define WM2200_GP3_OP_CFG_MASK 0x0200 /* GP3_OP_CFG */
2575 #define WM2200_GP3_DB 0x0100 /* GP3_DB */
2576 #define WM2200_GP3_DB_MASK 0x0100 /* GP3_DB */
2579 #define WM2200_GP3_LVL 0x0040 /* GP3_LVL */
2580 #define WM2200_GP3_LVL_MASK 0x0040 /* GP3_LVL */
2583 #define WM2200_GP3_FN_MASK 0x003F /* GP3_FN - [5:0] */
2584 #define WM2200_GP3_FN_SHIFT 0 /* GP3_FN - [5:0] */
2585 #define WM2200_GP3_FN_WIDTH 6 /* GP3_FN - [5:0] */
2588 * R1795 (0x703) - GPIO CTRL 4
2590 #define WM2200_GP4_DIR 0x8000 /* GP4_DIR */
2591 #define WM2200_GP4_DIR_MASK 0x8000 /* GP4_DIR */
2594 #define WM2200_GP4_PU 0x4000 /* GP4_PU */
2595 #define WM2200_GP4_PU_MASK 0x4000 /* GP4_PU */
2598 #define WM2200_GP4_PD 0x2000 /* GP4_PD */
2599 #define WM2200_GP4_PD_MASK 0x2000 /* GP4_PD */
2602 #define WM2200_GP4_POL 0x0400 /* GP4_POL */
2603 #define WM2200_GP4_POL_MASK 0x0400 /* GP4_POL */
2606 #define WM2200_GP4_OP_CFG 0x0200 /* GP4_OP_CFG */
2607 #define WM2200_GP4_OP_CFG_MASK 0x0200 /* GP4_OP_CFG */
2610 #define WM2200_GP4_DB 0x0100 /* GP4_DB */
2611 #define WM2200_GP4_DB_MASK 0x0100 /* GP4_DB */
2614 #define WM2200_GP4_LVL 0x0040 /* GP4_LVL */
2615 #define WM2200_GP4_LVL_MASK 0x0040 /* GP4_LVL */
2618 #define WM2200_GP4_FN_MASK 0x003F /* GP4_FN - [5:0] */
2619 #define WM2200_GP4_FN_SHIFT 0 /* GP4_FN - [5:0] */
2620 #define WM2200_GP4_FN_WIDTH 6 /* GP4_FN - [5:0] */
2623 * R1799 (0x707) - ADPS1 IRQ0
2625 #define WM2200_DSP_IRQ1 0x0002 /* DSP_IRQ1 */
2626 #define WM2200_DSP_IRQ1_MASK 0x0002 /* DSP_IRQ1 */
2629 #define WM2200_DSP_IRQ0 0x0001 /* DSP_IRQ0 */
2630 #define WM2200_DSP_IRQ0_MASK 0x0001 /* DSP_IRQ0 */
2631 #define WM2200_DSP_IRQ0_SHIFT 0 /* DSP_IRQ0 */
2635 * R1800 (0x708) - ADPS1 IRQ1
2637 #define WM2200_DSP_IRQ3 0x0002 /* DSP_IRQ3 */
2638 #define WM2200_DSP_IRQ3_MASK 0x0002 /* DSP_IRQ3 */
2641 #define WM2200_DSP_IRQ2 0x0001 /* DSP_IRQ2 */
2642 #define WM2200_DSP_IRQ2_MASK 0x0001 /* DSP_IRQ2 */
2643 #define WM2200_DSP_IRQ2_SHIFT 0 /* DSP_IRQ2 */
2647 * R1801 (0x709) - Misc Pad Ctrl 1
2649 #define WM2200_LDO1ENA_PD 0x8000 /* LDO1ENA_PD */
2650 #define WM2200_LDO1ENA_PD_MASK 0x8000 /* LDO1ENA_PD */
2653 #define WM2200_MCLK2_PD 0x2000 /* MCLK2_PD */
2654 #define WM2200_MCLK2_PD_MASK 0x2000 /* MCLK2_PD */
2657 #define WM2200_MCLK1_PD 0x1000 /* MCLK1_PD */
2658 #define WM2200_MCLK1_PD_MASK 0x1000 /* MCLK1_PD */
2661 #define WM2200_DACLRCLK1_PU 0x0400 /* DACLRCLK1_PU */
2662 #define WM2200_DACLRCLK1_PU_MASK 0x0400 /* DACLRCLK1_PU */
2665 #define WM2200_DACLRCLK1_PD 0x0200 /* DACLRCLK1_PD */
2666 #define WM2200_DACLRCLK1_PD_MASK 0x0200 /* DACLRCLK1_PD */
2669 #define WM2200_BCLK1_PU 0x0100 /* BCLK1_PU */
2670 #define WM2200_BCLK1_PU_MASK 0x0100 /* BCLK1_PU */
2673 #define WM2200_BCLK1_PD 0x0080 /* BCLK1_PD */
2674 #define WM2200_BCLK1_PD_MASK 0x0080 /* BCLK1_PD */
2677 #define WM2200_DACDAT1_PU 0x0040 /* DACDAT1_PU */
2678 #define WM2200_DACDAT1_PU_MASK 0x0040 /* DACDAT1_PU */
2681 #define WM2200_DACDAT1_PD 0x0020 /* DACDAT1_PD */
2682 #define WM2200_DACDAT1_PD_MASK 0x0020 /* DACDAT1_PD */
2685 #define WM2200_DMICDAT3_PD 0x0010 /* DMICDAT3_PD */
2686 #define WM2200_DMICDAT3_PD_MASK 0x0010 /* DMICDAT3_PD */
2689 #define WM2200_DMICDAT2_PD 0x0008 /* DMICDAT2_PD */
2690 #define WM2200_DMICDAT2_PD_MASK 0x0008 /* DMICDAT2_PD */
2693 #define WM2200_DMICDAT1_PD 0x0004 /* DMICDAT1_PD */
2694 #define WM2200_DMICDAT1_PD_MASK 0x0004 /* DMICDAT1_PD */
2697 #define WM2200_RSTB_PU 0x0002 /* RSTB_PU */
2698 #define WM2200_RSTB_PU_MASK 0x0002 /* RSTB_PU */
2701 #define WM2200_ADDR_PD 0x0001 /* ADDR_PD */
2702 #define WM2200_ADDR_PD_MASK 0x0001 /* ADDR_PD */
2703 #define WM2200_ADDR_PD_SHIFT 0 /* ADDR_PD */
2707 * R2048 (0x800) - Interrupt Status 1
2709 #define WM2200_DSP_IRQ0_EINT 0x0080 /* DSP_IRQ0_EINT */
2710 #define WM2200_DSP_IRQ0_EINT_MASK 0x0080 /* DSP_IRQ0_EINT */
2713 #define WM2200_DSP_IRQ1_EINT 0x0040 /* DSP_IRQ1_EINT */
2714 #define WM2200_DSP_IRQ1_EINT_MASK 0x0040 /* DSP_IRQ1_EINT */
2717 #define WM2200_DSP_IRQ2_EINT 0x0020 /* DSP_IRQ2_EINT */
2718 #define WM2200_DSP_IRQ2_EINT_MASK 0x0020 /* DSP_IRQ2_EINT */
2721 #define WM2200_DSP_IRQ3_EINT 0x0010 /* DSP_IRQ3_EINT */
2722 #define WM2200_DSP_IRQ3_EINT_MASK 0x0010 /* DSP_IRQ3_EINT */
2725 #define WM2200_GP4_EINT 0x0008 /* GP4_EINT */
2726 #define WM2200_GP4_EINT_MASK 0x0008 /* GP4_EINT */
2729 #define WM2200_GP3_EINT 0x0004 /* GP3_EINT */
2730 #define WM2200_GP3_EINT_MASK 0x0004 /* GP3_EINT */
2733 #define WM2200_GP2_EINT 0x0002 /* GP2_EINT */
2734 #define WM2200_GP2_EINT_MASK 0x0002 /* GP2_EINT */
2737 #define WM2200_GP1_EINT 0x0001 /* GP1_EINT */
2738 #define WM2200_GP1_EINT_MASK 0x0001 /* GP1_EINT */
2739 #define WM2200_GP1_EINT_SHIFT 0 /* GP1_EINT */
2743 * R2049 (0x801) - Interrupt Status 1 Mask
2745 #define WM2200_IM_DSP_IRQ0_EINT 0x0080 /* IM_DSP_IRQ0_EINT */
2746 #define WM2200_IM_DSP_IRQ0_EINT_MASK 0x0080 /* IM_DSP_IRQ0_EINT */
2749 #define WM2200_IM_DSP_IRQ1_EINT 0x0040 /* IM_DSP_IRQ1_EINT */
2750 #define WM2200_IM_DSP_IRQ1_EINT_MASK 0x0040 /* IM_DSP_IRQ1_EINT */
2753 #define WM2200_IM_DSP_IRQ2_EINT 0x0020 /* IM_DSP_IRQ2_EINT */
2754 #define WM2200_IM_DSP_IRQ2_EINT_MASK 0x0020 /* IM_DSP_IRQ2_EINT */
2757 #define WM2200_IM_DSP_IRQ3_EINT 0x0010 /* IM_DSP_IRQ3_EINT */
2758 #define WM2200_IM_DSP_IRQ3_EINT_MASK 0x0010 /* IM_DSP_IRQ3_EINT */
2761 #define WM2200_IM_GP4_EINT 0x0008 /* IM_GP4_EINT */
2762 #define WM2200_IM_GP4_EINT_MASK 0x0008 /* IM_GP4_EINT */
2765 #define WM2200_IM_GP3_EINT 0x0004 /* IM_GP3_EINT */
2766 #define WM2200_IM_GP3_EINT_MASK 0x0004 /* IM_GP3_EINT */
2769 #define WM2200_IM_GP2_EINT 0x0002 /* IM_GP2_EINT */
2770 #define WM2200_IM_GP2_EINT_MASK 0x0002 /* IM_GP2_EINT */
2773 #define WM2200_IM_GP1_EINT 0x0001 /* IM_GP1_EINT */
2774 #define WM2200_IM_GP1_EINT_MASK 0x0001 /* IM_GP1_EINT */
2775 #define WM2200_IM_GP1_EINT_SHIFT 0 /* IM_GP1_EINT */
2779 * R2050 (0x802) - Interrupt Status 2
2781 #define WM2200_WSEQ_BUSY_EINT 0x0100 /* WSEQ_BUSY_EINT */
2782 #define WM2200_WSEQ_BUSY_EINT_MASK 0x0100 /* WSEQ_BUSY_EINT */
2785 #define WM2200_FLL_LOCK_EINT 0x0002 /* FLL_LOCK_EINT */
2786 #define WM2200_FLL_LOCK_EINT_MASK 0x0002 /* FLL_LOCK_EINT */
2789 #define WM2200_CLKGEN_EINT 0x0001 /* CLKGEN_EINT */
2790 #define WM2200_CLKGEN_EINT_MASK 0x0001 /* CLKGEN_EINT */
2791 #define WM2200_CLKGEN_EINT_SHIFT 0 /* CLKGEN_EINT */
2795 * R2051 (0x803) - Interrupt Raw Status 2
2797 #define WM2200_WSEQ_BUSY_STS 0x0100 /* WSEQ_BUSY_STS */
2798 #define WM2200_WSEQ_BUSY_STS_MASK 0x0100 /* WSEQ_BUSY_STS */
2801 #define WM2200_FLL_LOCK_STS 0x0002 /* FLL_LOCK_STS */
2802 #define WM2200_FLL_LOCK_STS_MASK 0x0002 /* FLL_LOCK_STS */
2805 #define WM2200_CLKGEN_STS 0x0001 /* CLKGEN_STS */
2806 #define WM2200_CLKGEN_STS_MASK 0x0001 /* CLKGEN_STS */
2807 #define WM2200_CLKGEN_STS_SHIFT 0 /* CLKGEN_STS */
2811 * R2052 (0x804) - Interrupt Status 2 Mask
2813 #define WM2200_IM_WSEQ_BUSY_EINT 0x0100 /* IM_WSEQ_BUSY_EINT */
2814 #define WM2200_IM_WSEQ_BUSY_EINT_MASK 0x0100 /* IM_WSEQ_BUSY_EINT */
2817 #define WM2200_IM_FLL_LOCK_EINT 0x0002 /* IM_FLL_LOCK_EINT */
2818 #define WM2200_IM_FLL_LOCK_EINT_MASK 0x0002 /* IM_FLL_LOCK_EINT */
2821 #define WM2200_IM_CLKGEN_EINT 0x0001 /* IM_CLKGEN_EINT */
2822 #define WM2200_IM_CLKGEN_EINT_MASK 0x0001 /* IM_CLKGEN_EINT */
2823 #define WM2200_IM_CLKGEN_EINT_SHIFT 0 /* IM_CLKGEN_EINT */
2827 * R2056 (0x808) - Interrupt Control
2829 #define WM2200_IM_IRQ 0x0001 /* IM_IRQ */
2830 #define WM2200_IM_IRQ_MASK 0x0001 /* IM_IRQ */
2831 #define WM2200_IM_IRQ_SHIFT 0 /* IM_IRQ */
2835 * R2304 (0x900) - EQL_1
2837 #define WM2200_EQL_B1_GAIN_MASK 0xF800 /* EQL_B1_GAIN - [15:11] */
2840 #define WM2200_EQL_B2_GAIN_MASK 0x07C0 /* EQL_B2_GAIN - [10:6] */
2843 #define WM2200_EQL_B3_GAIN_MASK 0x003E /* EQL_B3_GAIN - [5:1] */
2846 #define WM2200_EQL_ENA 0x0001 /* EQL_ENA */
2847 #define WM2200_EQL_ENA_MASK 0x0001 /* EQL_ENA */
2848 #define WM2200_EQL_ENA_SHIFT 0 /* EQL_ENA */
2852 * R2305 (0x901) - EQL_2
2854 #define WM2200_EQL_B4_GAIN_MASK 0xF800 /* EQL_B4_GAIN - [15:11] */
2857 #define WM2200_EQL_B5_GAIN_MASK 0x07C0 /* EQL_B5_GAIN - [10:6] */
2862 * R2306 (0x902) - EQL_3
2864 #define WM2200_EQL_B1_A_MASK 0xFFFF /* EQL_B1_A - [15:0] */
2865 #define WM2200_EQL_B1_A_SHIFT 0 /* EQL_B1_A - [15:0] */
2866 #define WM2200_EQL_B1_A_WIDTH 16 /* EQL_B1_A - [15:0] */
2869 * R2307 (0x903) - EQL_4
2871 #define WM2200_EQL_B1_B_MASK 0xFFFF /* EQL_B1_B - [15:0] */
2872 #define WM2200_EQL_B1_B_SHIFT 0 /* EQL_B1_B - [15:0] */
2873 #define WM2200_EQL_B1_B_WIDTH 16 /* EQL_B1_B - [15:0] */
2876 * R2308 (0x904) - EQL_5
2878 #define WM2200_EQL_B1_PG_MASK 0xFFFF /* EQL_B1_PG - [15:0] */
2879 #define WM2200_EQL_B1_PG_SHIFT 0 /* EQL_B1_PG - [15:0] */
2880 #define WM2200_EQL_B1_PG_WIDTH 16 /* EQL_B1_PG - [15:0] */
2883 * R2309 (0x905) - EQL_6
2885 #define WM2200_EQL_B2_A_MASK 0xFFFF /* EQL_B2_A - [15:0] */
2886 #define WM2200_EQL_B2_A_SHIFT 0 /* EQL_B2_A - [15:0] */
2887 #define WM2200_EQL_B2_A_WIDTH 16 /* EQL_B2_A - [15:0] */
2890 * R2310 (0x906) - EQL_7
2892 #define WM2200_EQL_B2_B_MASK 0xFFFF /* EQL_B2_B - [15:0] */
2893 #define WM2200_EQL_B2_B_SHIFT 0 /* EQL_B2_B - [15:0] */
2894 #define WM2200_EQL_B2_B_WIDTH 16 /* EQL_B2_B - [15:0] */
2897 * R2311 (0x907) - EQL_8
2899 #define WM2200_EQL_B2_C_MASK 0xFFFF /* EQL_B2_C - [15:0] */
2900 #define WM2200_EQL_B2_C_SHIFT 0 /* EQL_B2_C - [15:0] */
2901 #define WM2200_EQL_B2_C_WIDTH 16 /* EQL_B2_C - [15:0] */
2904 * R2312 (0x908) - EQL_9
2906 #define WM2200_EQL_B2_PG_MASK 0xFFFF /* EQL_B2_PG - [15:0] */
2907 #define WM2200_EQL_B2_PG_SHIFT 0 /* EQL_B2_PG - [15:0] */
2908 #define WM2200_EQL_B2_PG_WIDTH 16 /* EQL_B2_PG - [15:0] */
2911 * R2313 (0x909) - EQL_10
2913 #define WM2200_EQL_B3_A_MASK 0xFFFF /* EQL_B3_A - [15:0] */
2914 #define WM2200_EQL_B3_A_SHIFT 0 /* EQL_B3_A - [15:0] */
2915 #define WM2200_EQL_B3_A_WIDTH 16 /* EQL_B3_A - [15:0] */
2918 * R2314 (0x90A) - EQL_11
2920 #define WM2200_EQL_B3_B_MASK 0xFFFF /* EQL_B3_B - [15:0] */
2921 #define WM2200_EQL_B3_B_SHIFT 0 /* EQL_B3_B - [15:0] */
2922 #define WM2200_EQL_B3_B_WIDTH 16 /* EQL_B3_B - [15:0] */
2925 * R2315 (0x90B) - EQL_12
2927 #define WM2200_EQL_B3_C_MASK 0xFFFF /* EQL_B3_C - [15:0] */
2928 #define WM2200_EQL_B3_C_SHIFT 0 /* EQL_B3_C - [15:0] */
2929 #define WM2200_EQL_B3_C_WIDTH 16 /* EQL_B3_C - [15:0] */
2932 * R2316 (0x90C) - EQL_13
2934 #define WM2200_EQL_B3_PG_MASK 0xFFFF /* EQL_B3_PG - [15:0] */
2935 #define WM2200_EQL_B3_PG_SHIFT 0 /* EQL_B3_PG - [15:0] */
2936 #define WM2200_EQL_B3_PG_WIDTH 16 /* EQL_B3_PG - [15:0] */
2939 * R2317 (0x90D) - EQL_14
2941 #define WM2200_EQL_B4_A_MASK 0xFFFF /* EQL_B4_A - [15:0] */
2942 #define WM2200_EQL_B4_A_SHIFT 0 /* EQL_B4_A - [15:0] */
2943 #define WM2200_EQL_B4_A_WIDTH 16 /* EQL_B4_A - [15:0] */
2946 * R2318 (0x90E) - EQL_15
2948 #define WM2200_EQL_B4_B_MASK 0xFFFF /* EQL_B4_B - [15:0] */
2949 #define WM2200_EQL_B4_B_SHIFT 0 /* EQL_B4_B - [15:0] */
2950 #define WM2200_EQL_B4_B_WIDTH 16 /* EQL_B4_B - [15:0] */
2953 * R2319 (0x90F) - EQL_16
2955 #define WM2200_EQL_B4_C_MASK 0xFFFF /* EQL_B4_C - [15:0] */
2956 #define WM2200_EQL_B4_C_SHIFT 0 /* EQL_B4_C - [15:0] */
2957 #define WM2200_EQL_B4_C_WIDTH 16 /* EQL_B4_C - [15:0] */
2960 * R2320 (0x910) - EQL_17
2962 #define WM2200_EQL_B4_PG_MASK 0xFFFF /* EQL_B4_PG - [15:0] */
2963 #define WM2200_EQL_B4_PG_SHIFT 0 /* EQL_B4_PG - [15:0] */
2964 #define WM2200_EQL_B4_PG_WIDTH 16 /* EQL_B4_PG - [15:0] */
2967 * R2321 (0x911) - EQL_18
2969 #define WM2200_EQL_B5_A_MASK 0xFFFF /* EQL_B5_A - [15:0] */
2970 #define WM2200_EQL_B5_A_SHIFT 0 /* EQL_B5_A - [15:0] */
2971 #define WM2200_EQL_B5_A_WIDTH 16 /* EQL_B5_A - [15:0] */
2974 * R2322 (0x912) - EQL_19
2976 #define WM2200_EQL_B5_B_MASK 0xFFFF /* EQL_B5_B - [15:0] */
2977 #define WM2200_EQL_B5_B_SHIFT 0 /* EQL_B5_B - [15:0] */
2978 #define WM2200_EQL_B5_B_WIDTH 16 /* EQL_B5_B - [15:0] */
2981 * R2323 (0x913) - EQL_20
2983 #define WM2200_EQL_B5_PG_MASK 0xFFFF /* EQL_B5_PG - [15:0] */
2984 #define WM2200_EQL_B5_PG_SHIFT 0 /* EQL_B5_PG - [15:0] */
2985 #define WM2200_EQL_B5_PG_WIDTH 16 /* EQL_B5_PG - [15:0] */
2988 * R2326 (0x916) - EQR_1
2990 #define WM2200_EQR_B1_GAIN_MASK 0xF800 /* EQR_B1_GAIN - [15:11] */
2993 #define WM2200_EQR_B2_GAIN_MASK 0x07C0 /* EQR_B2_GAIN - [10:6] */
2996 #define WM2200_EQR_B3_GAIN_MASK 0x003E /* EQR_B3_GAIN - [5:1] */
2999 #define WM2200_EQR_ENA 0x0001 /* EQR_ENA */
3000 #define WM2200_EQR_ENA_MASK 0x0001 /* EQR_ENA */
3001 #define WM2200_EQR_ENA_SHIFT 0 /* EQR_ENA */
3005 * R2327 (0x917) - EQR_2
3007 #define WM2200_EQR_B4_GAIN_MASK 0xF800 /* EQR_B4_GAIN - [15:11] */
3010 #define WM2200_EQR_B5_GAIN_MASK 0x07C0 /* EQR_B5_GAIN - [10:6] */
3015 * R2328 (0x918) - EQR_3
3017 #define WM2200_EQR_B1_A_MASK 0xFFFF /* EQR_B1_A - [15:0] */
3018 #define WM2200_EQR_B1_A_SHIFT 0 /* EQR_B1_A - [15:0] */
3019 #define WM2200_EQR_B1_A_WIDTH 16 /* EQR_B1_A - [15:0] */
3022 * R2329 (0x919) - EQR_4
3024 #define WM2200_EQR_B1_B_MASK 0xFFFF /* EQR_B1_B - [15:0] */
3025 #define WM2200_EQR_B1_B_SHIFT 0 /* EQR_B1_B - [15:0] */
3026 #define WM2200_EQR_B1_B_WIDTH 16 /* EQR_B1_B - [15:0] */
3029 * R2330 (0x91A) - EQR_5
3031 #define WM2200_EQR_B1_PG_MASK 0xFFFF /* EQR_B1_PG - [15:0] */
3032 #define WM2200_EQR_B1_PG_SHIFT 0 /* EQR_B1_PG - [15:0] */
3033 #define WM2200_EQR_B1_PG_WIDTH 16 /* EQR_B1_PG - [15:0] */
3036 * R2331 (0x91B) - EQR_6
3038 #define WM2200_EQR_B2_A_MASK 0xFFFF /* EQR_B2_A - [15:0] */
3039 #define WM2200_EQR_B2_A_SHIFT 0 /* EQR_B2_A - [15:0] */
3040 #define WM2200_EQR_B2_A_WIDTH 16 /* EQR_B2_A - [15:0] */
3043 * R2332 (0x91C) - EQR_7
3045 #define WM2200_EQR_B2_B_MASK 0xFFFF /* EQR_B2_B - [15:0] */
3046 #define WM2200_EQR_B2_B_SHIFT 0 /* EQR_B2_B - [15:0] */
3047 #define WM2200_EQR_B2_B_WIDTH 16 /* EQR_B2_B - [15:0] */
3050 * R2333 (0x91D) - EQR_8
3052 #define WM2200_EQR_B2_C_MASK 0xFFFF /* EQR_B2_C - [15:0] */
3053 #define WM2200_EQR_B2_C_SHIFT 0 /* EQR_B2_C - [15:0] */
3054 #define WM2200_EQR_B2_C_WIDTH 16 /* EQR_B2_C - [15:0] */
3057 * R2334 (0x91E) - EQR_9
3059 #define WM2200_EQR_B2_PG_MASK 0xFFFF /* EQR_B2_PG - [15:0] */
3060 #define WM2200_EQR_B2_PG_SHIFT 0 /* EQR_B2_PG - [15:0] */
3061 #define WM2200_EQR_B2_PG_WIDTH 16 /* EQR_B2_PG - [15:0] */
3064 * R2335 (0x91F) - EQR_10
3066 #define WM2200_EQR_B3_A_MASK 0xFFFF /* EQR_B3_A - [15:0] */
3067 #define WM2200_EQR_B3_A_SHIFT 0 /* EQR_B3_A - [15:0] */
3068 #define WM2200_EQR_B3_A_WIDTH 16 /* EQR_B3_A - [15:0] */
3071 * R2336 (0x920) - EQR_11
3073 #define WM2200_EQR_B3_B_MASK 0xFFFF /* EQR_B3_B - [15:0] */
3074 #define WM2200_EQR_B3_B_SHIFT 0 /* EQR_B3_B - [15:0] */
3075 #define WM2200_EQR_B3_B_WIDTH 16 /* EQR_B3_B - [15:0] */
3078 * R2337 (0x921) - EQR_12
3080 #define WM2200_EQR_B3_C_MASK 0xFFFF /* EQR_B3_C - [15:0] */
3081 #define WM2200_EQR_B3_C_SHIFT 0 /* EQR_B3_C - [15:0] */
3082 #define WM2200_EQR_B3_C_WIDTH 16 /* EQR_B3_C - [15:0] */
3085 * R2338 (0x922) - EQR_13
3087 #define WM2200_EQR_B3_PG_MASK 0xFFFF /* EQR_B3_PG - [15:0] */
3088 #define WM2200_EQR_B3_PG_SHIFT 0 /* EQR_B3_PG - [15:0] */
3089 #define WM2200_EQR_B3_PG_WIDTH 16 /* EQR_B3_PG - [15:0] */
3092 * R2339 (0x923) - EQR_14
3094 #define WM2200_EQR_B4_A_MASK 0xFFFF /* EQR_B4_A - [15:0] */
3095 #define WM2200_EQR_B4_A_SHIFT 0 /* EQR_B4_A - [15:0] */
3096 #define WM2200_EQR_B4_A_WIDTH 16 /* EQR_B4_A - [15:0] */
3099 * R2340 (0x924) - EQR_15
3101 #define WM2200_EQR_B4_B_MASK 0xFFFF /* EQR_B4_B - [15:0] */
3102 #define WM2200_EQR_B4_B_SHIFT 0 /* EQR_B4_B - [15:0] */
3103 #define WM2200_EQR_B4_B_WIDTH 16 /* EQR_B4_B - [15:0] */
3106 * R2341 (0x925) - EQR_16
3108 #define WM2200_EQR_B4_C_MASK 0xFFFF /* EQR_B4_C - [15:0] */
3109 #define WM2200_EQR_B4_C_SHIFT 0 /* EQR_B4_C - [15:0] */
3110 #define WM2200_EQR_B4_C_WIDTH 16 /* EQR_B4_C - [15:0] */
3113 * R2342 (0x926) - EQR_17
3115 #define WM2200_EQR_B4_PG_MASK 0xFFFF /* EQR_B4_PG - [15:0] */
3116 #define WM2200_EQR_B4_PG_SHIFT 0 /* EQR_B4_PG - [15:0] */
3117 #define WM2200_EQR_B4_PG_WIDTH 16 /* EQR_B4_PG - [15:0] */
3120 * R2343 (0x927) - EQR_18
3122 #define WM2200_EQR_B5_A_MASK 0xFFFF /* EQR_B5_A - [15:0] */
3123 #define WM2200_EQR_B5_A_SHIFT 0 /* EQR_B5_A - [15:0] */
3124 #define WM2200_EQR_B5_A_WIDTH 16 /* EQR_B5_A - [15:0] */
3127 * R2344 (0x928) - EQR_19
3129 #define WM2200_EQR_B5_B_MASK 0xFFFF /* EQR_B5_B - [15:0] */
3130 #define WM2200_EQR_B5_B_SHIFT 0 /* EQR_B5_B - [15:0] */
3131 #define WM2200_EQR_B5_B_WIDTH 16 /* EQR_B5_B - [15:0] */
3134 * R2345 (0x929) - EQR_20
3136 #define WM2200_EQR_B5_PG_MASK 0xFFFF /* EQR_B5_PG - [15:0] */
3137 #define WM2200_EQR_B5_PG_SHIFT 0 /* EQR_B5_PG - [15:0] */
3138 #define WM2200_EQR_B5_PG_WIDTH 16 /* EQR_B5_PG - [15:0] */
3141 * R2366 (0x93E) - HPLPF1_1
3143 #define WM2200_LHPF1_MODE 0x0002 /* LHPF1_MODE */
3144 #define WM2200_LHPF1_MODE_MASK 0x0002 /* LHPF1_MODE */
3147 #define WM2200_LHPF1_ENA 0x0001 /* LHPF1_ENA */
3148 #define WM2200_LHPF1_ENA_MASK 0x0001 /* LHPF1_ENA */
3149 #define WM2200_LHPF1_ENA_SHIFT 0 /* LHPF1_ENA */
3153 * R2367 (0x93F) - HPLPF1_2
3155 #define WM2200_LHPF1_COEFF_MASK 0xFFFF /* LHPF1_COEFF - [15:0] */
3156 #define WM2200_LHPF1_COEFF_SHIFT 0 /* LHPF1_COEFF - [15:0] */
3157 #define WM2200_LHPF1_COEFF_WIDTH 16 /* LHPF1_COEFF - [15:0] */
3160 * R2370 (0x942) - HPLPF2_1
3162 #define WM2200_LHPF2_MODE 0x0002 /* LHPF2_MODE */
3163 #define WM2200_LHPF2_MODE_MASK 0x0002 /* LHPF2_MODE */
3166 #define WM2200_LHPF2_ENA 0x0001 /* LHPF2_ENA */
3167 #define WM2200_LHPF2_ENA_MASK 0x0001 /* LHPF2_ENA */
3168 #define WM2200_LHPF2_ENA_SHIFT 0 /* LHPF2_ENA */
3172 * R2371 (0x943) - HPLPF2_2
3174 #define WM2200_LHPF2_COEFF_MASK 0xFFFF /* LHPF2_COEFF - [15:0] */
3175 #define WM2200_LHPF2_COEFF_SHIFT 0 /* LHPF2_COEFF - [15:0] */
3176 #define WM2200_LHPF2_COEFF_WIDTH 16 /* LHPF2_COEFF - [15:0] */
3179 * R2560 (0xA00) - DSP1 Control 1
3181 #define WM2200_DSP1_RW_SEQUENCE_ENA 0x0001 /* DSP1_RW_SEQUENCE_ENA */
3182 #define WM2200_DSP1_RW_SEQUENCE_ENA_MASK 0x0001 /* DSP1_RW_SEQUENCE_ENA */
3183 #define WM2200_DSP1_RW_SEQUENCE_ENA_SHIFT 0 /* DSP1_RW_SEQUENCE_ENA */
3187 * R2562 (0xA02) - DSP1 Control 2
3189 #define WM2200_DSP1_PAGE_BASE_PM_0_MASK 0xFF00 /* DSP1_PAGE_BASE_PM - [15:8] */
3194 * R2563 (0xA03) - DSP1 Control 3
3196 #define WM2200_DSP1_PAGE_BASE_DM_0_MASK 0xFF00 /* DSP1_PAGE_BASE_DM - [15:8] */
3201 * R2564 (0xA04) - DSP1 Control 4
3203 #define WM2200_DSP1_PAGE_BASE_ZM_0_MASK 0xFF00 /* DSP1_PAGE_BASE_ZM - [15:8] */
3208 * R2566 (0xA06) - DSP1 Control 5
3210 …efine WM2200_DSP1_START_ADDRESS_WDMA_BUFFER_0_MASK 0x3FFF /* DSP1_START_ADDRESS_WDMA_BUFFER_0 - […
3211 …e WM2200_DSP1_START_ADDRESS_WDMA_BUFFER_0_SHIFT 0 /* DSP1_START_ADDRESS_WDMA_BUFFER_0 - [13:…
3212 …2200_DSP1_START_ADDRESS_WDMA_BUFFER_0_WIDTH 14 /* DSP1_START_ADDRESS_WDMA_BUFFER_0 - [13:0] */
3215 * R2567 (0xA07) - DSP1 Control 6
3217 …efine WM2200_DSP1_START_ADDRESS_WDMA_BUFFER_1_MASK 0x3FFF /* DSP1_START_ADDRESS_WDMA_BUFFER_1 - […
3218 …e WM2200_DSP1_START_ADDRESS_WDMA_BUFFER_1_SHIFT 0 /* DSP1_START_ADDRESS_WDMA_BUFFER_1 - [13:…
3219 …2200_DSP1_START_ADDRESS_WDMA_BUFFER_1_WIDTH 14 /* DSP1_START_ADDRESS_WDMA_BUFFER_1 - [13:0] */
3222 * R2568 (0xA08) - DSP1 Control 7
3224 …efine WM2200_DSP1_START_ADDRESS_WDMA_BUFFER_2_MASK 0x3FFF /* DSP1_START_ADDRESS_WDMA_BUFFER_2 - […
3225 …e WM2200_DSP1_START_ADDRESS_WDMA_BUFFER_2_SHIFT 0 /* DSP1_START_ADDRESS_WDMA_BUFFER_2 - [13:…
3226 …2200_DSP1_START_ADDRESS_WDMA_BUFFER_2_WIDTH 14 /* DSP1_START_ADDRESS_WDMA_BUFFER_2 - [13:0] */
3229 * R2569 (0xA09) - DSP1 Control 8
3231 …efine WM2200_DSP1_START_ADDRESS_WDMA_BUFFER_3_MASK 0x3FFF /* DSP1_START_ADDRESS_WDMA_BUFFER_3 - […
3232 …e WM2200_DSP1_START_ADDRESS_WDMA_BUFFER_3_SHIFT 0 /* DSP1_START_ADDRESS_WDMA_BUFFER_3 - [13:…
3233 …2200_DSP1_START_ADDRESS_WDMA_BUFFER_3_WIDTH 14 /* DSP1_START_ADDRESS_WDMA_BUFFER_3 - [13:0] */
3236 * R2570 (0xA0A) - DSP1 Control 9
3238 …efine WM2200_DSP1_START_ADDRESS_WDMA_BUFFER_4_MASK 0x3FFF /* DSP1_START_ADDRESS_WDMA_BUFFER_4 - […
3239 …e WM2200_DSP1_START_ADDRESS_WDMA_BUFFER_4_SHIFT 0 /* DSP1_START_ADDRESS_WDMA_BUFFER_4 - [13:…
3240 …2200_DSP1_START_ADDRESS_WDMA_BUFFER_4_WIDTH 14 /* DSP1_START_ADDRESS_WDMA_BUFFER_4 - [13:0] */
3243 * R2571 (0xA0B) - DSP1 Control 10
3245 …efine WM2200_DSP1_START_ADDRESS_WDMA_BUFFER_5_MASK 0x3FFF /* DSP1_START_ADDRESS_WDMA_BUFFER_5 - […
3246 …e WM2200_DSP1_START_ADDRESS_WDMA_BUFFER_5_SHIFT 0 /* DSP1_START_ADDRESS_WDMA_BUFFER_5 - [13:…
3247 …2200_DSP1_START_ADDRESS_WDMA_BUFFER_5_WIDTH 14 /* DSP1_START_ADDRESS_WDMA_BUFFER_5 - [13:0] */
3250 * R2572 (0xA0C) - DSP1 Control 11
3252 …efine WM2200_DSP1_START_ADDRESS_WDMA_BUFFER_6_MASK 0x3FFF /* DSP1_START_ADDRESS_WDMA_BUFFER_6 - […
3253 …e WM2200_DSP1_START_ADDRESS_WDMA_BUFFER_6_SHIFT 0 /* DSP1_START_ADDRESS_WDMA_BUFFER_6 - [13:…
3254 …2200_DSP1_START_ADDRESS_WDMA_BUFFER_6_WIDTH 14 /* DSP1_START_ADDRESS_WDMA_BUFFER_6 - [13:0] */
3257 * R2573 (0xA0D) - DSP1 Control 12
3259 …efine WM2200_DSP1_START_ADDRESS_WDMA_BUFFER_7_MASK 0x3FFF /* DSP1_START_ADDRESS_WDMA_BUFFER_7 - […
3260 …e WM2200_DSP1_START_ADDRESS_WDMA_BUFFER_7_SHIFT 0 /* DSP1_START_ADDRESS_WDMA_BUFFER_7 - [13:…
3261 …2200_DSP1_START_ADDRESS_WDMA_BUFFER_7_WIDTH 14 /* DSP1_START_ADDRESS_WDMA_BUFFER_7 - [13:0] */
3264 * R2575 (0xA0F) - DSP1 Control 13
3266 …efine WM2200_DSP1_START_ADDRESS_RDMA_BUFFER_0_MASK 0x3FFF /* DSP1_START_ADDRESS_RDMA_BUFFER_0 - […
3267 …e WM2200_DSP1_START_ADDRESS_RDMA_BUFFER_0_SHIFT 0 /* DSP1_START_ADDRESS_RDMA_BUFFER_0 - [13:…
3268 …2200_DSP1_START_ADDRESS_RDMA_BUFFER_0_WIDTH 14 /* DSP1_START_ADDRESS_RDMA_BUFFER_0 - [13:0] */
3271 * R2576 (0xA10) - DSP1 Control 14
3273 …efine WM2200_DSP1_START_ADDRESS_RDMA_BUFFER_1_MASK 0x3FFF /* DSP1_START_ADDRESS_RDMA_BUFFER_1 - […
3274 …e WM2200_DSP1_START_ADDRESS_RDMA_BUFFER_1_SHIFT 0 /* DSP1_START_ADDRESS_RDMA_BUFFER_1 - [13:…
3275 …2200_DSP1_START_ADDRESS_RDMA_BUFFER_1_WIDTH 14 /* DSP1_START_ADDRESS_RDMA_BUFFER_1 - [13:0] */
3278 * R2577 (0xA11) - DSP1 Control 15
3280 …efine WM2200_DSP1_START_ADDRESS_RDMA_BUFFER_2_MASK 0x3FFF /* DSP1_START_ADDRESS_RDMA_BUFFER_2 - […
3281 …e WM2200_DSP1_START_ADDRESS_RDMA_BUFFER_2_SHIFT 0 /* DSP1_START_ADDRESS_RDMA_BUFFER_2 - [13:…
3282 …2200_DSP1_START_ADDRESS_RDMA_BUFFER_2_WIDTH 14 /* DSP1_START_ADDRESS_RDMA_BUFFER_2 - [13:0] */
3285 * R2578 (0xA12) - DSP1 Control 16
3287 …efine WM2200_DSP1_START_ADDRESS_RDMA_BUFFER_3_MASK 0x3FFF /* DSP1_START_ADDRESS_RDMA_BUFFER_3 - […
3288 …e WM2200_DSP1_START_ADDRESS_RDMA_BUFFER_3_SHIFT 0 /* DSP1_START_ADDRESS_RDMA_BUFFER_3 - [13:…
3289 …2200_DSP1_START_ADDRESS_RDMA_BUFFER_3_WIDTH 14 /* DSP1_START_ADDRESS_RDMA_BUFFER_3 - [13:0] */
3292 * R2579 (0xA13) - DSP1 Control 17
3294 …efine WM2200_DSP1_START_ADDRESS_RDMA_BUFFER_4_MASK 0x3FFF /* DSP1_START_ADDRESS_RDMA_BUFFER_4 - […
3295 …e WM2200_DSP1_START_ADDRESS_RDMA_BUFFER_4_SHIFT 0 /* DSP1_START_ADDRESS_RDMA_BUFFER_4 - [13:…
3296 …2200_DSP1_START_ADDRESS_RDMA_BUFFER_4_WIDTH 14 /* DSP1_START_ADDRESS_RDMA_BUFFER_4 - [13:0] */
3299 * R2580 (0xA14) - DSP1 Control 18
3301 …efine WM2200_DSP1_START_ADDRESS_RDMA_BUFFER_5_MASK 0x3FFF /* DSP1_START_ADDRESS_RDMA_BUFFER_5 - […
3302 …e WM2200_DSP1_START_ADDRESS_RDMA_BUFFER_5_SHIFT 0 /* DSP1_START_ADDRESS_RDMA_BUFFER_5 - [13:…
3303 …2200_DSP1_START_ADDRESS_RDMA_BUFFER_5_WIDTH 14 /* DSP1_START_ADDRESS_RDMA_BUFFER_5 - [13:0] */
3306 * R2582 (0xA16) - DSP1 Control 19
3308 #define WM2200_DSP1_WDMA_BUFFER_LENGTH_MASK 0x00FF /* DSP1_WDMA_BUFFER_LENGTH - [7:0] */
3309 #define WM2200_DSP1_WDMA_BUFFER_LENGTH_SHIFT 0 /* DSP1_WDMA_BUFFER_LENGTH - [7:0] */
3310 #define WM2200_DSP1_WDMA_BUFFER_LENGTH_WIDTH 8 /* DSP1_WDMA_BUFFER_LENGTH - [7:0] */
3313 * R2583 (0xA17) - DSP1 Control 20
3315 #define WM2200_DSP1_WDMA_CHANNEL_ENABLE_MASK 0x00FF /* DSP1_WDMA_CHANNEL_ENABLE - [7:0] */
3316 #define WM2200_DSP1_WDMA_CHANNEL_ENABLE_SHIFT 0 /* DSP1_WDMA_CHANNEL_ENABLE - [7:0] */
3317 #define WM2200_DSP1_WDMA_CHANNEL_ENABLE_WIDTH 8 /* DSP1_WDMA_CHANNEL_ENABLE - [7:0] */
3320 * R2584 (0xA18) - DSP1 Control 21
3322 #define WM2200_DSP1_RDMA_CHANNEL_ENABLE_MASK 0x003F /* DSP1_RDMA_CHANNEL_ENABLE - [5:0] */
3323 #define WM2200_DSP1_RDMA_CHANNEL_ENABLE_SHIFT 0 /* DSP1_RDMA_CHANNEL_ENABLE - [5:0] */
3324 #define WM2200_DSP1_RDMA_CHANNEL_ENABLE_WIDTH 6 /* DSP1_RDMA_CHANNEL_ENABLE - [5:0] */
3327 * R2586 (0xA1A) - DSP1 Control 22
3329 #define WM2200_DSP1_DM_SIZE_MASK 0xFFFF /* DSP1_DM_SIZE - [15:0] */
3330 #define WM2200_DSP1_DM_SIZE_SHIFT 0 /* DSP1_DM_SIZE - [15:0] */
3331 #define WM2200_DSP1_DM_SIZE_WIDTH 16 /* DSP1_DM_SIZE - [15:0] */
3334 * R2587 (0xA1B) - DSP1 Control 23
3336 #define WM2200_DSP1_PM_SIZE_MASK 0xFFFF /* DSP1_PM_SIZE - [15:0] */
3337 #define WM2200_DSP1_PM_SIZE_SHIFT 0 /* DSP1_PM_SIZE - [15:0] */
3338 #define WM2200_DSP1_PM_SIZE_WIDTH 16 /* DSP1_PM_SIZE - [15:0] */
3341 * R2588 (0xA1C) - DSP1 Control 24
3343 #define WM2200_DSP1_ZM_SIZE_MASK 0xFFFF /* DSP1_ZM_SIZE - [15:0] */
3344 #define WM2200_DSP1_ZM_SIZE_SHIFT 0 /* DSP1_ZM_SIZE - [15:0] */
3345 #define WM2200_DSP1_ZM_SIZE_WIDTH 16 /* DSP1_ZM_SIZE - [15:0] */
3348 * R2590 (0xA1E) - DSP1 Control 25
3350 #define WM2200_DSP1_PING_FULL 0x8000 /* DSP1_PING_FULL */
3351 #define WM2200_DSP1_PING_FULL_MASK 0x8000 /* DSP1_PING_FULL */
3354 #define WM2200_DSP1_PONG_FULL 0x4000 /* DSP1_PONG_FULL */
3355 #define WM2200_DSP1_PONG_FULL_MASK 0x4000 /* DSP1_PONG_FULL */
3358 #define WM2200_DSP1_WDMA_ACTIVE_CHANNELS_MASK 0x00FF /* DSP1_WDMA_ACTIVE_CHANNELS - [7:0] */
3359 #define WM2200_DSP1_WDMA_ACTIVE_CHANNELS_SHIFT 0 /* DSP1_WDMA_ACTIVE_CHANNELS - [7:0] */
3360 #define WM2200_DSP1_WDMA_ACTIVE_CHANNELS_WIDTH 8 /* DSP1_WDMA_ACTIVE_CHANNELS - [7:0] */
3363 * R2592 (0xA20) - DSP1 Control 26
3365 #define WM2200_DSP1_SCRATCH_0_MASK 0xFFFF /* DSP1_SCRATCH_0 - [15:0] */
3366 #define WM2200_DSP1_SCRATCH_0_SHIFT 0 /* DSP1_SCRATCH_0 - [15:0] */
3367 #define WM2200_DSP1_SCRATCH_0_WIDTH 16 /* DSP1_SCRATCH_0 - [15:0] */
3370 * R2593 (0xA21) - DSP1 Control 27
3372 #define WM2200_DSP1_SCRATCH_1_MASK 0xFFFF /* DSP1_SCRATCH_1 - [15:0] */
3373 #define WM2200_DSP1_SCRATCH_1_SHIFT 0 /* DSP1_SCRATCH_1 - [15:0] */
3374 #define WM2200_DSP1_SCRATCH_1_WIDTH 16 /* DSP1_SCRATCH_1 - [15:0] */
3377 * R2594 (0xA22) - DSP1 Control 28
3379 #define WM2200_DSP1_SCRATCH_2_MASK 0xFFFF /* DSP1_SCRATCH_2 - [15:0] */
3380 #define WM2200_DSP1_SCRATCH_2_SHIFT 0 /* DSP1_SCRATCH_2 - [15:0] */
3381 #define WM2200_DSP1_SCRATCH_2_WIDTH 16 /* DSP1_SCRATCH_2 - [15:0] */
3384 * R2595 (0xA23) - DSP1 Control 29
3386 #define WM2200_DSP1_SCRATCH_3_MASK 0xFFFF /* DSP1_SCRATCH_3 - [15:0] */
3387 #define WM2200_DSP1_SCRATCH_3_SHIFT 0 /* DSP1_SCRATCH_3 - [15:0] */
3388 #define WM2200_DSP1_SCRATCH_3_WIDTH 16 /* DSP1_SCRATCH_3 - [15:0] */
3391 * R2596 (0xA24) - DSP1 Control 30
3393 #define WM2200_DSP1_DBG_CLK_ENA 0x0008 /* DSP1_DBG_CLK_ENA */
3394 #define WM2200_DSP1_DBG_CLK_ENA_MASK 0x0008 /* DSP1_DBG_CLK_ENA */
3397 #define WM2200_DSP1_SYS_ENA 0x0004 /* DSP1_SYS_ENA */
3398 #define WM2200_DSP1_SYS_ENA_MASK 0x0004 /* DSP1_SYS_ENA */
3401 #define WM2200_DSP1_CORE_ENA 0x0002 /* DSP1_CORE_ENA */
3402 #define WM2200_DSP1_CORE_ENA_MASK 0x0002 /* DSP1_CORE_ENA */
3405 #define WM2200_DSP1_START 0x0001 /* DSP1_START */
3406 #define WM2200_DSP1_START_MASK 0x0001 /* DSP1_START */
3407 #define WM2200_DSP1_START_SHIFT 0 /* DSP1_START */
3411 * R2598 (0xA26) - DSP1 Control 31
3413 #define WM2200_DSP1_CLK_RATE_MASK 0x0018 /* DSP1_CLK_RATE - [4:3] */
3416 #define WM2200_DSP1_CLK_AVAIL 0x0004 /* DSP1_CLK_AVAIL */
3417 #define WM2200_DSP1_CLK_AVAIL_MASK 0x0004 /* DSP1_CLK_AVAIL */
3420 #define WM2200_DSP1_CLK_REQ_MASK 0x0003 /* DSP1_CLK_REQ - [1:0] */
3421 #define WM2200_DSP1_CLK_REQ_SHIFT 0 /* DSP1_CLK_REQ - [1:0] */
3422 #define WM2200_DSP1_CLK_REQ_WIDTH 2 /* DSP1_CLK_REQ - [1:0] */
3425 * R2816 (0xB00) - DSP2 Control 1
3427 #define WM2200_DSP2_RW_SEQUENCE_ENA 0x0001 /* DSP2_RW_SEQUENCE_ENA */
3428 #define WM2200_DSP2_RW_SEQUENCE_ENA_MASK 0x0001 /* DSP2_RW_SEQUENCE_ENA */
3429 #define WM2200_DSP2_RW_SEQUENCE_ENA_SHIFT 0 /* DSP2_RW_SEQUENCE_ENA */
3433 * R2818 (0xB02) - DSP2 Control 2
3435 #define WM2200_DSP2_PAGE_BASE_PM_0_MASK 0xFF00 /* DSP2_PAGE_BASE_PM - [15:8] */
3440 * R2819 (0xB03) - DSP2 Control 3
3442 #define WM2200_DSP2_PAGE_BASE_DM_0_MASK 0xFF00 /* DSP2_PAGE_BASE_DM - [15:8] */
3447 * R2820 (0xB04) - DSP2 Control 4
3449 #define WM2200_DSP2_PAGE_BASE_ZM_0_MASK 0xFF00 /* DSP2_PAGE_BASE_ZM - [15:8] */
3454 * R2822 (0xB06) - DSP2 Control 5
3456 …efine WM2200_DSP2_START_ADDRESS_WDMA_BUFFER_0_MASK 0x3FFF /* DSP2_START_ADDRESS_WDMA_BUFFER_0 - […
3457 …e WM2200_DSP2_START_ADDRESS_WDMA_BUFFER_0_SHIFT 0 /* DSP2_START_ADDRESS_WDMA_BUFFER_0 - [13:…
3458 …2200_DSP2_START_ADDRESS_WDMA_BUFFER_0_WIDTH 14 /* DSP2_START_ADDRESS_WDMA_BUFFER_0 - [13:0] */
3461 * R2823 (0xB07) - DSP2 Control 6
3463 …efine WM2200_DSP2_START_ADDRESS_WDMA_BUFFER_1_MASK 0x3FFF /* DSP2_START_ADDRESS_WDMA_BUFFER_1 - […
3464 …e WM2200_DSP2_START_ADDRESS_WDMA_BUFFER_1_SHIFT 0 /* DSP2_START_ADDRESS_WDMA_BUFFER_1 - [13:…
3465 …2200_DSP2_START_ADDRESS_WDMA_BUFFER_1_WIDTH 14 /* DSP2_START_ADDRESS_WDMA_BUFFER_1 - [13:0] */
3468 * R2824 (0xB08) - DSP2 Control 7
3470 …efine WM2200_DSP2_START_ADDRESS_WDMA_BUFFER_2_MASK 0x3FFF /* DSP2_START_ADDRESS_WDMA_BUFFER_2 - […
3471 …e WM2200_DSP2_START_ADDRESS_WDMA_BUFFER_2_SHIFT 0 /* DSP2_START_ADDRESS_WDMA_BUFFER_2 - [13:…
3472 …2200_DSP2_START_ADDRESS_WDMA_BUFFER_2_WIDTH 14 /* DSP2_START_ADDRESS_WDMA_BUFFER_2 - [13:0] */
3475 * R2825 (0xB09) - DSP2 Control 8
3477 …efine WM2200_DSP2_START_ADDRESS_WDMA_BUFFER_3_MASK 0x3FFF /* DSP2_START_ADDRESS_WDMA_BUFFER_3 - […
3478 …e WM2200_DSP2_START_ADDRESS_WDMA_BUFFER_3_SHIFT 0 /* DSP2_START_ADDRESS_WDMA_BUFFER_3 - [13:…
3479 …2200_DSP2_START_ADDRESS_WDMA_BUFFER_3_WIDTH 14 /* DSP2_START_ADDRESS_WDMA_BUFFER_3 - [13:0] */
3482 * R2826 (0xB0A) - DSP2 Control 9
3484 …efine WM2200_DSP2_START_ADDRESS_WDMA_BUFFER_4_MASK 0x3FFF /* DSP2_START_ADDRESS_WDMA_BUFFER_4 - […
3485 …e WM2200_DSP2_START_ADDRESS_WDMA_BUFFER_4_SHIFT 0 /* DSP2_START_ADDRESS_WDMA_BUFFER_4 - [13:…
3486 …2200_DSP2_START_ADDRESS_WDMA_BUFFER_4_WIDTH 14 /* DSP2_START_ADDRESS_WDMA_BUFFER_4 - [13:0] */
3489 * R2827 (0xB0B) - DSP2 Control 10
3491 …efine WM2200_DSP2_START_ADDRESS_WDMA_BUFFER_5_MASK 0x3FFF /* DSP2_START_ADDRESS_WDMA_BUFFER_5 - […
3492 …e WM2200_DSP2_START_ADDRESS_WDMA_BUFFER_5_SHIFT 0 /* DSP2_START_ADDRESS_WDMA_BUFFER_5 - [13:…
3493 …2200_DSP2_START_ADDRESS_WDMA_BUFFER_5_WIDTH 14 /* DSP2_START_ADDRESS_WDMA_BUFFER_5 - [13:0] */
3496 * R2828 (0xB0C) - DSP2 Control 11
3498 …efine WM2200_DSP2_START_ADDRESS_WDMA_BUFFER_6_MASK 0x3FFF /* DSP2_START_ADDRESS_WDMA_BUFFER_6 - […
3499 …e WM2200_DSP2_START_ADDRESS_WDMA_BUFFER_6_SHIFT 0 /* DSP2_START_ADDRESS_WDMA_BUFFER_6 - [13:…
3500 …2200_DSP2_START_ADDRESS_WDMA_BUFFER_6_WIDTH 14 /* DSP2_START_ADDRESS_WDMA_BUFFER_6 - [13:0] */
3503 * R2829 (0xB0D) - DSP2 Control 12
3505 …efine WM2200_DSP2_START_ADDRESS_WDMA_BUFFER_7_MASK 0x3FFF /* DSP2_START_ADDRESS_WDMA_BUFFER_7 - […
3506 …e WM2200_DSP2_START_ADDRESS_WDMA_BUFFER_7_SHIFT 0 /* DSP2_START_ADDRESS_WDMA_BUFFER_7 - [13:…
3507 …2200_DSP2_START_ADDRESS_WDMA_BUFFER_7_WIDTH 14 /* DSP2_START_ADDRESS_WDMA_BUFFER_7 - [13:0] */
3510 * R2831 (0xB0F) - DSP2 Control 13
3512 …efine WM2200_DSP2_START_ADDRESS_RDMA_BUFFER_0_MASK 0x3FFF /* DSP2_START_ADDRESS_RDMA_BUFFER_0 - […
3513 …e WM2200_DSP2_START_ADDRESS_RDMA_BUFFER_0_SHIFT 0 /* DSP2_START_ADDRESS_RDMA_BUFFER_0 - [13:…
3514 …2200_DSP2_START_ADDRESS_RDMA_BUFFER_0_WIDTH 14 /* DSP2_START_ADDRESS_RDMA_BUFFER_0 - [13:0] */
3517 * R2832 (0xB10) - DSP2 Control 14
3519 …efine WM2200_DSP2_START_ADDRESS_RDMA_BUFFER_1_MASK 0x3FFF /* DSP2_START_ADDRESS_RDMA_BUFFER_1 - […
3520 …e WM2200_DSP2_START_ADDRESS_RDMA_BUFFER_1_SHIFT 0 /* DSP2_START_ADDRESS_RDMA_BUFFER_1 - [13:…
3521 …2200_DSP2_START_ADDRESS_RDMA_BUFFER_1_WIDTH 14 /* DSP2_START_ADDRESS_RDMA_BUFFER_1 - [13:0] */
3524 * R2833 (0xB11) - DSP2 Control 15
3526 …efine WM2200_DSP2_START_ADDRESS_RDMA_BUFFER_2_MASK 0x3FFF /* DSP2_START_ADDRESS_RDMA_BUFFER_2 - […
3527 …e WM2200_DSP2_START_ADDRESS_RDMA_BUFFER_2_SHIFT 0 /* DSP2_START_ADDRESS_RDMA_BUFFER_2 - [13:…
3528 …2200_DSP2_START_ADDRESS_RDMA_BUFFER_2_WIDTH 14 /* DSP2_START_ADDRESS_RDMA_BUFFER_2 - [13:0] */
3531 * R2834 (0xB12) - DSP2 Control 16
3533 …efine WM2200_DSP2_START_ADDRESS_RDMA_BUFFER_3_MASK 0x3FFF /* DSP2_START_ADDRESS_RDMA_BUFFER_3 - […
3534 …e WM2200_DSP2_START_ADDRESS_RDMA_BUFFER_3_SHIFT 0 /* DSP2_START_ADDRESS_RDMA_BUFFER_3 - [13:…
3535 …2200_DSP2_START_ADDRESS_RDMA_BUFFER_3_WIDTH 14 /* DSP2_START_ADDRESS_RDMA_BUFFER_3 - [13:0] */
3538 * R2835 (0xB13) - DSP2 Control 17
3540 …efine WM2200_DSP2_START_ADDRESS_RDMA_BUFFER_4_MASK 0x3FFF /* DSP2_START_ADDRESS_RDMA_BUFFER_4 - […
3541 …e WM2200_DSP2_START_ADDRESS_RDMA_BUFFER_4_SHIFT 0 /* DSP2_START_ADDRESS_RDMA_BUFFER_4 - [13:…
3542 …2200_DSP2_START_ADDRESS_RDMA_BUFFER_4_WIDTH 14 /* DSP2_START_ADDRESS_RDMA_BUFFER_4 - [13:0] */
3545 * R2836 (0xB14) - DSP2 Control 18
3547 …efine WM2200_DSP2_START_ADDRESS_RDMA_BUFFER_5_MASK 0x3FFF /* DSP2_START_ADDRESS_RDMA_BUFFER_5 - […
3548 …e WM2200_DSP2_START_ADDRESS_RDMA_BUFFER_5_SHIFT 0 /* DSP2_START_ADDRESS_RDMA_BUFFER_5 - [13:…
3549 …2200_DSP2_START_ADDRESS_RDMA_BUFFER_5_WIDTH 14 /* DSP2_START_ADDRESS_RDMA_BUFFER_5 - [13:0] */
3552 * R2838 (0xB16) - DSP2 Control 19
3554 #define WM2200_DSP2_WDMA_BUFFER_LENGTH_MASK 0x00FF /* DSP2_WDMA_BUFFER_LENGTH - [7:0] */
3555 #define WM2200_DSP2_WDMA_BUFFER_LENGTH_SHIFT 0 /* DSP2_WDMA_BUFFER_LENGTH - [7:0] */
3556 #define WM2200_DSP2_WDMA_BUFFER_LENGTH_WIDTH 8 /* DSP2_WDMA_BUFFER_LENGTH - [7:0] */
3559 * R2839 (0xB17) - DSP2 Control 20
3561 #define WM2200_DSP2_WDMA_CHANNEL_ENABLE_MASK 0x00FF /* DSP2_WDMA_CHANNEL_ENABLE - [7:0] */
3562 #define WM2200_DSP2_WDMA_CHANNEL_ENABLE_SHIFT 0 /* DSP2_WDMA_CHANNEL_ENABLE - [7:0] */
3563 #define WM2200_DSP2_WDMA_CHANNEL_ENABLE_WIDTH 8 /* DSP2_WDMA_CHANNEL_ENABLE - [7:0] */
3566 * R2840 (0xB18) - DSP2 Control 21
3568 #define WM2200_DSP2_RDMA_CHANNEL_ENABLE_MASK 0x003F /* DSP2_RDMA_CHANNEL_ENABLE - [5:0] */
3569 #define WM2200_DSP2_RDMA_CHANNEL_ENABLE_SHIFT 0 /* DSP2_RDMA_CHANNEL_ENABLE - [5:0] */
3570 #define WM2200_DSP2_RDMA_CHANNEL_ENABLE_WIDTH 6 /* DSP2_RDMA_CHANNEL_ENABLE - [5:0] */
3573 * R2842 (0xB1A) - DSP2 Control 22
3575 #define WM2200_DSP2_DM_SIZE_MASK 0xFFFF /* DSP2_DM_SIZE - [15:0] */
3576 #define WM2200_DSP2_DM_SIZE_SHIFT 0 /* DSP2_DM_SIZE - [15:0] */
3577 #define WM2200_DSP2_DM_SIZE_WIDTH 16 /* DSP2_DM_SIZE - [15:0] */
3580 * R2843 (0xB1B) - DSP2 Control 23
3582 #define WM2200_DSP2_PM_SIZE_MASK 0xFFFF /* DSP2_PM_SIZE - [15:0] */
3583 #define WM2200_DSP2_PM_SIZE_SHIFT 0 /* DSP2_PM_SIZE - [15:0] */
3584 #define WM2200_DSP2_PM_SIZE_WIDTH 16 /* DSP2_PM_SIZE - [15:0] */
3587 * R2844 (0xB1C) - DSP2 Control 24
3589 #define WM2200_DSP2_ZM_SIZE_MASK 0xFFFF /* DSP2_ZM_SIZE - [15:0] */
3590 #define WM2200_DSP2_ZM_SIZE_SHIFT 0 /* DSP2_ZM_SIZE - [15:0] */
3591 #define WM2200_DSP2_ZM_SIZE_WIDTH 16 /* DSP2_ZM_SIZE - [15:0] */
3594 * R2846 (0xB1E) - DSP2 Control 25
3596 #define WM2200_DSP2_PING_FULL 0x8000 /* DSP2_PING_FULL */
3597 #define WM2200_DSP2_PING_FULL_MASK 0x8000 /* DSP2_PING_FULL */
3600 #define WM2200_DSP2_PONG_FULL 0x4000 /* DSP2_PONG_FULL */
3601 #define WM2200_DSP2_PONG_FULL_MASK 0x4000 /* DSP2_PONG_FULL */
3604 #define WM2200_DSP2_WDMA_ACTIVE_CHANNELS_MASK 0x00FF /* DSP2_WDMA_ACTIVE_CHANNELS - [7:0] */
3605 #define WM2200_DSP2_WDMA_ACTIVE_CHANNELS_SHIFT 0 /* DSP2_WDMA_ACTIVE_CHANNELS - [7:0] */
3606 #define WM2200_DSP2_WDMA_ACTIVE_CHANNELS_WIDTH 8 /* DSP2_WDMA_ACTIVE_CHANNELS - [7:0] */
3609 * R2848 (0xB20) - DSP2 Control 26
3611 #define WM2200_DSP2_SCRATCH_0_MASK 0xFFFF /* DSP2_SCRATCH_0 - [15:0] */
3612 #define WM2200_DSP2_SCRATCH_0_SHIFT 0 /* DSP2_SCRATCH_0 - [15:0] */
3613 #define WM2200_DSP2_SCRATCH_0_WIDTH 16 /* DSP2_SCRATCH_0 - [15:0] */
3616 * R2849 (0xB21) - DSP2 Control 27
3618 #define WM2200_DSP2_SCRATCH_1_MASK 0xFFFF /* DSP2_SCRATCH_1 - [15:0] */
3619 #define WM2200_DSP2_SCRATCH_1_SHIFT 0 /* DSP2_SCRATCH_1 - [15:0] */
3620 #define WM2200_DSP2_SCRATCH_1_WIDTH 16 /* DSP2_SCRATCH_1 - [15:0] */
3623 * R2850 (0xB22) - DSP2 Control 28
3625 #define WM2200_DSP2_SCRATCH_2_MASK 0xFFFF /* DSP2_SCRATCH_2 - [15:0] */
3626 #define WM2200_DSP2_SCRATCH_2_SHIFT 0 /* DSP2_SCRATCH_2 - [15:0] */
3627 #define WM2200_DSP2_SCRATCH_2_WIDTH 16 /* DSP2_SCRATCH_2 - [15:0] */
3630 * R2851 (0xB23) - DSP2 Control 29
3632 #define WM2200_DSP2_SCRATCH_3_MASK 0xFFFF /* DSP2_SCRATCH_3 - [15:0] */
3633 #define WM2200_DSP2_SCRATCH_3_SHIFT 0 /* DSP2_SCRATCH_3 - [15:0] */
3634 #define WM2200_DSP2_SCRATCH_3_WIDTH 16 /* DSP2_SCRATCH_3 - [15:0] */
3637 * R2852 (0xB24) - DSP2 Control 30
3639 #define WM2200_DSP2_DBG_CLK_ENA 0x0008 /* DSP2_DBG_CLK_ENA */
3640 #define WM2200_DSP2_DBG_CLK_ENA_MASK 0x0008 /* DSP2_DBG_CLK_ENA */
3643 #define WM2200_DSP2_SYS_ENA 0x0004 /* DSP2_SYS_ENA */
3644 #define WM2200_DSP2_SYS_ENA_MASK 0x0004 /* DSP2_SYS_ENA */
3647 #define WM2200_DSP2_CORE_ENA 0x0002 /* DSP2_CORE_ENA */
3648 #define WM2200_DSP2_CORE_ENA_MASK 0x0002 /* DSP2_CORE_ENA */
3651 #define WM2200_DSP2_START 0x0001 /* DSP2_START */
3652 #define WM2200_DSP2_START_MASK 0x0001 /* DSP2_START */
3653 #define WM2200_DSP2_START_SHIFT 0 /* DSP2_START */
3657 * R2854 (0xB26) - DSP2 Control 31
3659 #define WM2200_DSP2_CLK_RATE_MASK 0x0018 /* DSP2_CLK_RATE - [4:3] */
3662 #define WM2200_DSP2_CLK_AVAIL 0x0004 /* DSP2_CLK_AVAIL */
3663 #define WM2200_DSP2_CLK_AVAIL_MASK 0x0004 /* DSP2_CLK_AVAIL */
3666 #define WM2200_DSP2_CLK_REQ_MASK 0x0003 /* DSP2_CLK_REQ - [1:0] */
3667 #define WM2200_DSP2_CLK_REQ_SHIFT 0 /* DSP2_CLK_REQ - [1:0] */
3668 #define WM2200_DSP2_CLK_REQ_WIDTH 2 /* DSP2_CLK_REQ - [1:0] */