Lines Matching +full:6 +full:- +full:bit

1 /* SPDX-License-Identifier: GPL-2.0-only */
3  * Copyright (c) 2018-2021, The Linux Foundation. All rights reserved.
15 #define WCD939X_BIAS_ANALOG_BIAS_EN	BIT(7)
16 #define WCD939X_BIAS_PRECHRG_EN	BIT(6)
17 #define WCD939X_BIAS_PRECHRG_CTL_MODE	BIT(5)
19 #define WCD939X_RX_SUPPLIES_VPOS_EN	BIT(7)
20 #define WCD939X_RX_SUPPLIES_VNEG_EN	BIT(6)
21 #define WCD939X_RX_SUPPLIES_VPOS_PWR_LVL	BIT(3)
22 #define WCD939X_RX_SUPPLIES_VNEG_PWR_LVL	BIT(2)
23 #define WCD939X_RX_SUPPLIES_REGULATOR_MODE	BIT(1)
24 #define WCD939X_RX_SUPPLIES_RX_BIAS_ENABLE	BIT(0)
26 #define WCD939X_HPH_HPHL_ENABLE	BIT(7)
27 #define WCD939X_HPH_HPHR_ENABLE	BIT(6)
28 #define WCD939X_HPH_HPHL_REF_ENABLE	BIT(5)
29 #define WCD939X_HPH_HPHR_REF_ENABLE	BIT(4)
33 #define WCD939X_EAR_COMPANDER_CTL_GAIN_OVRD_REG	BIT(7)
34 #define WCD939X_EAR_COMPANDER_CTL_EAR_GAIN	GENMASK(6, 2)
35 #define WCD939X_EAR_COMPANDER_CTL_COMP_DFF_BYP	BIT(1)
36 #define WCD939X_EAR_COMPANDER_CTL_COMP_DFF_CLK_EDGE	BIT(0)
39 #define WCD939X_TX_CH2_ENABLE	BIT(7)
40 #define WCD939X_TX_CH2_HPF1_INIT	BIT(6)
41 #define WCD939X_TX_CH2_HPF2_INIT	BIT(5)
45 #define WCD939X_TX_CH4_ENABLE	BIT(7)
46 #define WCD939X_TX_CH4_HPF3_INIT	BIT(6)
47 #define WCD939X_TX_CH4_HPF4_INIT	BIT(5)
52 #define WCD939X_MBHC_MECH_L_DET_EN	BIT(7)
53 #define WCD939X_MBHC_MECH_GND_DET_EN	BIT(6)
54 #define WCD939X_MBHC_MECH_MECH_DETECT_TYPE	BIT(5)
55 #define WCD939X_MBHC_MECH_HPHL_PLUG_TYPE	BIT(4)
56 #define WCD939X_MBHC_MECH_GND_PLUG_TYPE	BIT(3)
57 #define WCD939X_MBHC_MECH_MECH_HS_L_PULLUP_COMP_EN	BIT(2)
58 #define WCD939X_MBHC_MECH_MECH_HS_G_PULLUP_COMP_EN	BIT(1)
59 #define WCD939X_MBHC_MECH_SW_HPH_L_P_100K_TO_GND	BIT(0)
61 #define WCD939X_MBHC_ELECT_FSM_EN	BIT(7)
62 #define WCD939X_MBHC_ELECT_BTNDET_ISRC_CTL	GENMASK(6, 4)
63 #define WCD939X_MBHC_ELECT_ELECT_DET_TYPE	BIT(3)
65 #define WCD939X_MBHC_ELECT_BIAS_EN	BIT(0)
67 #define WCD939X_MBHC_ZDET_ZDET_L_MEAS_EN	BIT(7)
68 #define WCD939X_MBHC_ZDET_ZDET_R_MEAS_EN	BIT(6)
69 #define WCD939X_MBHC_ZDET_ZDET_CHG_EN	BIT(5)
70 #define WCD939X_MBHC_ZDET_ZDET_ILEAK_COMP_EN	BIT(4)
71 #define WCD939X_MBHC_ZDET_ELECT_ISRC_EN	BIT(1)
94 #define WCD939X_MICB_ENABLE	GENMASK(7, 6)
98 #define WCD939X_MICB2_RAMP_RAMP_ENABLE	BIT(7)
99 #define WCD939X_MICB2_RAMP_MB2_IN2P_SHORT_ENABLE	BIT(6)
100 #define WCD939X_MICB2_RAMP_ALLSW_OVRD_ENABLE	BIT(5)
117 #define WCD939X_MODE_LDOH_EN	BIT(7)
118 #define WCD939X_MODE_PWRDN_STATE	BIT(6)
119 #define WCD939X_MODE_SLOWRAMP_EN	BIT(5)
127 #define WCD939X_TEST_CTL_1_EN_VREFGEN	BIT(4)
128 #define WCD939X_TEST_CTL_1_EN_LDO	BIT(3)
131 #define WCD939X_TEST_CTL_2_IBIAS_VREFGEN	GENMASK(7, 6)
132 #define WCD939X_TEST_CTL_2_INRUSH_CURRENT_FIX_DIS	BIT(5)
135 #define WCD939X_TEST_CTL_3_CFILT_REF_EN	BIT(7)
136 #define WCD939X_TEST_CTL_3_RZ_LDO_VAL	GENMASK(6, 4)
173 #define WCD939X_TEST_BLK_EN2_ADC2_INT1_EN	BIT(7)
174 #define WCD939X_TEST_BLK_EN2_ADC2_INT2_EN	BIT(6)
175 #define WCD939X_TEST_BLK_EN2_ADC2_SAR_EN	BIT(5)
176 #define WCD939X_TEST_BLK_EN2_ADC2_CMGEN_EN	BIT(4)
177 #define WCD939X_TEST_BLK_EN2_ADC2_CLKGEN_EN	BIT(3)
179 #define WCD939X_TEST_BLK_EN2_TXFE2_MBHC_CLKRST_EN	BIT(0)
245 #define WCD939X_OCP_CTL_OCP_FSM_EN	BIT(4)
246 #define WCD939X_OCP_CTL_SPARE_BITS	BIT(3)
247 #define WCD939X_OCP_CTL_SCD_OP_EN	BIT(1)
252 #define WCD939X_PA_CTL2_HPHPA_GND_R	BIT(6)
253 #define WCD939X_PA_CTL2_HPHPA_GND_L	BIT(4)
256 #define WCD939X_L_EN_CONST_SEL_L	GENMASK(7, 6)
257 #define WCD939X_L_EN_GAIN_SOURCE_SEL	BIT(5)
262 #define WCD939X_R_EN_CONST_SEL_R	GENMASK(7, 6)
263 #define WCD939X_R_EN_GAIN_SOURCE_SEL	BIT(5)
267 #define WCD939X_R_ATEST_DACR_REF_ATEST1_CONN	BIT(7)
268 #define WCD939X_R_ATEST_LDO1_R_ATEST2_CONN	BIT(6)
269 #define WCD939X_R_ATEST_LDO_R_ATEST2_CAL	BIT(5)
270 #define WCD939X_R_ATEST_LDO2_R_ATEST2_CONN	BIT(4)
271 #define WCD939X_R_ATEST_LDO_1P65V_ATEST1_CONN	BIT(3)
272 #define WCD939X_R_ATEST_HPH_GND_OVR	BIT(1)
274 #define WCD939X_RDAC_CLK_CTL1_OPAMP_CHOP_CLK_EN	BIT(7)
275 #define WCD939X_RDAC_CLK_CTL1_OPAMP_CHOP_CLK_DIV_CTRL	GENMASK(6, 4)
281 #define WCD939X_REFBUFF_UHQA_CTL_SPARE_BITS	GENMASK(7, 6)
282 #define WCD939X_REFBUFF_UHQA_CTL_HPH_VNEGREG2_COMP_CTL_OV	BIT(5)
283 #define WCD939X_REFBUFF_UHQA_CTL_REFBUFN_RBIAS_ADJUST	BIT(4)
287 #define WCD939X_REFBUFF_LP_CTL_HPH_VNEGREG2_CURR_COMP	GENMASK(7, 6)
289 #define WCD939X_REFBUFF_LP_CTL_EN_PREREF_FILT_STARTUP_CLKDIV	BIT(3)
291 #define WCD939X_REFBUFF_LP_CTL_PREREF_FILT_BYPASS	BIT(0)
296 #define WCD939X_EN_EN_SURGE_PROTECTION_HPHL	BIT(7)
297 #define WCD939X_EN_EN_SURGE_PROTECTION_HPHR	BIT(6)
299 #define WCD939X_EN_SURGE_VOLT_MODE_SHUTOFF_EN	BIT(3)
300 #define WCD939X_EN_LATCH_INTR_OP_STG_HIZ_EN	BIT(2)
301 #define WCD939X_EN_SURGE_LATCH_REG_RESET	BIT(1)
302 #define WCD939X_EN_SWTICH_VN_VNDAC_NSURGE_EN	BIT(0)
309 #define WCD939X_DAC_CON_DAC_SAMPLE_EDGE_SEL	BIT(7)
310 #define WCD939X_DAC_CON_REF_DBG_EN	BIT(6)
313 #define WCD939X_DAC_CON_INV_DATA	BIT(0)
328 #define WCD939X_CTL_1_RCO_EN	BIT(7)
329 #define WCD939X_CTL_1_ADC_MODE	BIT(4)
330 #define WCD939X_CTL_1_ADC_ENABLE	BIT(3)
331 #define WCD939X_CTL_1_DETECTION_DONE	BIT(2)
334 #define WCD939X_CTL_2_MUX_CTL	GENMASK(6, 4)
339 #define WCD939X_ZDET_ANA_CTL_AVERAGING_EN	BIT(7)
340 #define WCD939X_ZDET_ANA_CTL_MAXV_CTL	GENMASK(6, 4)
343 #define WCD939X_ZDET_RAMP_CTL_ACC1_MIN_CTL	GENMASK(6, 4)
346 #define WCD939X_FSM_STATUS_ADC_TIMEOUT	BIT(7)
347 #define WCD939X_FSM_STATUS_ADC_COMPLETE	BIT(6)
348 #define WCD939X_FSM_STATUS_HS_M_COMP_STATUS	BIT(5)
349 #define WCD939X_FSM_STATUS_FAST_PRESS_FLAG_STATUS	BIT(4)
350 #define WCD939X_FSM_STATUS_FAST_REMOVAL_FLAG_STATUS	BIT(3)
351 #define WCD939X_FSM_STATUS_REMOVAL_FLAG_STATUS	BIT(2)
352 #define WCD939X_FSM_STATUS_ELECT_REM_RT_STATUS	BIT(1)
353 #define WCD939X_FSM_STATUS_BTN_STATUS	BIT(0)
362 #define WCD939X_PA_GAIN_CTL_L_EN_HPHPA_2VPK	BIT(7)
363 #define WCD939X_PA_GAIN_CTL_L_RX_SUPPLY_LEVEL	BIT(6)
364 #define WCD939X_PA_GAIN_CTL_L_DAC_DR_BOOST	BIT(5)
369 #define WCD939X_PA_GAIN_CTL_R_D_RCO_CLK_EN	BIT(7)
370 #define WCD939X_PA_GAIN_CTL_R_SPARE_BITS	GENMASK(6, 5)
378 #define WCD939X_TIMER1_AUTOCHOP_TIMER_CTL_EN	BIT(1)
385 #define WCD939X_RDAC_HD2_CTL_L_EN_HD2_RES_DIV_L	BIT(7)
386 #define WCD939X_RDAC_HD2_CTL_L_HD2_RES_DIV_PULLGND_L	BIT(6)
389 #define WCD939X_RDAC_HD2_CTL_R_EN_HD2_RES_DIV_R	BIT(7)
390 #define WCD939X_RDAC_HD2_CTL_R_HD2_RES_DIV_PULLGND_L	BIT(6)
396 #define WCD939X_MOISTURE_DET_DC_CTRL_ONCOUNT	GENMASK(6, 5)
399 #define WCD939X_MOISTURE_DET_POLLING_CTRL_HPHL_PA_EN	BIT(6)
401 #define WCD939X_MOISTURE_DET_POLLING_CTRL_MOIST_OVRD_POLLING	BIT(3)
402 #define WCD939X_MOISTURE_DET_POLLING_CTRL_MOIST_EN_POLLING	BIT(2)
446 #define WCD939X_CDC_ANA_CLK_CTL_ANA_TX_DIV4_CLK_EN	BIT(5)
447 #define WCD939X_CDC_ANA_CLK_CTL_ANA_TX_DIV2_CLK_EN	BIT(4)
448 #define WCD939X_CDC_ANA_CLK_CTL_ANA_TX_CLK_EN	BIT(3)
449 #define WCD939X_CDC_ANA_CLK_CTL_ANA_RX_DIV4_CLK_EN	BIT(2)
450 #define WCD939X_CDC_ANA_CLK_CTL_ANA_RX_DIV2_CLK_EN	BIT(1)
451 #define WCD939X_CDC_ANA_CLK_CTL_ANA_RX_CLK_EN	BIT(0)
452 #define WCD939X_CDC_ANA_CLK_CTL_ANA_TX_DIV2_CLK_EN	BIT(4)
454 #define WCD939X_CDC_DIG_CLK_CTL_TXD3_CLK_EN	BIT(7)
455 #define WCD939X_CDC_DIG_CLK_CTL_TXD2_CLK_EN	BIT(6)
456 #define WCD939X_CDC_DIG_CLK_CTL_TXD1_CLK_EN	BIT(5)
457 #define WCD939X_CDC_DIG_CLK_CTL_TXD0_CLK_EN	BIT(4)
458 #define WCD939X_CDC_DIG_CLK_CTL_RXD2_CLK_EN	BIT(2)
459 #define WCD939X_CDC_DIG_CLK_CTL_RXD1_CLK_EN	BIT(1)
460 #define WCD939X_CDC_DIG_CLK_CTL_RXD0_CLK_EN	BIT(0)
474 #define WCD939X_CDC_COMP_CTL_0_HPHL_COMP_EN	BIT(1)
475 #define WCD939X_CDC_COMP_CTL_0_HPHR_COMP_EN	BIT(0)
477 #define WCD939X_CDC_ANA_TX_CLK_CTL_ANA_MBHC_1P2M_CLK_EN	BIT(5)
478 #define WCD939X_CDC_ANA_TX_CLK_CTL_ANA_TX3_ADC_CLK_EN	BIT(4)
479 #define WCD939X_CDC_ANA_TX_CLK_CTL_ANA_TX2_ADC_CLK_EN	BIT(3)
480 #define WCD939X_CDC_ANA_TX_CLK_CTL_ANA_TX1_ADC_CLK_EN	BIT(2)
481 #define WCD939X_CDC_ANA_TX_CLK_CTL_ANA_TX0_ADC_CLK_EN	BIT(1)
482 #define WCD939X_CDC_ANA_TX_CLK_CTL_ANA_TXSCBIAS_CLK_EN	BIT(0)
538 #define WCD939X_CDC_HPH_GAIN_CTL_HPH_STEREO_EN	BIT(4)
539 #define WCD939X_CDC_HPH_GAIN_CTL_HPHR_RX_EN	BIT(3)
540 #define WCD939X_CDC_HPH_GAIN_CTL_HPHL_RX_EN	BIT(2)
541 #define WCD939X_CDC_HPH_GAIN_CTL_HPHR_DSD_EN	BIT(1)
542 #define WCD939X_CDC_HPH_GAIN_CTL_HPHL_DSD_EN	BIT(0)
544 #define WCD939X_CDC_EAR_GAIN_CTL_EAR_EN	BIT(0)
554 #define WCD939X_CDC_REQ_CTL_TX3_WIDE_BAND	BIT(5)
555 #define WCD939X_CDC_REQ_CTL_TX2_WIDE_BAND	BIT(4)
556 #define WCD939X_CDC_REQ_CTL_TX1_WIDE_BAND	BIT(3)
557 #define WCD939X_CDC_REQ_CTL_TX0_WIDE_BAND	BIT(2)
558 #define WCD939X_CDC_REQ_CTL_FS_RATE_4P8	BIT(1)
559 #define WCD939X_CDC_REQ_CTL_NO_NOTCH	BIT(0)
562 #define WCD939X_CDC_AMIC_CTL_AMIC5_IN_SEL	BIT(3)
563 #define WCD939X_CDC_AMIC_CTL_AMIC4_IN_SEL	BIT(2)
564 #define WCD939X_CDC_AMIC_CTL_AMIC3_IN_SEL	BIT(1)
565 #define WCD939X_CDC_AMIC_CTL_AMIC1_IN_SEL	BIT(0)
567 #define WCD939X_CDC_DMIC_CTL_DMIC_LEGACY_SW_MODE	BIT(3)
568 #define WCD939X_CDC_DMIC_CTL_DMIC_DIV_BAK_EN	BIT(2)
569 #define WCD939X_CDC_DMIC_CTL_CLK_SCALE_EN	BIT(1)
570 #define WCD939X_CDC_DMIC_CTL_SOFT_RESET	BIT(0)
572 #define WCD939X_CDC_DMIC1_CTL_DMIC_CLK_SCALE_SEL	GENMASK(6, 4)
573 #define WCD939X_CDC_DMIC1_CTL_DMIC_CLK_EN	BIT(3)
576 #define WCD939X_CDC_DMIC2_CTL_DMIC_LEFT_EN	BIT(7)
577 #define WCD939X_CDC_DMIC2_CTL_DMIC_CLK_SCALE_SEL	GENMASK(6, 4)
578 #define WCD939X_CDC_DMIC2_CTL_DMIC_CLK_EN	BIT(3)
581 #define WCD939X_CDC_DMIC3_CTL_DMIC_CLK_SCALE_SEL	GENMASK(6, 4)
582 #define WCD939X_CDC_DMIC3_CTL_DMIC_CLK_EN	BIT(3)
585 #define WCD939X_CDC_DMIC4_CTL_DMIC_CLK_SCALE_SEL	GENMASK(6, 4)
586 #define WCD939X_CDC_DMIC4_CTL_DMIC_CLK_EN	BIT(3)
597 #define WCD939X_PDM_WD_CTL0_HOLD_OFF	BIT(4)
598 #define WCD939X_PDM_WD_CTL0_TIME_OUT_SEL	BIT(3)
601 #define WCD939X_PDM_WD_CTL1_HOLD_OFF	BIT(4)
602 #define WCD939X_PDM_WD_CTL1_TIME_OUT_SEL	BIT(3)
675 #define WCD939X_EFUSE_REG_0_EFUSE_BLOWN	BIT(0)
728 #define WCD939X_TOP_CFG0_HPH_DAC_RATE_SEL	BIT(1)
729 #define WCD939X_TOP_CFG0_PGA_UPDATE	BIT(0)
753 #define WCD939X_HPHL_PATH_CFG0_INT_EN	BIT(1)
754 #define WCD939X_HPHL_PATH_CFG0_DLY_ZN_EN	BIT(0)
756 #define WCD939X_HPHL_PATH_CFG1_DSM_SOFT_RST	BIT(5)
757 #define WCD939X_HPHL_PATH_CFG1_INT_SOFT_RST	BIT(4)
758 #define WCD939X_HPHL_PATH_CFG1_FMT_CONV	BIT(3)
759 #define WCD939X_HPHL_PATH_CFG1_IDLE_OVRD_EN	BIT(2)
762 #define WCD939X_HPHR_PATH_CFG0_INT_EN	BIT(2)
763 #define WCD939X_HPHR_PATH_CFG0_DLY_ZN_EN	BIT(1)
765 #define WCD939X_HPHR_PATH_CFG1_DSM_SOFT_RST	BIT(5)
766 #define WCD939X_HPHR_PATH_CFG1_INT_SOFT_RST	BIT(4)
767 #define WCD939X_HPHR_PATH_CFG1_FMT_CONV	BIT(3)
768 #define WCD939X_HPHR_PATH_CFG1_IDLE_OVRD_EN	BIT(2)
823 #define WCD939X_CFG0_AUTO_DISABLE_ANC	BIT(2)
824 #define WCD939X_CFG0_AUTO_DISABLE_DSD	BIT(1)
825 #define WCD939X_CFG0_IDLE_STEREO	BIT(0)
943 	return -EOPNOTSUPP;  in wcd939x_sdw_free()
950 	return -EOPNOTSUPP;  in wcd939x_sdw_set_sdw_stream()
958 	return -EOPNOTSUPP;  in wcd939x_sdw_hw_params()
973 	return PTR_ERR(-EINVAL);  in wcd939x_swr_get_regmap()