Lines Matching +full:channel +full:- +full:5
1 // SPDX-License-Identifier: GPL-2.0
2 // tscs454.c -- TSCS454 ALSA SoC Audio driver
21 #include <sound/soc-dapm.h>
28 #define BIQUAD_COEFF_COUNT 5
50 pll->id = id; in pll_init()
51 mutex_init(&pll->lock); in pll_init()
66 aif->id = id; in aif_init()
85 cache[((norm_addrs[i] + 1) * COEFF_SIZE) - 1] = 0x40; in init_coeff_ram_cache()
90 init_coeff_ram_cache(ram->cache); in coeff_ram_init()
91 mutex_init(&ram->lock); in coeff_ram_init()
103 status->streams |= mask; in set_aif_status_active()
111 status->streams &= mask; in set_aif_status_inactive()
116 return status->streams; in aifs_active()
121 return (0x03 << aif_id * 2) & status->streams; in aif_active()
282 tscs454->regmap = devm_regmap_init_i2c(i2c, &tscs454_regmap_cfg); in tscs454_data_init()
283 if (IS_ERR(tscs454->regmap)) { in tscs454_data_init()
284 ret = PTR_ERR(tscs454->regmap); in tscs454_data_init()
289 aif_init(&tscs454->aifs[i], i); in tscs454_data_init()
291 mutex_init(&tscs454->aifs_status_lock); in tscs454_data_init()
292 pll_init(&tscs454->pll1, 1); in tscs454_data_init()
293 pll_init(&tscs454->pll2, 2); in tscs454_data_init()
295 coeff_ram_init(&tscs454->dac_ram); in tscs454_data_init()
296 coeff_ram_init(&tscs454->spk_ram); in tscs454_data_init()
297 coeff_ram_init(&tscs454->sub_ram); in tscs454_data_init()
314 (struct coeff_ram_ctl *)kcontrol->private_value; in coeff_ram_get()
315 struct soc_bytes_ext *params = &ctl->bytes_ext; in coeff_ram_get()
319 if (strstr(kcontrol->id.name, "DAC")) { in coeff_ram_get()
320 coeff_ram = tscs454->dac_ram.cache; in coeff_ram_get()
321 coeff_ram_lock = &tscs454->dac_ram.lock; in coeff_ram_get()
322 } else if (strstr(kcontrol->id.name, "Speaker")) { in coeff_ram_get()
323 coeff_ram = tscs454->spk_ram.cache; in coeff_ram_get()
324 coeff_ram_lock = &tscs454->spk_ram.lock; in coeff_ram_get()
325 } else if (strstr(kcontrol->id.name, "Sub")) { in coeff_ram_get()
326 coeff_ram = tscs454->sub_ram.cache; in coeff_ram_get()
327 coeff_ram_lock = &tscs454->sub_ram.lock; in coeff_ram_get()
329 return -EINVAL; in coeff_ram_get()
334 memcpy(ucontrol->value.bytes.data, in coeff_ram_get()
335 &coeff_ram[ctl->addr * COEFF_SIZE], params->max); in coeff_ram_get()
362 ret = -EIO; in write_coeff_ram()
363 dev_err(component->dev, in write_coeff_ram()
368 ret = regmap_write(tscs454->regmap, r_addr, coeff_addr); in write_coeff_ram()
370 dev_err(component->dev, in write_coeff_ram()
375 ret = regmap_bulk_write(tscs454->regmap, r_wr, in write_coeff_ram()
379 dev_err(component->dev, in write_coeff_ram()
395 (struct coeff_ram_ctl *)kcontrol->private_value; in coeff_ram_put()
396 struct soc_bytes_ext *params = &ctl->bytes_ext; in coeff_ram_put()
397 unsigned int coeff_cnt = params->max / COEFF_SIZE; in coeff_ram_put()
407 if (strstr(kcontrol->id.name, "DAC")) { in coeff_ram_put()
408 coeff_ram = tscs454->dac_ram.cache; in coeff_ram_put()
409 coeff_ram_lock = &tscs454->dac_ram.lock; in coeff_ram_put()
410 coeff_ram_synced = &tscs454->dac_ram.synced; in coeff_ram_put()
414 } else if (strstr(kcontrol->id.name, "Speaker")) { in coeff_ram_put()
415 coeff_ram = tscs454->spk_ram.cache; in coeff_ram_put()
416 coeff_ram_lock = &tscs454->spk_ram.lock; in coeff_ram_put()
417 coeff_ram_synced = &tscs454->spk_ram.synced; in coeff_ram_put()
421 } else if (strstr(kcontrol->id.name, "Sub")) { in coeff_ram_put()
422 coeff_ram = tscs454->sub_ram.cache; in coeff_ram_put()
423 coeff_ram_lock = &tscs454->sub_ram.lock; in coeff_ram_put()
424 coeff_ram_synced = &tscs454->sub_ram.synced; in coeff_ram_put()
429 return -EINVAL; in coeff_ram_put()
436 memcpy(&coeff_ram[ctl->addr * COEFF_SIZE], in coeff_ram_put()
437 ucontrol->value.bytes.data, params->max); in coeff_ram_put()
439 mutex_lock(&tscs454->pll1.lock); in coeff_ram_put()
440 mutex_lock(&tscs454->pll2.lock); in coeff_ram_put()
446 ctl->addr, coeff_cnt); in coeff_ram_put()
448 dev_err(component->dev, in coeff_ram_put()
457 mutex_unlock(&tscs454->pll2.lock); in coeff_ram_put()
458 mutex_unlock(&tscs454->pll1.lock); in coeff_ram_put()
469 mutex_lock(&tscs454->dac_ram.lock); in coeff_ram_sync()
470 if (!tscs454->dac_ram.synced) { in coeff_ram_sync()
471 ret = write_coeff_ram(component, tscs454->dac_ram.cache, in coeff_ram_sync()
475 mutex_unlock(&tscs454->dac_ram.lock); in coeff_ram_sync()
479 mutex_unlock(&tscs454->dac_ram.lock); in coeff_ram_sync()
481 mutex_lock(&tscs454->spk_ram.lock); in coeff_ram_sync()
482 if (!tscs454->spk_ram.synced) { in coeff_ram_sync()
483 ret = write_coeff_ram(component, tscs454->spk_ram.cache, in coeff_ram_sync()
487 mutex_unlock(&tscs454->spk_ram.lock); in coeff_ram_sync()
491 mutex_unlock(&tscs454->spk_ram.lock); in coeff_ram_sync()
493 mutex_lock(&tscs454->sub_ram.lock); in coeff_ram_sync()
494 if (!tscs454->sub_ram.synced) { in coeff_ram_sync()
495 ret = write_coeff_ram(component, tscs454->sub_ram.cache, in coeff_ram_sync()
499 mutex_unlock(&tscs454->sub_ram.lock); in coeff_ram_sync()
503 mutex_unlock(&tscs454->sub_ram.lock); in coeff_ram_sync()
633 if (tscs454->sysclk_src_id < PLL_INPUT_BCLK) in set_sysclk()
634 freq = clk_get_rate(tscs454->sysclk); in set_sysclk()
636 freq = tscs454->bclk_freq; in set_sysclk()
639 ret = -EINVAL; in set_sysclk()
640 dev_err(component->dev, in set_sysclk()
647 pll_ctl->settings[i].addr, in set_sysclk()
648 pll_ctl->settings[i].val); in set_sysclk()
650 dev_err(component->dev, in set_sysclk()
662 mutex_lock(&pll->lock); in reserve_pll()
663 pll->users++; in reserve_pll()
664 mutex_unlock(&pll->lock); in reserve_pll()
669 mutex_lock(&pll->lock); in free_pll()
670 pll->users--; in free_pll()
671 mutex_unlock(&pll->lock); in free_pll()
678 snd_soc_dapm_to_component(source->dapm); in pll_connected()
682 if (strstr(source->name, "PLL 1")) { in pll_connected()
683 mutex_lock(&tscs454->pll1.lock); in pll_connected()
684 users = tscs454->pll1.users; in pll_connected()
685 mutex_unlock(&tscs454->pll1.lock); in pll_connected()
686 dev_dbg(component->dev, "%s(): PLL 1 users = %d\n", __func__, in pll_connected()
689 mutex_lock(&tscs454->pll2.lock); in pll_connected()
690 users = tscs454->pll2.users; in pll_connected()
691 mutex_unlock(&tscs454->pll2.lock); in pll_connected()
692 dev_dbg(component->dev, "%s(): PLL 2 users = %d\n", __func__, in pll_connected()
707 snd_soc_dapm_to_component(w->dapm); in pll_power_event()
715 if (strstr(w->name, "PLL 1")) in pll_power_event()
739 dev_err(component->dev, "Failed to %s PLL %d (%d)\n", in pll_power_event()
750 dev_err(component->dev, in pll_power_event()
778 ret = -ENODEV; in aif_set_provider()
779 dev_err(component->dev, "Unknown DAI %d (%d)\n", aif_id, ret); in aif_set_provider()
787 dev_err(component->dev, "Failed to set DAI %d to %s (%d)\n", in aif_set_provider()
800 ret = aif_set_provider(component, aif->id, aif->provider); in aif_prepare()
812 mutex_lock(&tscs454->aifs_status_lock); in aif_free()
814 dev_dbg(component->dev, "%s(): aif %d\n", __func__, aif->id); in aif_free()
816 set_aif_status_inactive(&tscs454->aifs_status, aif->id, playback); in aif_free()
818 dev_dbg(component->dev, "Set aif %d inactive. Streams status is 0x%x\n", in aif_free()
819 aif->id, tscs454->aifs_status.streams); in aif_free()
821 if (!aif_active(&tscs454->aifs_status, aif->id)) { in aif_free()
823 aif_set_provider(component, aif->id, false); in aif_free()
824 dev_dbg(component->dev, "Freeing pll %d from aif %d\n", in aif_free()
825 aif->pll->id, aif->id); in aif_free()
826 free_pll(aif->pll); in aif_free()
829 if (!aifs_active(&tscs454->aifs_status)) { in aif_free()
830 dev_dbg(component->dev, "Freeing pll %d from ir\n", in aif_free()
831 tscs454->internal_rate.pll->id); in aif_free()
832 free_pll(tscs454->internal_rate.pll); in aif_free()
835 mutex_unlock(&tscs454->aifs_status_lock); in aif_free()
947 "CH 4", "CH 5", "CH 4 + 5",
1008 SOC_DAPM_ENUM("Input Boost Channel 0 Enum",
1021 SOC_DAPM_ENUM("ADC Channel 0 Enum", adc_mux_ch0_enum);
1030 SOC_DAPM_ENUM("Input Processor Channel 0 Enum",
1039 SOC_DAPM_ENUM("Input Boost Channel 1 Enum",
1046 SOC_DAPM_ENUM("ADC Channel 1 Enum", adc_mux_ch1_enum);
1052 SOC_DAPM_ENUM("Input Processor Channel 1 Enum",
1068 "Normal", "Mono Mix to Channel 0",
1069 "Mono Mix to Channel 1", "Add"};
1106 static DECLARE_TLV_DB_SCALE(in_pga_vol_tlv_arr, -1725, 75, 0);
1112 static DECLARE_TLV_DB_MINMAX(in_vol_tlv_arr, -7125, 2400);
1118 static DECLARE_TLV_DB_MINMAX(asrc_vol_tlv_arr, -9562, 600);
1129 "Channel 0", "Channel 1", "Channel 2", "Channel 3", "Peak"};
1136 static DECLARE_TLV_DB_SCALE(alc_max_gain_tlv_arr, -1200, 600, 0);
1137 static DECLARE_TLV_DB_SCALE(alc_target_tlv_arr, -2850, 150, 0);
1140 static DECLARE_TLV_DB_SCALE(alc_min_gain_tlv_arr, -1725, 600, 0);
1143 static DECLARE_TLV_DB_SCALE(ngth_tlv_arr, -7650, 150, 0);
1192 static DECLARE_TLV_DB_MINMAX(mvol_tlv_arr, -9562, 0);
1196 static DECLARE_TLV_DB_SCALE(hp_vol_tlv_arr, -8850, 75, 0);
1200 static DECLARE_TLV_DB_SCALE(spk_vol_tlv_arr, -7725, 75, 0);
1206 "Pre Scale + EQ Band 0 - 1",
1207 "Pre Scale + EQ Band 0 - 2",
1208 "Pre Scale + EQ Band 0 - 3",
1209 "Pre Scale + EQ Band 0 - 4",
1210 "Pre Scale + EQ Band 0 - 5",
1256 static DECLARE_TLV_DB_MINMAX(mbc_mug_tlv_arr, -4650, 0);
1259 static DECLARE_TLV_DB_MINMAX(thr_tlv_arr, -9562, 0);
1263 "Reserved", "1.5:1", "2:1", "3:1", "4:1", "5:1", "6:1",
1311 "1:4", "1:5", "1:6", "1:7"};
1399 /* R_SUBEQFILT PG 5 ADDR 0x01 */
1407 /* R_SUBMBCCTL PG 5 ADDR 0x0B */
1432 /* R_SUBMBCMUG1 PG 5 ADDR 0x0C */
1437 /* R_SUBMBCRAT1 PG 5 ADDR 0x0E */
1442 /* R_SUBMBCMUG2 PG 5 ADDR 0x13 */
1447 /* R_SUBMBCRAT2 PG 5 ADDR 0x15 */
1452 /* R_SUBMBCMUG3 PG 5 ADDR 0x1A */
1457 /* R_SUBMBCRAT3 PG 5 ADDR 0x1C */
1462 /* R_SUBCLECTL PG 5 ADDR 0x21 */
1470 /* R_SUBCOMPRAT PG 5 ADDR 0x24 */
1475 /* R_SUBEXPRAT PG 5 ADDR 0x30 */
1484 (struct coeff_ram_ctl *)kcontrol->private_value; in bytes_info_ext()
1485 struct soc_bytes_ext *params = &ctl->bytes_ext; in bytes_info_ext()
1487 ucontrol->type = SNDRV_CTL_ELEM_TYPE_BYTES; in bytes_info_ext()
1488 ucontrol->count = params->max; in bytes_info_ext()
1574 SOC_SINGLE_TLV("Input Boost Channel 0 Volume", R_CH0AIC,
1577 SOC_SINGLE_TLV("Input Boost Channel 1 Volume", R_CH1AIC,
1580 SOC_SINGLE_TLV("Input Boost Channel 2 Volume", R_CH2AIC,
1583 SOC_SINGLE_TLV("Input Boost Channel 3 Volume", R_CH3AIC,
1586 SOC_ENUM("Input Channel 1 Polarity", in_pol_ch1_enum),
1587 SOC_ENUM("Input Channel 0 Polarity", in_pol_ch0_enum),
1588 SOC_ENUM("Input Processor Channel 0/1 Operation",
1590 SOC_SINGLE("Input Channel 1 Mute Switch",
1592 SOC_SINGLE("Input Channel 0 Mute Switch",
1594 SOC_SINGLE("Input Channel 1 HPF Disable Switch",
1596 SOC_SINGLE("Input Channel 0 HPF Disable Switch",
1599 SOC_ENUM("Input Channel 3 Polarity", in_pol_ch3_enum),
1600 SOC_ENUM("Input Channel 2 Polarity", in_pol_ch2_enum),
1601 SOC_ENUM("Input Processor Channel 2/3 Operation",
1603 SOC_SINGLE("Input Channel 3 Mute Switch",
1605 SOC_SINGLE("Input Channel 2 Mute Switch",
1607 SOC_SINGLE("Input Channel 3 HPF Disable Switch",
1609 SOC_SINGLE("Input Channel 2 HPF Disable Switch",
1615 SOC_SINGLE("Input Channel 0 PGA Mute Switch",
1617 SOC_SINGLE_TLV("Input Channel 0 PGA Volume", R_PGACTL0,
1621 SOC_SINGLE("Input Channel 1 PGA Mute Switch",
1623 SOC_SINGLE_TLV("Input Channel 1 PGA Volume", R_PGACTL1,
1627 SOC_SINGLE("Input Channel 2 PGA Mute Switch",
1629 SOC_SINGLE_TLV("Input Channel 2 PGA Volume", R_PGACTL2,
1633 SOC_SINGLE("Input Channel 3 PGA Mute Switch",
1635 SOC_SINGLE_TLV("Input Channel 3 PGA Volume", R_PGACTL3,
1639 SOC_SINGLE_TLV("Input Channel 0 Volume", R_ICH0VOL,
1642 SOC_SINGLE_TLV("Input Channel 1 Volume", R_ICH1VOL,
1645 SOC_SINGLE_TLV("Input Channel 2 Volume", R_ICH2VOL,
1648 SOC_SINGLE_TLV("Input Channel 3 Volume", R_ICH3VOL,
1670 SOC_SINGLE("Input Channel 3 ALC Switch",
1672 SOC_SINGLE("Input Channel 2 ALC Switch",
1674 SOC_SINGLE("Input Channel 1 ALC Switch",
1676 SOC_SINGLE("Input Channel 0 ALC Switch",
1712 SOC_SINGLE("DAC De-Emphasis Switch", R_DACCTL, FB_DACCTL_DACDEM, 1, 0),
1717 SOC_SINGLE("Speaker De-Emphasis Switch",
1722 SOC_SINGLE("Sub De-Emphasis Switch", R_SUBCTL, FB_SUBCTL_SUBDEM, 1, 0),
1772 SOC_SINGLE_TLV("Speaker MBC1 Make-Up Gain Volume", R_SPKMBCMUG1,
1789 SOC_SINGLE_TLV("Speaker MBC2 Make-Up Gain Volume", R_SPKMBCMUG2,
1806 SOC_SINGLE_TLV("Speaker MBC 3 Make-Up Gain Volume", R_SPKMBCMUG3,
1831 SOC_SINGLE_TLV("Speaker CLE Make-Up Gain Volume", R_SPKCLEMUG,
1901 SOC_SINGLE_TLV("DAC MBC 1 Make-Up Gain Volume", R_DACMBCMUG1,
1918 SOC_SINGLE_TLV("DAC MBC 2 Make-Up Gain Volume", R_DACMBCMUG2,
1935 SOC_SINGLE_TLV("DAC MBC 3 Make-Up Gain Volume", R_DACMBCMUG3,
1960 SOC_SINGLE_TLV("DAC CLE Make-Up Gain Volume", R_DACCLEMUG,
2011 /* R_SUBEQFILT PG 5 ADDR 0x01 */
2017 /* R_SUBMBCEN PG 5 ADDR 0x0A */
2021 /* R_SUBMBCCTL PG 5 ADDR 0x0B */
2028 /* R_SUBMBCMUG1 PG 5 ADDR 0x0C */
2030 SOC_SINGLE_TLV("Sub MBC 1 Make-Up Gain Volume", R_SUBMBCMUG1,
2033 /* R_SUBMBCTHR1 PG 5 ADDR 0x0D */
2037 /* R_SUBMBCRAT1 PG 5 ADDR 0x0E */
2039 /* R_SUBMBCATK1L PG 5 ADDR 0x0F */
2040 /* R_SUBMBCATK1H PG 5 ADDR 0x10 */
2042 /* R_SUBMBCREL1L PG 5 ADDR 0x11 */
2043 /* R_SUBMBCREL1H PG 5 ADDR 0x12 */
2045 /* R_SUBMBCMUG2 PG 5 ADDR 0x13 */
2047 SOC_SINGLE_TLV("Sub MBC 2 Make-Up Gain Volume", R_SUBMBCMUG2,
2050 /* R_SUBMBCTHR2 PG 5 ADDR 0x14 */
2054 /* R_SUBMBCRAT2 PG 5 ADDR 0x15 */
2056 /* R_SUBMBCATK2L PG 5 ADDR 0x16 */
2057 /* R_SUBMBCATK2H PG 5 ADDR 0x17 */
2059 /* R_SUBMBCREL2L PG 5 ADDR 0x18 */
2060 /* R_SUBMBCREL2H PG 5 ADDR 0x19 */
2062 /* R_SUBMBCMUG3 PG 5 ADDR 0x1A */
2064 SOC_SINGLE_TLV("Sub MBC 3 Make-Up Gain Volume", R_SUBMBCMUG3,
2067 /* R_SUBMBCTHR3 PG 5 ADDR 0x1B */
2071 /* R_SUBMBCRAT3 PG 5 ADDR 0x1C */
2073 /* R_SUBMBCATK3L PG 5 ADDR 0x1D */
2074 /* R_SUBMBCATK3H PG 5 ADDR 0x1E */
2076 /* R_SUBMBCREL3L PG 5 ADDR 0x1F */
2077 /* R_SUBMBCREL3H PG 5 ADDR 0x20 */
2079 /* R_SUBCLECTL PG 5 ADDR 0x21 */
2088 /* R_SUBCLEMUG PG 5 ADDR 0x22 */
2089 SOC_SINGLE_TLV("Sub CLE Make-Up Gain Volume", R_SUBCLEMUG,
2092 /* R_SUBCOMPTHR PG 5 ADDR 0x23 */
2096 /* R_SUBCOMPRAT PG 5 ADDR 0x24 */
2098 /* R_SUBCOMPATKL PG 5 ADDR 0x25 */
2099 /* R_SUBCOMPATKH PG 5 ADDR 0x26 */
2101 /* R_SUBCOMPRELL PG 5 ADDR 0x27 */
2102 /* R_SUBCOMPRELH PG 5 ADDR 0x28 */
2104 /* R_SUBLIMTHR PG 5 ADDR 0x29 */
2108 /* R_SUBLIMTGT PG 5 ADDR 0x2A */
2112 /* R_SUBLIMATKL PG 5 ADDR 0x2B */
2113 /* R_SUBLIMATKH PG 5 ADDR 0x2C */
2115 /* R_SUBLIMRELL PG 5 ADDR 0x2D */
2116 /* R_SUBLIMRELR PG 5 ADDR 0x2E */
2118 /* R_SUBEXPTHR PG 5 ADDR 0x2F */
2122 /* R_SUBEXPRAT PG 5 ADDR 0x30 */
2124 /* R_SUBEXPATKL PG 5 ADDR 0x31 */
2125 /* R_SUBEXPATKR PG 5 ADDR 0x32 */
2127 /* R_SUBEXPRELL PG 5 ADDR 0x33 */
2128 /* R_SUBEXPRELR PG 5 ADDR 0x34 */
2130 /* R_SUBFXCTL PG 5 ADDR 0x35 */
2143 COEFF_RAM_CTL("DAC Cascade 1 Left BiQuad 5", BIQUAD_SIZE, 0x14),
2150 COEFF_RAM_CTL("DAC Cascade 1 Right BiQuad 5", BIQUAD_SIZE, 0x34),
2160 COEFF_RAM_CTL("DAC Cascade 2 Left BiQuad 5", BIQUAD_SIZE, 0x54),
2167 COEFF_RAM_CTL("DAC Cascade 2 Right BiQuad 5", BIQUAD_SIZE, 0x74),
2214 COEFF_RAM_CTL("Speaker Cascade 1 Left BiQuad 5", BIQUAD_SIZE, 0x14),
2221 COEFF_RAM_CTL("Speaker Cascade 1 Right BiQuad 5", BIQUAD_SIZE, 0x34),
2231 COEFF_RAM_CTL("Speaker Cascade 2 Left BiQuad 5", BIQUAD_SIZE, 0x54),
2238 COEFF_RAM_CTL("Speaker Cascade 2 Right BiQuad 5", BIQUAD_SIZE, 0x74),
2285 COEFF_RAM_CTL("Sub Cascade 1 Left BiQuad 5", BIQUAD_SIZE, 0x14),
2292 COEFF_RAM_CTL("Sub Cascade 1 Right BiQuad 5", BIQUAD_SIZE, 0x34),
2302 COEFF_RAM_CTL("Sub Cascade 2 Left BiQuad 5", BIQUAD_SIZE, 0x54),
2309 COEFF_RAM_CTL("Sub Cascade 2 Right BiQuad 5", BIQUAD_SIZE, 0x74),
2369 SND_SOC_DAPM_ADC("Input Processor Channel 3", NULL,
2371 SND_SOC_DAPM_ADC("Input Processor Channel 2", NULL,
2373 SND_SOC_DAPM_ADC("Input Processor Channel 1", NULL,
2375 SND_SOC_DAPM_ADC("Input Processor Channel 0", NULL,
2438 SND_SOC_DAPM_MUX("Input Boost Channel 0 Mux", SND_SOC_NOPM, 0, 0,
2440 SND_SOC_DAPM_MUX("ADC Channel 0 Mux", SND_SOC_NOPM, 0, 0,
2442 SND_SOC_DAPM_MUX("Input Processor Channel 0 Mux", SND_SOC_NOPM, 0, 0,
2445 SND_SOC_DAPM_MUX("Input Boost Channel 1 Mux", SND_SOC_NOPM, 0, 0,
2447 SND_SOC_DAPM_MUX("ADC Channel 1 Mux", SND_SOC_NOPM, 0, 0,
2449 SND_SOC_DAPM_MUX("Input Processor Channel 1 Mux", SND_SOC_NOPM, 0, 0,
2548 {"Sub Mux", "CH 5", "CH 4_5 Mux"},
2549 {"Sub Mux", "CH 4 + 5", "CH 4_5 Mux"},
2556 {"Sub Mux", "ADC/DMic 1 Left", "Input Processor Channel 0"},
2557 {"Sub Mux", "ADC/DMic 1 Right", "Input Processor Channel 1"},
2558 {"Sub Mux", "ADC/DMic 1 Left Plus Right", "Input Processor Channel 0"},
2559 {"Sub Mux", "ADC/DMic 1 Left Plus Right", "Input Processor Channel 1"},
2574 {"Input Boost Channel 0 Mux", "Input 3", "Line In 3 Left"},
2575 {"Input Boost Channel 0 Mux", "Input 2", "Line In 2 Left"},
2576 {"Input Boost Channel 0 Mux", "Input 1", "Line In 1 Left"},
2577 {"Input Boost Channel 0 Mux", "D2S", "D2S 1"},
2579 {"Input Boost Channel 1 Mux", "Input 3", "Line In 3 Right"},
2580 {"Input Boost Channel 1 Mux", "Input 2", "Line In 2 Right"},
2581 {"Input Boost Channel 1 Mux", "Input 1", "Line In 1 Right"},
2582 {"Input Boost Channel 1 Mux", "D2S", "D2S 2"},
2584 {"ADC Channel 0 Mux", "Input 3 Boost Bypass", "Line In 3 Left"},
2585 {"ADC Channel 0 Mux", "Input 2 Boost Bypass", "Line In 2 Left"},
2586 {"ADC Channel 0 Mux", "Input 1 Boost Bypass", "Line In 1 Left"},
2587 {"ADC Channel 0 Mux", "Input Boost", "Input Boost Channel 0 Mux"},
2589 {"ADC Channel 1 Mux", "Input 3 Boost Bypass", "Line In 3 Right"},
2590 {"ADC Channel 1 Mux", "Input 2 Boost Bypass", "Line In 2 Right"},
2591 {"ADC Channel 1 Mux", "Input 1 Boost Bypass", "Line In 1 Right"},
2592 {"ADC Channel 1 Mux", "Input Boost", "Input Boost Channel 1 Mux"},
2594 {"Input Processor Channel 0 Mux", "ADC", "ADC Channel 0 Mux"},
2595 {"Input Processor Channel 0 Mux", "DMic", "DMic 1"},
2597 {"Input Processor Channel 0", NULL, "PLLs"},
2598 {"Input Processor Channel 0", NULL, "Input Processor Channel 0 Mux"},
2600 {"Input Processor Channel 1 Mux", "ADC", "ADC Channel 1 Mux"},
2601 {"Input Processor Channel 1 Mux", "DMic", "DMic 1"},
2603 {"Input Processor Channel 1", NULL, "PLLs"},
2604 {"Input Processor Channel 1", NULL, "Input Processor Channel 1 Mux"},
2606 {"Input Processor Channel 2", NULL, "PLLs"},
2607 {"Input Processor Channel 2", NULL, "DMic 2"},
2609 {"Input Processor Channel 3", NULL, "PLLs"},
2610 {"Input Processor Channel 3", NULL, "DMic 2"},
2612 {"DAI 1 Out Mux", "ADC/DMic 1", "Input Processor Channel 0"},
2613 {"DAI 1 Out Mux", "ADC/DMic 1", "Input Processor Channel 1"},
2614 {"DAI 1 Out Mux", "DMic 2", "Input Processor Channel 2"},
2615 {"DAI 1 Out Mux", "DMic 2", "Input Processor Channel 3"},
2617 {"DAI 2 Out Mux", "ADC/DMic 1", "Input Processor Channel 0"},
2618 {"DAI 2 Out Mux", "ADC/DMic 1", "Input Processor Channel 1"},
2619 {"DAI 2 Out Mux", "DMic 2", "Input Processor Channel 2"},
2620 {"DAI 2 Out Mux", "DMic 2", "Input Processor Channel 3"},
2622 {"DAI 3 Out Mux", "ADC/DMic 1", "Input Processor Channel 0"},
2623 {"DAI 3 Out Mux", "ADC/DMic 1", "Input Processor Channel 1"},
2624 {"DAI 3 Out Mux", "DMic 2", "Input Processor Channel 2"},
2625 {"DAI 3 Out Mux", "DMic 2", "Input Processor Channel 3"},
2636 struct snd_soc_component *component = dai->component; in tscs454_set_sysclk()
2641 dev_dbg(component->dev, "%s(): freq = %u\n", __func__, freq); in tscs454_set_sysclk()
2646 if (bclk_dai != dai->id) in tscs454_set_sysclk()
2649 tscs454->bclk_freq = freq; in tscs454_set_sysclk()
2658 struct snd_soc_component *component = dai->component; in tscs454_set_bclk_ratio()
2662 dev_dbg(component->dev, "set_bclk_ratio() id = %d ratio = %u\n", in tscs454_set_bclk_ratio()
2663 dai->id, ratio); in tscs454_set_bclk_ratio()
2665 switch (dai->id) { in tscs454_set_bclk_ratio()
2679 ret = -EINVAL; in tscs454_set_bclk_ratio()
2680 dev_err(component->dev, "Unknown audio interface (%d)\n", ret); in tscs454_set_bclk_ratio()
2695 ret = -EINVAL; in tscs454_set_bclk_ratio()
2696 dev_err(component->dev, "Unsupported bclk ratio (%d)\n", ret); in tscs454_set_bclk_ratio()
2703 dev_err(component->dev, in tscs454_set_bclk_ratio()
2718 aif->provider = true; in set_aif_provider_from_fmt()
2721 aif->provider = false; in set_aif_provider_from_fmt()
2724 ret = -EINVAL; in set_aif_provider_from_fmt()
2725 dev_err(component->dev, "Unsupported format (%d)\n", ret); in set_aif_provider_from_fmt()
2749 ret = -EINVAL; in set_aif_tdm_delay()
2750 dev_err(component->dev, in set_aif_tdm_delay()
2757 dev_err(component->dev, "Failed to setup tdm format (%d)\n", in set_aif_tdm_delay()
2783 ret = -EINVAL; in set_aif_format_from_fmt()
2784 dev_err(component->dev, in set_aif_format_from_fmt()
2812 ret = -EINVAL; in set_aif_format_from_fmt()
2813 dev_err(component->dev, "Format unsupported (%d)\n", ret); in set_aif_format_from_fmt()
2820 dev_err(component->dev, "Failed to set DAI %d format (%d)\n", in set_aif_format_from_fmt()
2847 ret = -EINVAL; in set_aif_clock_format_from_fmt()
2848 dev_err(component->dev, in set_aif_clock_format_from_fmt()
2867 ret = -EINVAL; in set_aif_clock_format_from_fmt()
2868 dev_err(component->dev, "Format unknown (%d)\n", ret); in set_aif_clock_format_from_fmt()
2875 dev_err(component->dev, in set_aif_clock_format_from_fmt()
2886 struct snd_soc_component *component = dai->component; in tscs454_set_dai_fmt()
2888 struct aif *aif = &tscs454->aifs[dai->id]; in tscs454_set_dai_fmt()
2895 ret = set_aif_format_from_fmt(component, dai->id, fmt); in tscs454_set_dai_fmt()
2899 ret = set_aif_clock_format_from_fmt(component, dai->id, fmt); in tscs454_set_dai_fmt()
2910 struct snd_soc_component *component = dai->component; in tscs454_dai1_set_tdm_slot()
2918 ret = -EINVAL; in tscs454_dai1_set_tdm_slot()
2919 dev_err(component->dev, "Invalid TDM slot mask (%d)\n", ret); in tscs454_dai1_set_tdm_slot()
2934 ret = -EINVAL; in tscs454_dai1_set_tdm_slot()
2935 dev_err(component->dev, "Invalid number of slots (%d)\n", ret); in tscs454_dai1_set_tdm_slot()
2950 ret = -EINVAL; in tscs454_dai1_set_tdm_slot()
2951 dev_err(component->dev, "Invalid TDM slot width (%d)\n", ret); in tscs454_dai1_set_tdm_slot()
2956 dev_err(component->dev, "Failed to set slots (%d)\n", ret); in tscs454_dai1_set_tdm_slot()
2967 struct snd_soc_component *component = dai->component; in tscs454_dai23_set_tdm_slot()
2976 ret = -EINVAL; in tscs454_dai23_set_tdm_slot()
2977 dev_err(component->dev, "Invalid TDM slot mask (%d)\n", ret); in tscs454_dai23_set_tdm_slot()
2981 switch (dai->id) { in tscs454_dai23_set_tdm_slot()
2989 ret = -EINVAL; in tscs454_dai23_set_tdm_slot()
2990 dev_err(component->dev, "Unrecognized interface %d (%d)\n", in tscs454_dai23_set_tdm_slot()
2991 dai->id, ret); in tscs454_dai23_set_tdm_slot()
3003 ret = -EINVAL; in tscs454_dai23_set_tdm_slot()
3004 dev_err(component->dev, "Invalid number of slots (%d)\n", ret); in tscs454_dai23_set_tdm_slot()
3019 ret = -EINVAL; in tscs454_dai23_set_tdm_slot()
3020 dev_err(component->dev, "Invalid TDM slot width (%d)\n", ret); in tscs454_dai23_set_tdm_slot()
3025 dev_err(component->dev, "Failed to set slots (%d)\n", ret); in tscs454_dai23_set_tdm_slot()
3083 ret = -EINVAL; in set_aif_fs()
3084 dev_err(component->dev, "Unsupported sample rate (%d)\n", ret); in set_aif_fs()
3099 ret = -EINVAL; in set_aif_fs()
3100 dev_err(component->dev, "DAI ID not recognized (%d)\n", ret); in set_aif_fs()
3107 dev_err(component->dev, in set_aif_fs()
3137 ret = -EINVAL; in set_aif_sample_format()
3138 dev_err(component->dev, "Unsupported format width (%d)\n", ret); in set_aif_sample_format()
3153 ret = -EINVAL; in set_aif_sample_format()
3154 dev_err(component->dev, "AIF ID not recognized (%d)\n", ret); in set_aif_sample_format()
3161 dev_err(component->dev, in set_aif_sample_format()
3173 struct snd_soc_component *component = dai->component; in tscs454_hw_params()
3176 struct aif *aif = &tscs454->aifs[dai->id]; in tscs454_hw_params()
3180 mutex_lock(&tscs454->aifs_status_lock); in tscs454_hw_params()
3182 dev_dbg(component->dev, "%s(): aif %d fs = %u\n", __func__, in tscs454_hw_params()
3183 aif->id, fs); in tscs454_hw_params()
3185 if (!aif_active(&tscs454->aifs_status, aif->id)) { in tscs454_hw_params()
3187 aif->pll = &tscs454->pll1; in tscs454_hw_params()
3189 aif->pll = &tscs454->pll2; in tscs454_hw_params()
3191 dev_dbg(component->dev, "Reserving pll %d for aif %d\n", in tscs454_hw_params()
3192 aif->pll->id, aif->id); in tscs454_hw_params()
3194 reserve_pll(aif->pll); in tscs454_hw_params()
3197 if (!aifs_active(&tscs454->aifs_status)) { /* First active aif */ in tscs454_hw_params()
3200 tscs454->internal_rate.pll = &tscs454->pll1; in tscs454_hw_params()
3202 tscs454->internal_rate.pll = &tscs454->pll2; in tscs454_hw_params()
3204 dev_dbg(component->dev, "Reserving pll %d for ir\n", in tscs454_hw_params()
3205 tscs454->internal_rate.pll->id); in tscs454_hw_params()
3207 reserve_pll(tscs454->internal_rate.pll); in tscs454_hw_params()
3210 ret = set_aif_fs(component, aif->id, fs); in tscs454_hw_params()
3212 dev_err(component->dev, "Failed to set aif fs (%d)\n", ret); in tscs454_hw_params()
3216 ret = set_aif_sample_format(component, params_format(params), aif->id); in tscs454_hw_params()
3218 dev_err(component->dev, in tscs454_hw_params()
3223 set_aif_status_active(&tscs454->aifs_status, aif->id, in tscs454_hw_params()
3224 substream->stream == SNDRV_PCM_STREAM_PLAYBACK); in tscs454_hw_params()
3226 dev_dbg(component->dev, "Set aif %d active. Streams status is 0x%x\n", in tscs454_hw_params()
3227 aif->id, tscs454->aifs_status.streams); in tscs454_hw_params()
3231 mutex_unlock(&tscs454->aifs_status_lock); in tscs454_hw_params()
3239 struct snd_soc_component *component = dai->component; in tscs454_hw_free()
3241 struct aif *aif = &tscs454->aifs[dai->id]; in tscs454_hw_free()
3244 substream->stream == SNDRV_PCM_STREAM_PLAYBACK); in tscs454_hw_free()
3251 struct snd_soc_component *component = dai->component; in tscs454_prepare()
3253 struct aif *aif = &tscs454->aifs[dai->id]; in tscs454_prepare()
3288 switch (tscs454->sysclk_src_id) { in tscs454_probe()
3302 ret = -EINVAL; in tscs454_probe()
3303 dev_err(component->dev, "Invalid sysclk src id (%d)\n", ret); in tscs454_probe()
3310 dev_err(component->dev, "Failed to set PLL input (%d)\n", ret); in tscs454_probe()
3314 if (tscs454->sysclk_src_id < PLL_INPUT_BCLK) in tscs454_probe()
3339 .name = "tscs454-dai1",
3359 .name = "tscs454-dai2",
3379 .name = "tscs454-dai3",
3409 tscs454 = devm_kzalloc(&i2c->dev, sizeof(*tscs454), GFP_KERNEL); in tscs454_i2c_probe()
3411 return -ENOMEM; in tscs454_i2c_probe()
3420 tscs454->sysclk = devm_clk_get(&i2c->dev, src_names[src]); in tscs454_i2c_probe()
3421 if (!IS_ERR(tscs454->sysclk)) { in tscs454_i2c_probe()
3423 } else if (PTR_ERR(tscs454->sysclk) != -ENOENT) { in tscs454_i2c_probe()
3424 ret = PTR_ERR(tscs454->sysclk); in tscs454_i2c_probe()
3425 dev_err(&i2c->dev, "Failed to get sysclk (%d)\n", ret); in tscs454_i2c_probe()
3429 dev_dbg(&i2c->dev, "PLL input is %s\n", src_names[src]); in tscs454_i2c_probe()
3430 tscs454->sysclk_src_id = src; in tscs454_i2c_probe()
3432 ret = regmap_write(tscs454->regmap, in tscs454_i2c_probe()
3435 dev_err(&i2c->dev, "Failed to reset the component (%d)\n", ret); in tscs454_i2c_probe()
3438 regcache_mark_dirty(tscs454->regmap); in tscs454_i2c_probe()
3440 ret = regmap_register_patch(tscs454->regmap, tscs454_patch, in tscs454_i2c_probe()
3443 dev_err(&i2c->dev, "Failed to apply patch (%d)\n", ret); in tscs454_i2c_probe()
3447 regmap_write(tscs454->regmap, R_PAGESEL, 0x00); in tscs454_i2c_probe()
3449 ret = devm_snd_soc_register_component(&i2c->dev, &soc_component_dev_tscs454, in tscs454_i2c_probe()
3452 dev_err(&i2c->dev, "Failed to register component (%d)\n", ret); in tscs454_i2c_probe()