Lines Matching +full:pga +full:- +full:gain
1 // SPDX-License-Identifier: GPL-2.0-only
16 * ---------------------------------------
17 * MONO_LOUT -> N/A | MONO_LOUT -> N/A
18 * | IN1L -> LINE1L
19 * | IN1R -> LINE1R
20 * | IN2L -> LINE2L
21 * | IN2R -> LINE2R
22 * | MIC3L/R -> N/A
25 * ---------------------------------------
89 /* Output Common-Mode Voltage */
125 /* Class-D speaker driver init; datasheet p. 46 */
169 (struct soc_mixer_control *)kcontrol->private_value;
170 unsigned int reg = mc->reg;
171 unsigned int shift = mc->shift;
172 int max = mc->max;
173 unsigned int mask = (1 << fls(max)) - 1;
174 unsigned int invert = mc->invert;
179 val = (ucontrol->value.integer.value[0] & mask);
188 val = mask - val;
219 struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm);
227 aic3x->micbias_vg << MICBIAS_LEVEL_SHIFT);
249 "differential of HPLOUT", "constant VCM", "single-ended" };
254 "differential of HPROUT", "constant VCM", "single-ended",
260 "single-ended", "differential" };
280 "-5.5dB", "-8dB", "-10dB", "-12dB",
281 "-14dB", "-17dB", "-20dB", "-24dB" };
312 * DAC digital volumes. From -63.5 to 0 dB in 0.5 dB steps
314 static DECLARE_TLV_DB_SCALE(dac_tlv, -6350, 50, 0);
315 /* ADC PGA gain volumes. From 0 to 59.5 dB in 0.5 dB steps */
318 * Output stage volumes. From -78.3 to 0 dB. Muted below -78.3 dB.
321 * Define dB scale so that it is mostly correct for range about -55 to 0 dB
323 * so much). This setting shows -50 dB (actual is -50.3 dB) for register
324 * value 100 and -58.5 dB (actual is -78.3 dB) for register value 117.
326 static DECLARE_TLV_DB_SCALE(output_stage_tlv, -5900, 50, 1);
338 * only for swapped L-to-R and R-to-L routes. See below stereo controls
339 * for direct L-to-L and R-to-R routes.
371 /* Stereo output controls for direct L-to-L and R-to-R routes */
372 SOC_DOUBLE_R_TLV("Line PGA Bypass Volume",
379 SOC_DOUBLE_R_TLV("HP PGA Bypass Volume",
386 SOC_DOUBLE_R_TLV("HPCOM PGA Bypass Volume",
408 * Note: enable Automatic input Gain Controller with care. It can
409 * adjust PGA to max value when ADC is on and will never go back.
419 /* De-emphasis */
420 SOC_DOUBLE("De-emphasis Switch", AIC3X_CODEC_DFILT_CTRL, 2, 0, 0x01, 0),
423 SOC_DOUBLE_R_TLV("PGA Capture Volume", LADC_VOL, RADC_VOL,
425 SOC_DOUBLE_R("PGA Capture Switch", LADC_VOL, RADC_VOL, 7, 0x01, 1),
427 SOC_ENUM("ADC HPF Cut-off", aic3x_adc_hpf_enum),
430 SOC_ENUM("Output Driver Power-On time", aic3x_poweron_time_enum),
431 SOC_ENUM("Output Driver Ramp-up step", aic3x_rampup_step_enum),
438 * only for swapped L-to-R and R-to-L routes. See below stereo controls
439 * for direct L-to-L and R-to-R routes.
459 /* Stereo output controls for direct L-to-L and R-to-R routes */
477 SOC_DOUBLE_R_TLV("Mono PGA Bypass Volume",
491 * Class-D amplifier gain. From 0 to 18 dB in 6 dB steps
496 SOC_DOUBLE_TLV("Class-D Playback Volume", CLASSD_CTRL, 6, 4, 3, 0, classd_amp_tlv);
590 /* Left PGA Mixer */
599 /* Right PGA Mixer */
608 /* Left PGA Mixer for tlv320aic3104 */
616 /* Right PGA Mixer for tlv320aic3104 */
707 SND_SOC_DAPM_MIXER("Left PGA Mixer", SND_SOC_NOPM, 0, 0,
714 SND_SOC_DAPM_MIXER("Right PGA Mixer", SND_SOC_NOPM, 0, 0,
770 SND_SOC_DAPM_MIXER("Left PGA Mixer", SND_SOC_NOPM, 0, 0,
775 SND_SOC_DAPM_MIXER("Right PGA Mixer", SND_SOC_NOPM, 0, 0,
782 ARRAY_SIZE(aic3x_left_line_mixer_controls) - 2),
785 ARRAY_SIZE(aic3x_right_line_mixer_controls) - 2),
788 ARRAY_SIZE(aic3x_left_hp_mixer_controls) - 2),
791 ARRAY_SIZE(aic3x_right_hp_mixer_controls) - 2),
794 ARRAY_SIZE(aic3x_left_hpcom_mixer_controls) - 2),
797 ARRAY_SIZE(aic3x_right_hpcom_mixer_controls) - 2),
815 /* Class-D outputs */
816 SND_SOC_DAPM_PGA("Left Class-D Out", CLASSD_CTRL, 3, 0, NULL, 0),
817 SND_SOC_DAPM_PGA("Right Class-D Out", CLASSD_CTRL, 2, 0, NULL, 0),
825 {"Left Line1L Mux", "single-ended", "LINE1L"},
827 {"Left Line1R Mux", "single-ended", "LINE1R"},
830 {"Left PGA Mixer", "Line1L Switch", "Left Line1L Mux"},
831 {"Left PGA Mixer", "Line1R Switch", "Left Line1R Mux"},
833 {"Left ADC", NULL, "Left PGA Mixer"},
836 {"Right Line1R Mux", "single-ended", "LINE1R"},
838 {"Right Line1L Mux", "single-ended", "LINE1L"},
841 {"Right PGA Mixer", "Line1L Switch", "Right Line1L Mux"},
842 {"Right PGA Mixer", "Line1R Switch", "Right Line1R Mux"},
844 {"Right ADC", NULL, "Right PGA Mixer"},
857 {"Left Line Mixer", "PGAL Bypass Switch", "Left PGA Mixer"},
859 {"Left Line Mixer", "PGAR Bypass Switch", "Right PGA Mixer"},
867 {"Right Line Mixer", "PGAL Bypass Switch", "Left PGA Mixer"},
869 {"Right Line Mixer", "PGAR Bypass Switch", "Right PGA Mixer"},
877 {"Left HP Mixer", "PGAL Bypass Switch", "Left PGA Mixer"},
879 {"Left HP Mixer", "PGAR Bypass Switch", "Right PGA Mixer"},
887 {"Right HP Mixer", "PGAL Bypass Switch", "Left PGA Mixer"},
889 {"Right HP Mixer", "PGAR Bypass Switch", "Right PGA Mixer"},
897 {"Left HPCOM Mixer", "PGAL Bypass Switch", "Left PGA Mixer"},
899 {"Left HPCOM Mixer", "PGAR Bypass Switch", "Right PGA Mixer"},
904 {"Left HPCOM Mux", "single-ended", "Left HPCOM Mixer"},
909 {"Right HPCOM Mixer", "PGAL Bypass Switch", "Left PGA Mixer"},
911 {"Right HPCOM Mixer", "PGAR Bypass Switch", "Right PGA Mixer"},
916 {"Right HPCOM Mux", "single-ended", "Right HPCOM Mixer"},
926 {"Left Line2L Mux", "single-ended", "LINE2L"},
929 {"Left PGA Mixer", "Line2L Switch", "Left Line2L Mux"},
930 {"Left PGA Mixer", "Mic3L Switch", "MIC3L"},
931 {"Left PGA Mixer", "Mic3R Switch", "MIC3R"},
936 {"Right Line2R Mux", "single-ended", "LINE2R"},
939 {"Right PGA Mixer", "Line2R Switch", "Right Line2R Mux"},
940 {"Right PGA Mixer", "Mic3L Switch", "MIC3L"},
941 {"Right PGA Mixer", "Mic3R Switch", "MIC3R"},
981 {"Left PGA Mixer", "Mic2L Switch", "MIC2L"},
982 {"Left PGA Mixer", "Mic2R Switch", "MIC2R"},
985 {"Right PGA Mixer", "Mic2L Switch", "MIC2L"},
986 {"Right PGA Mixer", "Mic2R Switch", "MIC2R"},
992 {"Mono Mixer", "PGAL Bypass Switch", "Left PGA Mixer"},
995 {"Mono Mixer", "PGAR Bypass Switch", "Right PGA Mixer"},
1002 /* Class-D outputs */
1003 {"Left Class-D Out", NULL, "Left Line Out"},
1004 {"Right Class-D Out", NULL, "Left Line Out"},
1005 {"SPOP", NULL, "Left Class-D Out"},
1006 {"SPOM", NULL, "Right Class-D Out"},
1014 switch (aic3x->model) {
1052 struct snd_soc_component *component = dai->component;
1058 int width = aic3x->slot_width;
1086 if (aic3x->sysclk / (128 * pll_q) == fsref) {
1118 data -= 2;
1131 codec_clk = (2048 * fsref) / (aic3x->sysclk / 1000);
1145 if (abs(codec_clk - tmp_clk) <
1146 abs(codec_clk - last_clk)) {
1166 d = ((2048 * p * fsref) - j * aic3x->sysclk)
1167 * 100 / (aic3x->sysclk/100);
1173 if (abs(codec_clk - clk) < abs(codec_clk - last_clk)) {
1185 return -EINVAL;
1204 struct snd_soc_component *component = dai->component;
1207 int width = aic3x->slot_width;
1210 width = substream->runtime->sample_bits;
1213 if (aic3x->dai_fmt == SND_SOC_DAIFMT_DSP_A)
1214 delay += (aic3x->tdm_delay*width + 1);
1215 else if (aic3x->dai_fmt == SND_SOC_DAIFMT_DSP_B)
1216 delay += aic3x->tdm_delay*width;
1226 struct snd_soc_component *component = dai->component;
1244 struct snd_soc_component *component = codec_dai->component;
1253 aic3x->sysclk = freq;
1260 struct snd_soc_component *component = codec_dai->component;
1269 aic3x->master = 1;
1273 aic3x->master = 0;
1277 aic3x->master = 1;
1282 aic3x->master = 1;
1287 return -EINVAL;
1309 return -EINVAL;
1312 aic3x->dai_fmt = fmt & SND_SOC_DAIFMT_FORMAT_MASK;
1325 struct snd_soc_component *component = codec_dai->component;
1330 dev_err(component->dev, "tx and rx masks must be symmetric\n");
1331 return -EINVAL;
1335 dev_err(component->dev, "tx and rx masks need to be non 0\n");
1336 return -EINVAL;
1342 dev_err(component->dev, "Invalid mask, slots must be adjacent\n");
1343 return -EINVAL;
1353 dev_err(component->dev, "Unsupported slot width %d\n", slot_width);
1354 return -EINVAL;
1358 aic3x->tdm_delay = lsb;
1359 aic3x->slot_width = slot_width;
1361 /* DOUT in high-impedance on inactive bit clocks */
1373 struct aic3x_priv *aic3x = disable_nb->aic3x;
1380 if (aic3x->gpio_reset)
1381 gpiod_set_value(aic3x->gpio_reset, 1);
1382 regcache_mark_dirty(aic3x->regmap);
1395 ret = regulator_bulk_enable(ARRAY_SIZE(aic3x->supplies),
1396 aic3x->supplies);
1399 aic3x->power = 1;
1401 if (aic3x->gpio_reset) {
1403 gpiod_set_value(aic3x->gpio_reset, 0);
1406 if (aic3x->model == AIC3X_MODEL_3007)
1407 regmap_multi_reg_write_bypassed(aic3x->regmap, aic3007_class_d,
1411 regcache_cache_only(aic3x->regmap, false);
1412 regcache_sync(aic3x->regmap);
1427 * Delay is needed to reduce pop-noise after syncing back the
1438 regcache_mark_dirty(aic3x->regmap);
1439 aic3x->power = 0;
1441 regcache_cache_only(aic3x->regmap, true);
1442 ret = regulator_bulk_disable(ARRAY_SIZE(aic3x->supplies),
1443 aic3x->supplies);
1459 aic3x->master) {
1466 if (!aic3x->power)
1469 aic3x->master) {
1476 if (aic3x->power)
1500 .name = "tlv320aic3x-hifi",
1526 /* PGA to Mono Line Out default volume, disconnect from Output Mixer */
1570 /* By default route Line1 to ADC PGA mixer */
1574 /* PGA to HP Bypass default volume, disconnect from Output Mixer */
1579 /* PGA to Line Out default volume, disconnect from Output Mixer */
1584 if (aic3x->model != AIC3X_MODEL_3104) {
1595 switch (aic3x->model) {
1606 /* Output common-mode voltage = 1.5 V */
1608 aic3x->ocmv << HPOUT_SC_OCMV_SHIFT);
1618 aic3x->component = component;
1620 for (i = 0; i < ARRAY_SIZE(aic3x->supplies); i++) {
1621 aic3x->disable_nb[i].nb.notifier_call = aic3x_regulator_event;
1622 aic3x->disable_nb[i].aic3x = aic3x;
1624 aic3x->supplies[i].consumer,
1625 &aic3x->disable_nb[i].nb);
1627 dev_err(component->dev,
1634 regcache_mark_dirty(aic3x->regmap);
1637 if (aic3x->setup) {
1638 if (aic3x->model != AIC3X_MODEL_3104) {
1641 (aic3x->setup->gpio_func[0] & 0xf) << 4);
1643 (aic3x->setup->gpio_func[1] & 0xf) << 4);
1645 dev_warn(component->dev, "GPIO functionality is not supported on tlv320aic3104\n");
1649 switch (aic3x->model) {
1669 switch (aic3x->micbias_vg) {
1675 (aic3x->micbias_vg) << MICBIAS_LEVEL_SHIFT);
1706 struct device_node *np = dev->of_node;
1710 if (np && !of_property_read_u32(np, "ai3x-ocmv", &value)) {
1713 aic3x->ocmv = value;
1718 dvdd = regulator_get_voltage(aic3x->supplies[1].consumer);
1719 avdd = regulator_get_voltage(aic3x->supplies[2].consumer);
1726 aic3x->ocmv = HPOUT_SC_OCMV_1_8V;
1728 aic3x->ocmv = HPOUT_SC_OCMV_1_65V;
1730 aic3x->ocmv = HPOUT_SC_OCMV_1_5V;
1732 aic3x->ocmv = HPOUT_SC_OCMV_1_35V;
1744 struct device_node *np = dev->of_node;
1750 return -ENOMEM;
1752 aic3x->regmap = regmap;
1753 if (IS_ERR(aic3x->regmap)) {
1754 ret = PTR_ERR(aic3x->regmap);
1758 regcache_cache_only(aic3x->regmap, true);
1764 return -ENOMEM;
1766 if (of_property_read_u32_array(np, "ai3x-gpio-func",
1767 ai3x_setup->gpio_func, 2) >= 0) {
1768 aic3x->setup = ai3x_setup;
1771 if (!of_property_read_u32(np, "ai3x-micbias-vg", &value)) {
1774 aic3x->micbias_vg = AIC3X_MICBIAS_2_0V;
1777 aic3x->micbias_vg = AIC3X_MICBIAS_2_5V;
1780 aic3x->micbias_vg = AIC3X_MICBIAS_AVDDV;
1783 aic3x->micbias_vg = AIC3X_MICBIAS_OFF;
1788 aic3x->micbias_vg = AIC3X_MICBIAS_OFF;
1792 aic3x->model = driver_data;
1794 aic3x->gpio_reset = devm_gpiod_get_optional(dev, "reset",
1796 ret = PTR_ERR_OR_ZERO(aic3x->gpio_reset);
1798 if (ret != -EBUSY)
1803 * its reset line. Try to get it non-exclusively, although
1808 aic3x->gpio_reset = devm_gpiod_get(dev, "reset",
1810 ret = PTR_ERR_OR_ZERO(aic3x->gpio_reset);
1814 aic3x->shared_reset = true;
1817 gpiod_set_consumer_name(aic3x->gpio_reset, "tlv320aic3x reset");
1819 for (i = 0; i < ARRAY_SIZE(aic3x->supplies); i++)
1820 aic3x->supplies[i].supply = aic3x_supply_names[i];
1822 ret = devm_regulator_bulk_get(dev, ARRAY_SIZE(aic3x->supplies),
1823 aic3x->supplies);
1842 if (aic3x->gpio_reset && !aic3x->shared_reset)
1843 gpiod_set_value(aic3x->gpio_reset, 1);