1 /* SPDX-License-Identifier: GPL-2.0
10 #include <linux/clk-provider.h>
26  * struct clk_aic32x4_pll_muldiv - Multiplier/divider settings
49 	struct clk_aic32x4 *pll = to_clk_aic32x4(hw);  in clk_aic32x4_pll_prepare()  local
51 	return regmap_update_bits(pll->regmap, AIC32X4_PLLPR,  in clk_aic32x4_pll_prepare()
57 	struct clk_aic32x4 *pll = to_clk_aic32x4(hw);  in clk_aic32x4_pll_unprepare()  local
59 	regmap_update_bits(pll->regmap, AIC32X4_PLLPR,  in clk_aic32x4_pll_unprepare()
65 	struct clk_aic32x4 *pll = to_clk_aic32x4(hw);  in clk_aic32x4_pll_is_prepared()  local
70 	ret = regmap_read(pll->regmap, AIC32X4_PLLPR, &val);  in clk_aic32x4_pll_is_prepared()
77 static int clk_aic32x4_pll_get_muldiv(struct clk_aic32x4 *pll,  in clk_aic32x4_pll_get_muldiv()  argument
84 	ret = regmap_read(pll->regmap, AIC32X4_PLLPR, &val);  in clk_aic32x4_pll_get_muldiv()
87 	settings->r = val & AIC32X4_PLL_R_MASK;  in clk_aic32x4_pll_get_muldiv()
88 	settings->p = (val & AIC32X4_PLL_P_MASK) >> AIC32X4_PLL_P_SHIFT;  in clk_aic32x4_pll_get_muldiv()
90 	ret = regmap_read(pll->regmap, AIC32X4_PLLJ, &val);  in clk_aic32x4_pll_get_muldiv()
93 	settings->j = val;  in clk_aic32x4_pll_get_muldiv()
95 	ret = regmap_read(pll->regmap, AIC32X4_PLLDMSB, &val);  in clk_aic32x4_pll_get_muldiv()
98 	settings->d = val << 8;  in clk_aic32x4_pll_get_muldiv()
100 	ret = regmap_read(pll->regmap, AIC32X4_PLLDLSB,	 &val);  in clk_aic32x4_pll_get_muldiv()
103 	settings->d |= val;  in clk_aic32x4_pll_get_muldiv()
108 static int clk_aic32x4_pll_set_muldiv(struct clk_aic32x4 *pll,  in clk_aic32x4_pll_set_muldiv()  argument
114 	ret = regmap_update_bits(pll->regmap, AIC32X4_PLLPR,  in clk_aic32x4_pll_set_muldiv()
115 				AIC32X4_PLL_R_MASK, settings->r);  in clk_aic32x4_pll_set_muldiv()
119 	ret = regmap_update_bits(pll->regmap, AIC32X4_PLLPR,  in clk_aic32x4_pll_set_muldiv()
121 				settings->p << AIC32X4_PLL_P_SHIFT);  in clk_aic32x4_pll_set_muldiv()
125 	ret = regmap_write(pll->regmap, AIC32X4_PLLJ, settings->j);  in clk_aic32x4_pll_set_muldiv()
129 	ret = regmap_write(pll->regmap, AIC32X4_PLLDMSB, (settings->d >> 8));  in clk_aic32x4_pll_set_muldiv()
132 	ret = regmap_write(pll->regmap, AIC32X4_PLLDLSB, (settings->d & 0xff));  in clk_aic32x4_pll_set_muldiv()
146 	 * it back out later.  in clk_aic32x4_pll_calc_rate()
148 	rate = (u64) parent_rate * settings->r *  in clk_aic32x4_pll_calc_rate()
149 				((settings->j * 10000) + settings->d);  in clk_aic32x4_pll_calc_rate()
151 	return (unsigned long) DIV_ROUND_UP_ULL(rate, settings->p * 10000);  in clk_aic32x4_pll_calc_rate()
159 	settings->p = parent_rate / AIC32X4_MAX_PLL_CLKIN + 1;  in clk_aic32x4_pll_calc_muldiv()
160 	if (settings->p > 8)  in clk_aic32x4_pll_calc_muldiv()
161 		return -1;  in clk_aic32x4_pll_calc_muldiv()
168 	multiplier = (u64) rate * settings->p * 10000;  in clk_aic32x4_pll_calc_muldiv()
175 	settings->r = ((u32) multiplier / 640000) + 1;  in clk_aic32x4_pll_calc_muldiv()
176 	if (settings->r > 4)  in clk_aic32x4_pll_calc_muldiv()
177 		return -1;  in clk_aic32x4_pll_calc_muldiv()
178 	do_div(multiplier, settings->r);  in clk_aic32x4_pll_calc_muldiv()
184 		return -1;  in clk_aic32x4_pll_calc_muldiv()
186 	/* Figure out the integer part, J, and the fractional part, D. */  in clk_aic32x4_pll_calc_muldiv()
187 	settings->j = (u32) multiplier / 10000;  in clk_aic32x4_pll_calc_muldiv()
188 	settings->d = (u32) multiplier % 10000;  in clk_aic32x4_pll_calc_muldiv()
196 	struct clk_aic32x4 *pll = to_clk_aic32x4(hw);  in clk_aic32x4_pll_recalc_rate()  local
200 	ret =  clk_aic32x4_pll_get_muldiv(pll, &settings);  in clk_aic32x4_pll_recalc_rate()
213 	ret = clk_aic32x4_pll_calc_muldiv(&settings, req->rate, req->best_parent_rate);  in clk_aic32x4_pll_determine_rate()
215 		return -EINVAL;  in clk_aic32x4_pll_determine_rate()
217 	req->rate = clk_aic32x4_pll_calc_rate(&settings, req->best_parent_rate);  in clk_aic32x4_pll_determine_rate()
226 	struct clk_aic32x4 *pll = to_clk_aic32x4(hw);  in clk_aic32x4_pll_set_rate()  local
232 		return -EINVAL;  in clk_aic32x4_pll_set_rate()
234 	ret = clk_aic32x4_pll_set_muldiv(pll, &settings);  in clk_aic32x4_pll_set_rate()
246 	struct clk_aic32x4 *pll = to_clk_aic32x4(hw);  in clk_aic32x4_pll_set_parent()  local
248 	return regmap_update_bits(pll->regmap,  in clk_aic32x4_pll_set_parent()
256 	struct clk_aic32x4 *pll = to_clk_aic32x4(hw);  in clk_aic32x4_pll_get_parent()  local
259 	regmap_read(pll->regmap, AIC32X4_PLLPR, &val);  in clk_aic32x4_pll_get_parent()
280 	return regmap_update_bits(mux->regmap,  in clk_aic32x4_codec_clkin_set_parent()
290 	regmap_read(mux->regmap, AIC32X4_CLKMUX, &val);  in clk_aic32x4_codec_clkin_get_parent()
305 	return regmap_update_bits(div->regmap, div->reg,  in clk_aic32x4_div_prepare()
313 	regmap_update_bits(div->regmap, div->reg,  in clk_aic32x4_div_unprepare()
325 		return -EINVAL;  in clk_aic32x4_div_set_rate()
327 	return regmap_update_bits(div->regmap, div->reg,  in clk_aic32x4_div_set_rate()
336 	divisor = DIV_ROUND_UP(req->best_parent_rate, req->rate);  in clk_aic32x4_div_determine_rate()
338 		return -EINVAL;  in clk_aic32x4_div_determine_rate()
340 	req->rate = DIV_ROUND_UP(req->best_parent_rate, divisor);  in clk_aic32x4_div_determine_rate()
351 	err = regmap_read(div->regmap, div->reg, &val);  in clk_aic32x4_div_recalc_rate()
374 	return regmap_update_bits(mux->regmap, AIC32X4_IFACE3,  in clk_aic32x4_bdiv_set_parent()
383 	regmap_read(mux->regmap, AIC32X4_IFACE3, &val);  in clk_aic32x4_bdiv_get_parent()
400 		.name = "pll",
410 			(const char *[]) { "mclk", "bclk", "gpio", "pll" },
460 	init.ops = desc->ops;  in aic32x4_register_clk()
461 	init.name = desc->name;  in aic32x4_register_clk()
462 	init.parent_names = desc->parent_names;  in aic32x4_register_clk()
463 	init.num_parents = desc->num_parents;  in aic32x4_register_clk()
468 		return (struct clk *) -ENOMEM;  in aic32x4_register_clk()
470 	priv->dev = dev;  in aic32x4_register_clk()
471 	priv->hw.init = &init;  in aic32x4_register_clk()
472 	priv->regmap = dev_get_regmap(dev, NULL);  in aic32x4_register_clk()
473 	priv->reg = desc->reg;  in aic32x4_register_clk()
475 	clk_hw_register_clkdev(&priv->hw, desc->name, devname);  in aic32x4_register_clk()
476 	return devm_clk_register(dev, &priv->hw);  in aic32x4_register_clk()
492 			(const char *[]) { mclk_name, "bclk", "gpio", "pll" };  in aic32x4_register_clocks()