Lines Matching +full:mic +full:- +full:offset
1 // SPDX-License-Identifier: GPL-2.0
5 * Copyright (C) 2014-2017 Texas Instruments Incorporated - https://www.ti.com/
50 #define AIC31XX_PLLPR AIC31XX_REG(0, 5) /* PLL P and R-VAL register */
51 #define AIC31XX_PLLJ AIC31XX_REG(0, 6) /* PLL J-VAL register */
52 #define AIC31XX_PLLDMSB AIC31XX_REG(0, 7) /* PLL D-VAL MSB register */
53 #define AIC31XX_PLLDLSB AIC31XX_REG(0, 8) /* PLL D-VAL LSB register */
65 #define AIC31XX_DATA_OFFSET AIC31XX_REG(0, 28) /* Audio Data Slot Offset Programming */
90 #define AIC31XX_ADCSETUP AIC31XX_REG(0, 81) /* ADC Digital Mic */
96 #define AIC31XX_SPKAMP AIC31XX_REG(1, 32) /* Class-D Speakear Amplifier */
98 #define AIC31XX_SPPGARAMP AIC31XX_REG(1, 34) /* Output Driver PGA Ramp-Down Period Control */
109 #define AIC31XX_MICBIAS AIC31XX_REG(1, 46) /* MIC Bias Control */
110 #define AIC31XX_MICPGA AIC31XX_REG(1, 47) /* MIC PGA*/
111 …ine AIC31XX_MICPGAPI AIC31XX_REG(1, 48) /* Delta-Sigma Mono ADC Channel Fine-Gain Input Selection …
112 #define AIC31XX_MICPGAMI AIC31XX_REG(1, 49) /* ADC Input Selection for M-Terminal */