Lines Matching +full:channel +full:- +full:select
1 /* SPDX-License-Identifier: GPL-2.0-or-later */
50 #define LINVOL_LIN_VOL 0x01F /* Left Channel PGA Volume control …
51 #define LINVOL_LIN_ENABLE_MUTE 0x080 /* Left Channel Input Mute …
52 #define LINVOL_LRIN_BOTH 0x100 /* Left Channel Line Input Volume update …
55 #define RINVOL_RIN_VOL 0x01F /* Right Channel PGA Volume control …
56 #define RINVOL_RIN_ENABLE_MUTE 0x080 /* Right Channel Input Mute …
57 #define RINVOL_RLIN_BOTH 0x100 /* Right Channel Line Input Volume update …
60 #define LOUT1V_LHP_VOL 0x07F /* Left Channel Headphone volume control …
61 #define LOUT1V_ENABLE_LZC 0x080 /* Left Channel Zero cross detect enable …
62 #define LOUT1V_LRHP_BOTH 0x100 /* Left Channel Headphone volume update …
65 #define ROUT1V_RHP_VOL 0x07F /* Right Channel Headphone volume control …
66 #define ROUT1V_ENABLE_RZC 0x080 /* Right Channel Zero cross detect enable …
67 #define ROUT1V_RLHP_BOTH 0x100 /* Right Channel Headphone volume update …
72 #define APANA_ADC_IN_SELECT 0x004 /* Microphone/Line IN select to ADC (1=MIC, 0=Line…
74 #define APANA_SELECT_DAC 0x010 /* Select DAC (1=Select DAC, 0=Don't Select DAC) …
81 #define APDIGI_DE_EMPHASIS 0x006 /* De-Emphasis Control …
107 #define SRATE_BOS_RATE 0x002 /* Base Over-Sampling rate …
109 #define SRATE_CORECLK_DIV2 0x040 /* Core Clock divider select …
110 #define SRATE_CLKOUT_DIV2 0x080 /* Clock Out divider select …