1 // SPDX-License-Identifier: GPL-2.0
5 // Copyright 2021-2022 Deqx Pty Ltd
17 	bool master[2];  member
25 static const DECLARE_TLV_DB_SCALE(src_tlv, -12750, 50, 0);
133 	{"SRC mclk source", "Master (MCLK)", "MCLK"},
134 	{"SRC mclk source", "Master (RXCLKI)", "RXMCLKI"},
156 	struct snd_soc_component *component = dai->component;  in src4xxx_set_dai_fmt()
163 		src4xxx->master[dai->id] = true;  in src4xxx_set_dai_fmt()
167 		src4xxx->master[dai->id] = false;  in src4xxx_set_dai_fmt()
170 		return -EINVAL;  in src4xxx_set_dai_fmt()
185 		return -EINVAL;  in src4xxx_set_dai_fmt()
193 		return -EINVAL;  in src4xxx_set_dai_fmt()
197 	regmap_update_bits(src4xxx->regmap, SRC4XXX_BUS_FMT(dai->id),  in src4xxx_set_dai_fmt()
206 	struct snd_soc_component *component = codec_dai->component;  in src4xxx_set_mclk_hz()
209 	dev_info(component->dev, "changing mclk rate from %d to %d Hz\n",  in src4xxx_set_mclk_hz()
210 		src4xxx->mclk_hz, freq);  in src4xxx_set_mclk_hz()
211 	src4xxx->mclk_hz = freq;  in src4xxx_set_mclk_hz()
220 	struct snd_soc_component *component = dai->component;  in src4xxx_hw_params()
227 	switch (dai->id) {  in src4xxx_hw_params()
236 	if (src4xxx->master[dai->id]) {  in src4xxx_hw_params()
237 		mclk_div = src4xxx->mclk_hz/params_rate(params);  in src4xxx_hw_params()
238 		if (src4xxx->mclk_hz != mclk_div*params_rate(params)) {  in src4xxx_hw_params()
239 			dev_err(component->dev,  in src4xxx_hw_params()
241 				src4xxx->mclk_hz, params_rate(params));  in src4xxx_hw_params()
242 			return -EINVAL;  in src4xxx_hw_params()
245 		val = ((int)mclk_div - 128) / 128;  in src4xxx_hw_params()
247 			dev_err(component->dev,  in src4xxx_hw_params()
250 			dev_err(component->dev,  in src4xxx_hw_params()
251 				"unsupported sample rate %d Hz for the master clock of %d Hz\n",  in src4xxx_hw_params()
252 				params_rate(params), src4xxx->mclk_hz);  in src4xxx_hw_params()
253 			return -EINVAL;  in src4xxx_hw_params()
257 		ret = regmap_update_bits(src4xxx->regmap,  in src4xxx_hw_params()
261 			dev_err(component->dev,  in src4xxx_hw_params()
268 		/* set the PLL for the digital receiver */  in src4xxx_hw_params()
269 		switch (src4xxx->mclk_hz) {  in src4xxx_hw_params()
284 			 * -Wsometimes-uninitialized from clang.  in src4xxx_hw_params()
286 			dev_info(component->dev,  in src4xxx_hw_params()
287 …"Couldn't set the RCV PLL as this master clock rate is unknown. Chosen regmap values may not match…  in src4xxx_hw_params()
293 		ret = regmap_write(src4xxx->regmap, SRC4XXX_RCV_PLL_0F, pj);  in src4xxx_hw_params()
295 			dev_err(component->dev,  in src4xxx_hw_params()
296 				"Failed to update PLL register 0x%x\n",  in src4xxx_hw_params()
298 		ret = regmap_write(src4xxx->regmap, SRC4XXX_RCV_PLL_10, jd);  in src4xxx_hw_params()
300 			dev_err(component->dev,  in src4xxx_hw_params()
301 				"Failed to update PLL register 0x%x\n",  in src4xxx_hw_params()
303 		ret = regmap_write(src4xxx->regmap, SRC4XXX_RCV_PLL_11, d);  in src4xxx_hw_params()
305 			dev_err(component->dev,  in src4xxx_hw_params()
306 				"Failed to update PLL register 0x%x\n",  in src4xxx_hw_params()
309 		ret = regmap_update_bits(src4xxx->regmap,  in src4xxx_hw_params()
313 			dev_err(component->dev,  in src4xxx_hw_params()
320 		return regmap_update_bits(src4xxx->regmap, reg,  in src4xxx_hw_params()
323 		dev_info(dai->dev, "not setting up MCLK as not master\n");  in src4xxx_hw_params()
345 		.name = "src4xxx-portA",
364 		.name = "src4xxx-portB",
426 		return -ENOMEM;  in src4xxx_probe()
428 	src4xxx->regmap = regmap;  in src4xxx_probe()
429 	src4xxx->dev = dev;  in src4xxx_probe()
430 	src4xxx->mclk_hz = 0; /* mclk has not been configured yet */  in src4xxx_probe()
442 	ret = regmap_update_bits(src4xxx->regmap, SRC4XXX_PWR_RST_01,  in src4xxx_probe()
447 	/* set receiver to use master clock (rcv mclk is most likely jittery) */  in src4xxx_probe()
448 	ret = regmap_update_bits(src4xxx->regmap, SRC4XXX_RCV_CTL_0D,  in src4xxx_probe()
455 	ret = regmap_update_bits(src4xxx->regmap, SRC4XXX_RCV_CTL_0E,  in src4xxx_probe()