18 #define RT9120_REG_DEVID	0x00
19 #define RT9120_REG_I2SFMT	0x02
20 #define RT9120_REG_I2SWL	0x03
21 #define RT9120_REG_SDIOSEL	0x04
22 #define RT9120_REG_SYSCTL	0x05
23 #define RT9120_REG_SPKGAIN	0x07
24 #define RT9120_REG_VOLRAMP	0x0A
25 #define RT9120_REG_ERRRPT	0x10
26 #define RT9120_REG_MSVOL	0x20
27 #define RT9120_REG_SWRESET	0x40
28 #define RT9120_REG_INTERCFG	0x63
29 #define RT9120_REG_INTERNAL0	0x65
30 #define RT9120_REG_INTERNAL1	0x69
31 #define RT9120_REG_UVPOPT	0x6C
32 #define RT9120_REG_DIGCFG	0xF8
39 #define RT9120_CFG_FMT_I2S	0
44 #define RT9120_AUDBIT_MASK	GENMASK(1, 0)
45 #define RT9120_CFG_AUDBIT_16	0
48 #define RT9120_AUDWL_MASK	GENMASK(5, 0)
55 #define RT9120_VENDOR_ID	0x42
56 #define RT9120S_VENDOR_ID	0x43
71 	CHIP_IDX_RT9120 = 0,
88 	0, 3, TLV_DB_SCALE_ITEM(600, 200, 0),
89 	4, 7, TLV_DB_SCALE_ITEM(1300, 100, 0)
101 	SOC_SINGLE_TLV("MS Volume", RT9120_REG_MSVOL, 0, 2047, 1, digital_tlv),
102 	SOC_SINGLE_TLV("SPK Gain Volume", RT9120_REG_SPKGAIN, 0, 7, 0, classd_tlv),
103 	SOC_SINGLE("PBTL Switch", RT9120_REG_SYSCTL, 3, 1, 0),
114 		snd_soc_component_write(comp, RT9120_REG_ERRRPT, 0);  in internal_power_event()
126 	return 0;  in internal_power_event()
130 	SND_SOC_DAPM_MIXER("DMIX", SND_SOC_NOPM, 0, 0, NULL, 0),
131 	SND_SOC_DAPM_DAC("LDAC", NULL, SND_SOC_NOPM, 0, 0),
132 	SND_SOC_DAPM_DAC("RDAC", NULL, SND_SOC_NOPM, 0, 0),
136 	SND_SOC_DAPM_PGA("SPKL PA", SND_SOC_NOPM, 0, 0, NULL, 0),
137 	SND_SOC_DAPM_PGA("SPKR PA", SND_SOC_NOPM, 0, 0, NULL, 0),
169 		snd_soc_component_write(comp, RT9120_REG_INTERCFG, 0xde);  in rt9120_codec_probe()
170 		snd_soc_component_write(comp, RT9120_REG_INTERNAL0, 0x66);  in rt9120_codec_probe()
172 		snd_soc_component_write(comp, RT9120_REG_INTERNAL0, 0x04);  in rt9120_codec_probe()
177 	return 0;  in rt9120_codec_probe()
232 	return 0;  in rt9120_set_fmt()
282 	if (fs % 48 == 0)  in rt9120_hw_params()
283 		auto_sync = 0;  in rt9120_hw_params()
289 	return 0;  in rt9120_hw_params()
323 	regmap_reg_range(0x00, 0x0C),
324 	regmap_reg_range(0x10, 0x15),
325 	regmap_reg_range(0x20, 0x27),
326 	regmap_reg_range(0x30, 0x38),
327 	regmap_reg_range(0x3A, 0x40),
328 	regmap_reg_range(0x63, 0x63),
329 	regmap_reg_range(0x65, 0x65),
330 	regmap_reg_range(0x69, 0x69),
331 	regmap_reg_range(0x6C, 0x6C),
332 	regmap_reg_range(0xF8, 0xF8)
341 	regmap_reg_range(0x00, 0x00),
342 	regmap_reg_range(0x02, 0x0A),
343 	regmap_reg_range(0x10, 0x15),
344 	regmap_reg_range(0x20, 0x27),
345 	regmap_reg_range(0x30, 0x38),
346 	regmap_reg_range(0x3A, 0x3D),
347 	regmap_reg_range(0x40, 0x40),
348 	regmap_reg_range(0x63, 0x63),
349 	regmap_reg_range(0x65, 0x65),
350 	regmap_reg_range(0x69, 0x69),
351 	regmap_reg_range(0x6C, 0x6C),
352 	regmap_reg_range(0xF8, 0xF8)
363 	case 0x00 ... 0x01:  in rt9120_volatile_reg()
364 	case 0x10:  in rt9120_volatile_reg()
365 	case 0x30 ... 0x40:  in rt9120_volatile_reg()
375 	case 0x00:  in rt9120_get_reg_size()
376 	case 0x20 ... 0x27:  in rt9120_get_reg_size()
378 	case 0x30 ... 0x3D:  in rt9120_get_reg_size()
380 	case 0x3E ... 0x3F:  in rt9120_get_reg_size()
392 	u8 raw[4] = {0};  in rt9120_reg_read()
396 	if (ret < 0)  in rt9120_reg_read()
406 		*val = raw[0] << 16 | raw[1] << 8 | raw[2];  in rt9120_reg_read()
412 		*val = raw[0];  in rt9120_reg_read()
415 	return 0;  in rt9120_reg_read()
432 	{ .reg = 0x02, .def = 0x02 },
433 	{ .reg = 0x03, .def = 0xf2 },
434 	{ .reg = 0x04, .def = 0x01 },
435 	{ .reg = 0x05, .def = 0xc0 },
436 	{ .reg = 0x06, .def = 0x28 },
437 	{ .reg = 0x07, .def = 0x04 },
438 	{ .reg = 0x08, .def = 0xff },
439 	{ .reg = 0x09, .def = 0x01 },
440 	{ .reg = 0x0a, .def = 0x01 },
441 	{ .reg = 0x0b, .def = 0x00 },
442 	{ .reg = 0x0c, .def = 0x04 },
443 	{ .reg = 0x11, .def = 0x30 },
444 	{ .reg = 0x12, .def = 0x08 },
445 	{ .reg = 0x13, .def = 0x12 },
446 	{ .reg = 0x14, .def = 0x09 },
447 	{ .reg = 0x15, .def = 0x00 },
448 	{ .reg = 0x20, .def = 0x7ff },
449 	{ .reg = 0x21, .def = 0x180 },
450 	{ .reg = 0x22, .def = 0x180 },
451 	{ .reg = 0x23, .def = 0x00 },
452 	{ .reg = 0x24, .def = 0x80 },
453 	{ .reg = 0x25, .def = 0x180 },
454 	{ .reg = 0x26, .def = 0x640 },
455 	{ .reg = 0x27, .def = 0x180 },
456 	{ .reg = 0x63, .def = 0x5e },
457 	{ .reg = 0x65, .def = 0x66 },
458 	{ .reg = 0x6c, .def = 0xe0 },
459 	{ .reg = 0xf8, .def = 0x44 },
496 		dev_err(data->dev, "DEVID not correct [0x%0x]\n", devid);  in rt9120_check_vendor_info()
500 	return 0;  in rt9120_check_vendor_info()
513 	return 0;  in rt9120_do_register_reset()
569 					 RT9120_DVDD_UVSEL_MASK, 0);  in rt9120_probe()
600 		gpiod_set_value(data->pwdnn_gpio, 0);  in rt9120_runtime_suspend()
603 	return 0;  in rt9120_runtime_suspend()
617 	return 0;  in rt9120_runtime_resume()