Lines Matching +full:0 +full:x44030000
53 #define RT722_VENDOR_REG 0x20
54 #define RT722_VENDOR_CALI 0x58
55 #define RT722_VENDOR_SPK_EFUSE 0x5c
56 #define RT722_VENDOR_IMS_DRE 0x5b
57 #define RT722_VENDOR_ANALOG_CTL 0x5f
58 #define RT722_VENDOR_HDA_CTL 0x61
61 #define RT722_JD_PRODUCT_NUM 0x00
62 #define RT722_ANALOG_BIAS_CTL3 0x04
63 #define RT722_JD_CTRL1 0x09
64 #define RT722_LDO2_3_CTL1 0x0e
65 #define RT722_LDO1_CTL 0x1a
66 #define RT722_HP_JD_CTRL 0x24
67 #define RT722_CLSD_CTRL6 0x3c
68 #define RT722_COMBO_JACK_AUTO_CTL1 0x45
69 #define RT722_COMBO_JACK_AUTO_CTL2 0x46
70 #define RT722_COMBO_JACK_AUTO_CTL3 0x47
71 #define RT722_DIGITAL_MISC_CTRL4 0x4a
72 #define RT722_VREFO_GAT 0x63
73 #define RT722_FSM_CTL 0x67
74 #define RT722_SDCA_INTR_REC 0x82
75 #define RT722_SW_CONFIG1 0x8a
76 #define RT722_SW_CONFIG2 0x8b
79 #define RT722_DAC_DC_CALI_CTL0 0x00
80 #define RT722_DAC_DC_CALI_CTL1 0x01
81 #define RT722_DAC_DC_CALI_CTL2 0x02
82 #define RT722_DAC_DC_CALI_CTL3 0x03
85 #define RT722_ULTRA_SOUND_DETECTOR6 0x1e
88 #define RT722_IMS_DIGITAL_CTL1 0x00
89 #define RT722_IMS_DIGITAL_CTL5 0x05
90 #define RT722_HP_DETECT_RLDET_CTL1 0x29
91 #define RT722_HP_DETECT_RLDET_CTL2 0x2a
94 #define RT722_MISC_POWER_CTL0 0x00
95 #define RT722_MISC_POWER_CTL7 0x08
98 #define RT722_HDA_LEGACY_MUX_CTL0 0x00
99 #define RT722_HDA_LEGACY_UNSOL_CTL 0x03
100 #define RT722_HDA_LEGACY_CONFIG_CTL0 0x06
101 #define RT722_HDA_LEGACY_RESET_CTL 0x08
102 #define RT722_HDA_LEGACY_GPIO_WAKE_EN_CTL 0x0e
103 #define RT722_DMIC_ENT_FLOAT_CTL 0x10
104 #define RT722_DMIC_GAIN_ENT_FLOAT_CTL0 0x11
105 #define RT722_DMIC_GAIN_ENT_FLOAT_CTL2 0x13
106 #define RT722_ADC_ENT_FLOAT_CTL 0x15
107 #define RT722_ADC_VOL_CH_FLOAT_CTL 0x17
108 #define RT722_ADC_SAMPLE_RATE_FLOAT 0x18
109 #define RT722_DAC03_HP_PDE_FLOAT_CTL 0x22
110 #define RT722_MIC2_LINE2_PDE_FLOAT_CTL 0x23
111 #define RT722_ET41_LINE2_PDE_FLOAT_CTL 0x24
112 #define RT722_ADC0A_08_PDE_FLOAT_CTL 0x25
113 #define RT722_ADC10_PDE_FLOAT_CTL 0x26
114 #define RT722_DMIC1_2_PDE_FLOAT_CTL 0x28
115 #define RT722_AMP_PDE_FLOAT_CTL 0x29
116 #define RT722_I2S_IN_OUT_PDE_FLOAT_CTL 0x2f
117 #define RT722_GE_RELATED_CTL1 0x45
118 #define RT722_GE_RELATED_CTL2 0x46
119 #define RT722_MIXER_CTL0 0x52
120 #define RT722_MIXER_CTL1 0x53
121 #define RT722_EAPD_CTL 0x55
122 #define RT722_UMP_HID_CTL0 0x60
123 #define RT722_UMP_HID_CTL1 0x61
124 #define RT722_UMP_HID_CTL2 0x62
125 #define RT722_UMP_HID_CTL3 0x63
126 #define RT722_UMP_HID_CTL4 0x64
127 #define RT722_UMP_HID_CTL5 0x65
128 #define RT722_UMP_HID_CTL6 0x66
129 #define RT722_UMP_HID_CTL7 0x67
130 #define RT722_UMP_HID_CTL8 0x68
131 #define RT722_FLOAT_CTRL_1 0x70
132 #define RT722_ENT_FLOAT_CTRL_1 0x76
134 /* Parameter & Verb control 01 (0x1a)(NID:20h) */
135 #define RT722_HIDDEN_REG_SW_RESET (0x1 << 14)
137 /* combo jack auto switch control 2 (0x46)(NID:20h) */
138 #define RT722_COMBOJACK_AUTO_DET_STATUS (0x1 << 11)
139 #define RT722_COMBOJACK_AUTO_DET_TRS (0x1 << 10)
140 #define RT722_COMBOJACK_AUTO_DET_CTIA (0x1 << 9)
141 #define RT722_COMBOJACK_AUTO_DET_OMTP (0x1 << 8)
143 /* DAC calibration control (0x00)(NID:58h) */
144 #define RT722_DC_CALIB_CTRL (0x1 << 16)
145 /* DAC DC offset calibration control-1 (0x01)(NID:58h) */
146 #define RT722_PDM_DC_CALIB_STATUS (0x1 << 15)
148 #define RT722_EAPD_HIGH 0x2
149 #define RT722_EAPD_LOW 0x0
152 #define RT722_BUF_ADDR_HID1 0x44030000
153 #define RT722_BUF_ADDR_HID2 0x44030020
156 #define FUNC_NUM_JACK_CODEC 0x01
157 #define FUNC_NUM_MIC_ARRAY 0x02
158 #define FUNC_NUM_HID 0x03
159 #define FUNC_NUM_AMP 0x04
162 #define RT722_SDCA_ENT_HID01 0x01
163 #define RT722_SDCA_ENT_GE49 0x49
164 #define RT722_SDCA_ENT_USER_FU05 0x05
165 #define RT722_SDCA_ENT_USER_FU06 0x06
166 #define RT722_SDCA_ENT_USER_FU0F 0x0f
167 #define RT722_SDCA_ENT_USER_FU10 0x19
168 #define RT722_SDCA_ENT_USER_FU1E 0x1e
169 #define RT722_SDCA_ENT_FU15 0x15
170 #define RT722_SDCA_ENT_PDE23 0x23
171 #define RT722_SDCA_ENT_PDE40 0x40
172 #define RT722_SDCA_ENT_PDE11 0x11
173 #define RT722_SDCA_ENT_PDE12 0x12
174 #define RT722_SDCA_ENT_PDE2A 0x2a
175 #define RT722_SDCA_ENT_CS01 0x01
176 #define RT722_SDCA_ENT_CS11 0x11
177 #define RT722_SDCA_ENT_CS1F 0x1f
178 #define RT722_SDCA_ENT_CS1C 0x1c
179 #define RT722_SDCA_ENT_CS31 0x31
180 #define RT722_SDCA_ENT_OT23 0x42
181 #define RT722_SDCA_ENT_IT26 0x26
182 #define RT722_SDCA_ENT_IT09 0x09
183 #define RT722_SDCA_ENT_PLATFORM_FU15 0x15
184 #define RT722_SDCA_ENT_PLATFORM_FU44 0x44
185 #define RT722_SDCA_ENT_XU03 0x03
186 #define RT722_SDCA_ENT_XU0D 0x0d
189 #define RT722_SDCA_CTL_SAMPLE_FREQ_INDEX 0x10
190 #define RT722_SDCA_CTL_FU_MUTE 0x01
191 #define RT722_SDCA_CTL_FU_VOLUME 0x02
192 #define RT722_SDCA_CTL_HIDTX_CURRENT_OWNER 0x10
193 #define RT722_SDCA_CTL_HIDTX_SET_OWNER_TO_DEVICE 0x11
194 #define RT722_SDCA_CTL_HIDTX_MESSAGE_OFFSET 0x12
195 #define RT722_SDCA_CTL_HIDTX_MESSAGE_LENGTH 0x13
196 #define RT722_SDCA_CTL_SELECTED_MODE 0x01
197 #define RT722_SDCA_CTL_DETECTED_MODE 0x02
198 #define RT722_SDCA_CTL_REQ_POWER_STATE 0x01
199 #define RT722_SDCA_CTL_VENDOR_DEF 0x30
200 #define RT722_SDCA_CTL_FU_CH_GAIN 0x0b
203 #define CH_L 0x01
204 #define CH_R 0x02
205 #define CH_01 0x01
206 #define CH_02 0x02
207 #define CH_03 0x03
208 #define CH_04 0x04
209 #define CH_08 0x08
212 #define RT722_SDCA_RATE_16000HZ 0x04
213 #define RT722_SDCA_RATE_32000HZ 0x07
214 #define RT722_SDCA_RATE_44100HZ 0x08
215 #define RT722_SDCA_RATE_48000HZ 0x09
216 #define RT722_SDCA_RATE_96000HZ 0x0b
217 #define RT722_SDCA_RATE_192000HZ 0x0d