Lines Matching +full:dmic +full:- +full:ref
1 // SPDX-License-Identifier: GPL-2.0-only
3 // rt5682s.c -- RT5682I-VS ALSA SoC audio component driver
25 #include <sound/soc-dapm.h>
38 .dai_clk_names[RT5682S_DAI_WCLK_IDX] = "rt5682-dai-wclk",
39 .dai_clk_names[RT5682S_DAI_BCLK_IDX] = "rt5682-dai-bclk",
46 [RT5682S_SUPPLY_LDO1_IN] = "LDO1-IN",
69 ret = regmap_multi_reg_write(rt5682s->regmap, patch_list, ARRAY_SIZE(patch_list));
624 regmap_write(rt5682s->regmap, RT5682S_RESET, 0);
634 dev_dbg(component->dev, "%s btn_type=%x\n", __func__, btn_type);
651 mutex_lock(&rt5682s->sar_mutex);
695 dev_err(component->dev, "Invalid SAR Power mode: %d\n", mode);
699 mutex_unlock(&rt5682s->sar_mutex);
733 * rt5682s_headset_detect - Detect headset.
782 dev_dbg(component->dev, "%s, val=%d, count=%d\n", __func__, val, count);
810 if (!rt5682s->wclk_enabled) {
824 dev_dbg(component->dev, "jack_type = %d\n", jack_type);
836 if (!rt5682s->component ||
837 !snd_soc_card_is_instantiated(rt5682s->component->card)) {
840 &rt5682s->jack_detect_work, msecs_to_jiffies(15));
844 dapm = snd_soc_component_to_dapm(rt5682s->component);
847 mutex_lock(&rt5682s->calibrate_mutex);
848 mutex_lock(&rt5682s->wclk_mutex);
850 val = snd_soc_component_read(rt5682s->component, RT5682S_AJD1_CTRL)
854 if (rt5682s->jack_type == 0) {
856 rt5682s->jack_type = rt5682s_headset_detect(rt5682s->component, 1);
857 rt5682s->irq_work_delay_time = 0;
858 } else if ((rt5682s->jack_type & SND_JACK_HEADSET) == SND_JACK_HEADSET) {
860 rt5682s->jack_type = SND_JACK_HEADSET;
861 btn_type = rt5682s_button_detect(rt5682s->component);
873 rt5682s->jack_type |= SND_JACK_BTN_0;
878 rt5682s->jack_type |= SND_JACK_BTN_1;
883 rt5682s->jack_type |= SND_JACK_BTN_2;
888 rt5682s->jack_type |= SND_JACK_BTN_3;
893 dev_err(rt5682s->component->dev,
900 rt5682s->jack_type = rt5682s_headset_detect(rt5682s->component, 0);
901 rt5682s->irq_work_delay_time = 50;
904 mutex_unlock(&rt5682s->wclk_mutex);
905 mutex_unlock(&rt5682s->calibrate_mutex);
908 snd_soc_jack_report(rt5682s->hs_jack, rt5682s->jack_type,
912 if (rt5682s->jack_type & (SND_JACK_BTN_0 | SND_JACK_BTN_1 |
914 schedule_delayed_work(&rt5682s->jd_check_work, 0);
916 cancel_delayed_work_sync(&rt5682s->jd_check_work);
924 if (snd_soc_component_read(rt5682s->component, RT5682S_AJD1_CTRL) & RT5682S_JDH_RS_MASK) {
926 schedule_delayed_work(&rt5682s->jack_detect_work, 0);
928 schedule_delayed_work(&rt5682s->jd_check_work, 500);
936 mod_delayed_work(system_power_efficient_wq, &rt5682s->jack_detect_work,
937 msecs_to_jiffies(rt5682s->irq_work_delay_time));
948 rt5682s->hs_jack = hs_jack;
951 regmap_update_bits(rt5682s->regmap, RT5682S_IRQ_CTRL_2,
953 regmap_update_bits(rt5682s->regmap, RT5682S_RC_CLK_CTRL,
955 cancel_delayed_work_sync(&rt5682s->jack_detect_work);
960 switch (rt5682s->pdata.jd_src) {
962 regmap_update_bits(rt5682s->regmap, RT5682S_CBJ_CTRL_5,
964 regmap_update_bits(rt5682s->regmap, RT5682S_CBJ_CTRL_2,
966 regmap_update_bits(rt5682s->regmap, RT5682S_CBJ_CTRL_1,
971 regmap_update_bits(rt5682s->regmap, RT5682S_SAR_IL_CMD_1,
973 regmap_update_bits(rt5682s->regmap, RT5682S_GPIO_CTRL_1,
975 regmap_update_bits(rt5682s->regmap, RT5682S_PWR_ANLG_3,
977 regmap_update_bits(rt5682s->regmap, RT5682S_PWR_ANLG_2,
979 regmap_update_bits(rt5682s->regmap, RT5682S_RC_CLK_CTRL,
981 regmap_update_bits(rt5682s->regmap, RT5682S_IRQ_CTRL_2,
984 regmap_update_bits(rt5682s->regmap, RT5682S_4BTN_IL_CMD_4,
987 regmap_update_bits(rt5682s->regmap, RT5682S_4BTN_IL_CMD_5,
990 regmap_update_bits(rt5682s->regmap, RT5682S_4BTN_IL_CMD_6,
993 regmap_update_bits(rt5682s->regmap, RT5682S_4BTN_IL_CMD_7,
998 &rt5682s->jack_detect_work, msecs_to_jiffies(250));
1002 regmap_update_bits(rt5682s->regmap, RT5682S_IRQ_CTRL_2,
1004 regmap_update_bits(rt5682s->regmap, RT5682S_RC_CLK_CTRL,
1009 dev_warn(component->dev, "Wrong JD source\n");
1016 static const DECLARE_TLV_DB_SCALE(dac_vol_tlv, -9562, 75, 0);
1017 static const DECLARE_TLV_DB_SCALE(adc_vol_tlv, -1725, 75, 0);
1019 static const DECLARE_TLV_DB_SCALE(cbj_bst_tlv, -1200, 150, 0);
1042 * rt5682s_sel_asrc_clk_src - select ASRC clock source for a set of filters
1065 return -EINVAL;
1090 if (rt5682s->sysclk < target) {
1091 dev_err(rt5682s->component->dev,
1092 "sysclk rate %d is too low\n", rt5682s->sysclk);
1096 for (i = 0; i < size - 1; i++) {
1097 dev_dbg(rt5682s->component->dev, "div[%d]=%d\n", i, div[i]);
1098 if (target * div[i] == rt5682s->sysclk)
1100 if (target * div[i + 1] > rt5682s->sysclk) {
1101 dev_dbg(rt5682s->component->dev,
1102 "can't find div for sysclk %d\n", rt5682s->sysclk);
1107 if (target * div[i] < rt5682s->sysclk)
1108 dev_err(rt5682s->component->dev,
1109 "sysclk rate %d is too high\n", rt5682s->sysclk);
1111 return size - 1;
1120 return -EINVAL;
1127 return -EINVAL;
1131 * set_dmic_clk - Set parameter of dmic.
1137 * Choose dmic clock between 1MHz and 3MHz.
1143 struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm);
1148 if (rt5682s->pdata.dmic_clk_rate)
1149 dmic_clk_rate = rt5682s->pdata.dmic_clk_rate;
1162 struct snd_soc_component *component = rt5682s->component;
1182 struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm);
1186 if (rt5682s->wclk_enabled)
1197 static void rt5682s_set_filter_clk(struct rt5682s_priv *rt5682s, int reg, int ref)
1199 struct snd_soc_component *component = rt5682s->component;
1204 idx = rt5682s_div_sel(rt5682s, ref, div_f, ARRAY_SIZE(div_f));
1211 if (rt5682s->sysclk <= 12288000 * div_o[idx])
1223 struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm);
1225 int ref, reg, val;
1230 if (w->shift == RT5682S_PWR_ADC_S1F_BIT && val == RT5682S_GP4_PIN_ADCDAT2)
1231 ref = 256 * rt5682s->lrck[RT5682S_AIF2];
1233 ref = 256 * rt5682s->lrck[RT5682S_AIF1];
1235 if (w->shift == RT5682S_PWR_ADC_S1F_BIT)
1240 rt5682s_set_filter_clk(rt5682s, reg, ref);
1248 struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm);
1252 if (rt5682s->pdata.dmic_delay)
1253 delay = rt5682s->pdata.dmic_delay;
1269 if (!rt5682s->jack_type && !rt5682s->wclk_enabled) {
1281 struct snd_soc_component *component = rt5682s->component;
1302 if (on && rt5682s->master[id]) {
1303 pre_div = get_clk_info(rt5682s->sysclk, rt5682s->lrck[id]);
1305 dev_err(component->dev, "get pre_div failed\n");
1309 dev_dbg(component->dev, "lrck is %dHz and pre_div is %d for iis %d master\n",
1310 rt5682s->lrck[id], pre_div, id);
1320 struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm);
1327 if (!snd_soc_dapm_widget_name_cmp(w, "I2S1") && !rt5682s->wclk_enabled)
1338 struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm);
1341 if ((rt5682s->sysclk_src == RT5682S_CLK_SRC_PLL1) ||
1342 (rt5682s->sysclk_src == RT5682S_CLK_SRC_PLL2 && rt5682s->pll_comb == USE_PLLAB))
1351 struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm);
1354 if (rt5682s->sysclk_src == RT5682S_CLK_SRC_PLL2)
1364 struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm);
1366 switch (w->shift) {
1392 struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm);
1437 struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm);
1441 if (rt5682s->pdata.amic_delay)
1442 delay = rt5682s->pdata.amic_delay;
1462 struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm);
1465 if ((rt5682s->jack_type & SND_JACK_HEADSET) != SND_JACK_HEADSET)
1570 /* MX-26 [13] [5] */
1588 /* MX-26 [11:10] [3:2] */
1606 /* MX-26 [12] [4] */
1608 "DAC MIX", "DMIC"
1623 /* MX-79 [6:4] I2S1 ADC data location */
1640 /* MX-2B [4], MX-2B [0]*/
1701 SND_SOC_DAPM_SUPPLY_S("DMIC ASRC", 1, RT5682S_PLL_TRACK_1,
1711 SND_SOC_DAPM_INPUT("DMIC L1"),
1712 SND_SOC_DAPM_INPUT("DMIC R1"),
1716 SND_SOC_DAPM_SUPPLY("DMIC CLK", SND_SOC_NOPM, 0, 0,
1883 {"DMIC L1", NULL, "DMIC CLK"},
1884 {"DMIC L1", NULL, "DMIC1 Power"},
1885 {"DMIC R1", NULL, "DMIC CLK"},
1886 {"DMIC R1", NULL, "DMIC1 Power"},
1887 {"DMIC CLK", NULL, "DMIC ASRC"},
1896 {"Stereo1 ADC L2 Mux", "DMIC", "DMIC L1"},
1901 {"Stereo1 ADC R2 Mux", "DMIC", "DMIC R1"},
1984 struct snd_soc_component *component = dai->component;
1998 dev_err(component->dev, "Invalid or oversized Tx slots.\n");
1999 return -EINVAL;
2001 val |= (tx_slotnum - 1) << RT5682S_TDM_ADC_DL_SFT;
2020 return -EINVAL;
2030 return -EINVAL;
2050 return -EINVAL;
2064 struct snd_soc_component *component = dai->component;
2069 rt5682s->lrck[dai->id] = params_rate(params);
2073 dev_err(component->dev, "Unsupported frame size: %d\n", frame_size);
2074 return -EINVAL;
2097 return -EINVAL;
2100 switch (dai->id) {
2122 dev_err(component->dev, "Invalid dai->id: %d\n", dai->id);
2123 return -EINVAL;
2131 struct snd_soc_component *component = dai->component;
2137 rt5682s->master[dai->id] = 1;
2140 rt5682s->master[dai->id] = 0;
2143 return -EINVAL;
2154 if (dai->id == RT5682S_AIF1)
2157 return -EINVAL;
2160 if (dai->id == RT5682S_AIF1)
2164 return -EINVAL;
2167 return -EINVAL;
2186 return -EINVAL;
2189 switch (dai->id) {
2197 tdm_ctrl | rt5682s->master[dai->id]);
2200 if (rt5682s->master[dai->id] == 0)
2207 dev_err(component->dev, "Invalid dai->id: %d\n", dai->id);
2208 return -EINVAL;
2219 if (freq == rt5682s->sysclk && clk_id == rt5682s->sysclk_src)
2236 dev_err(component->dev, "Invalid clock id (%d)\n", clk_id);
2237 return -EINVAL;
2247 rt5682s->sysclk = freq;
2248 rt5682s->sysclk_src = clk_id;
2250 dev_dbg(component->dev, "Sysclk is %dHz and clock id is %d\n",
2314 for (i = ARRAY_SIZE(plla_table) - 1; i >= 0; i--) {
2316 for (j = ARRAY_SIZE(pllb_table) - 1; j >= 0; j--) {
2327 return -EINVAL;
2337 if (source == rt5682s->pll_src[pll_id] && freq_in == rt5682s->pll_in[pll_id] &&
2338 freq_out == rt5682s->pll_out[pll_id])
2342 dev_dbg(component->dev, "PLL disabled\n");
2343 rt5682s->pll_in[pll_id] = 0;
2344 rt5682s->pll_out[pll_id] = 0;
2360 dev_err(component->dev, "Unknown PLL Source %d\n", source);
2361 return -EINVAL;
2364 rt5682s->pll_comb = find_pll_inter_combination(freq_in, freq_out,
2367 if ((pll_id == RT5682S_PLL1 && rt5682s->pll_comb == USE_PLLA) ||
2368 (pll_id == RT5682S_PLL2 && (rt5682s->pll_comb == USE_PLLB ||
2369 rt5682s->pll_comb == USE_PLLAB))) {
2370 dev_dbg(component->dev,
2371 "Supported freq conversion for PLL%d:(%d->%d): %d\n",
2372 pll_id + 1, freq_in, freq_out, rt5682s->pll_comb);
2374 dev_err(component->dev,
2375 "Unsupported freq conversion for PLL%d:(%d->%d): %d\n",
2376 pll_id + 1, freq_in, freq_out, rt5682s->pll_comb);
2377 return -EINVAL;
2380 if (rt5682s->pll_comb == USE_PLLA || rt5682s->pll_comb == USE_PLLAB) {
2381 dev_dbg(component->dev,
2396 if (rt5682s->pll_comb == USE_PLLB || rt5682s->pll_comb == USE_PLLAB) {
2397 dev_dbg(component->dev,
2416 if (rt5682s->pll_comb == USE_PLLB)
2420 rt5682s->pll_in[pll_id] = freq_in;
2421 rt5682s->pll_out[pll_id] = freq_out;
2422 rt5682s->pll_src[pll_id] = source;
2430 struct snd_soc_component *component = dai->component;
2433 rt5682s->bclk[dai->id] = ratio;
2453 dev_err(dai->dev, "Invalid bclk1 ratio %d\n", ratio);
2454 return -EINVAL;
2462 struct snd_soc_component *component = dai->component;
2465 rt5682s->bclk[dai->id] = ratio;
2477 dev_err(dai->dev, "Invalid bclk2 ratio %d\n", ratio);
2478 return -EINVAL;
2492 regmap_update_bits(rt5682s->regmap, RT5682S_PWR_DIG_1,
2497 regmap_update_bits(rt5682s->regmap, RT5682S_PWR_DIG_1,
2501 regmap_update_bits(rt5682s->regmap, RT5682S_PWR_DIG_1, RT5682S_PWR_LDO, 0);
2502 if (!rt5682s->wclk_enabled)
2503 regmap_update_bits(rt5682s->regmap, RT5682S_PWR_DIG_1,
2520 if (!rt5682s->master[RT5682S_AIF1]) {
2521 dev_dbg(rt5682s->component->dev, "dai clk fmt not set correctly\n");
2531 struct snd_soc_component *component = rt5682s->component;
2532 int ref, reg;
2535 return -EINVAL;
2537 mutex_lock(&rt5682s->wclk_mutex);
2553 ref = 256 * rt5682s->lrck[RT5682S_AIF1];
2554 rt5682s_set_filter_clk(rt5682s, reg, ref);
2557 rt5682s->wclk_enabled = 1;
2559 mutex_unlock(&rt5682s->wclk_mutex);
2568 struct snd_soc_component *component = rt5682s->component;
2573 mutex_lock(&rt5682s->wclk_mutex);
2575 if (!rt5682s->jack_type)
2587 rt5682s->wclk_enabled = 0;
2589 mutex_unlock(&rt5682s->wclk_mutex);
2597 struct snd_soc_component *component = rt5682s->component;
2605 if (rt5682s->lrck[RT5682S_AIF1] != CLK_48 &&
2606 rt5682s->lrck[RT5682S_AIF1] != CLK_44) {
2607 dev_warn(component->dev, "%s: clk %s only support %d or %d Hz output\n",
2612 return rt5682s->lrck[RT5682S_AIF1];
2620 struct snd_soc_component *component = rt5682s->component;
2624 return -EINVAL;
2629 if (req->rate != CLK_48 && req->rate != CLK_44) {
2630 dev_warn(component->dev, "%s: clk %s only support %d or %d Hz output\n",
2632 req->rate = CLK_48;
2643 struct snd_soc_component *component = rt5682s->component;
2649 return -EINVAL;
2658 parent_clk = clk_get_parent(hw->clk);
2660 dev_warn(component->dev,
2665 dev_warn(component->dev, "clk %s only support %d Hz input\n",
2679 rt5682s->lrck[RT5682S_AIF1] = rate;
2689 struct snd_soc_component *component = rt5682s->component;
2731 if (!req->best_parent_rate || !rt5682s_clk_check(rt5682s))
2732 return -EINVAL;
2741 factor = rt5682s_bclk_get_factor(req->rate, req->best_parent_rate);
2743 req->rate = req->best_parent_rate * factor;
2753 struct snd_soc_component *component = rt5682s->component;
2758 return -EINVAL;
2763 if (dai->id == RT5682S_AIF1)
2766 dev_err(component->dev, "dai %d not found in component\n",
2768 return -ENODEV;
2788 struct device *dev = component->dev;
2790 struct rt5682s_platform_data *pdata = &rt5682s->pdata;
2799 dai_clk_hw = &rt5682s->dai_clks_hw[i];
2804 if (rt5682s->mclk) {
2814 parent = &rt5682s->dai_clks_hw[RT5682S_DAI_WCLK_IDX];
2820 return -EINVAL;
2823 init.name = pdata->dai_clk_names[i];
2826 dai_clk_hw->init = &init;
2834 if (dev->of_node) {
2855 rt5682s->mclk = devm_clk_get_optional(component->dev, "mclk");
2856 if (IS_ERR(rt5682s->mclk))
2857 return PTR_ERR(rt5682s->mclk);
2865 rt5682s->lrck[RT5682S_AIF1] = CLK_48;
2880 rt5682s->component = component;
2897 if (rt5682s->irq)
2898 disable_irq(rt5682s->irq);
2900 cancel_delayed_work_sync(&rt5682s->jack_detect_work);
2901 cancel_delayed_work_sync(&rt5682s->jd_check_work);
2903 if (rt5682s->hs_jack)
2904 rt5682s->jack_type = rt5682s_headset_detect(component, 0);
2906 regcache_cache_only(rt5682s->regmap, true);
2907 regcache_mark_dirty(rt5682s->regmap);
2916 regcache_cache_only(rt5682s->regmap, false);
2917 regcache_sync(rt5682s->regmap);
2919 if (rt5682s->hs_jack) {
2921 &rt5682s->jack_detect_work, msecs_to_jiffies(0));
2924 if (rt5682s->irq)
2925 enable_irq(rt5682s->irq);
2968 device_property_read_u32(dev, "realtek,dmic1-data-pin",
2969 &rt5682s->pdata.dmic1_data_pin);
2970 device_property_read_u32(dev, "realtek,dmic1-clk-pin",
2971 &rt5682s->pdata.dmic1_clk_pin);
2972 device_property_read_u32(dev, "realtek,jd-src",
2973 &rt5682s->pdata.jd_src);
2974 device_property_read_u32(dev, "realtek,dmic-clk-rate-hz",
2975 &rt5682s->pdata.dmic_clk_rate);
2976 device_property_read_u32(dev, "realtek,dmic-delay-ms",
2977 &rt5682s->pdata.dmic_delay);
2978 device_property_read_u32(dev, "realtek,amic-delay-ms",
2979 &rt5682s->pdata.amic_delay);
2980 device_property_read_u32(dev, "realtek,ldo-sel",
2981 &rt5682s->pdata.ldo_dacref);
2983 if (device_property_read_string_array(dev, "clock-output-names",
2984 rt5682s->pdata.dai_clk_names,
2987 rt5682s->pdata.dai_clk_names[RT5682S_DAI_WCLK_IDX],
2988 rt5682s->pdata.dai_clk_names[RT5682S_DAI_BCLK_IDX]);
2990 rt5682s->pdata.dmic_clk_driving_high = device_property_read_bool(dev,
2991 "realtek,dmic-clk-driving-high");
3000 mutex_lock(&rt5682s->calibrate_mutex);
3002 regmap_write(rt5682s->regmap, RT5682S_PWR_ANLG_1, 0xaa80);
3004 regmap_write(rt5682s->regmap, RT5682S_PWR_ANLG_1, 0xfa80);
3005 regmap_write(rt5682s->regmap, RT5682S_PWR_DIG_1, 0x01c0);
3006 regmap_write(rt5682s->regmap, RT5682S_MICBIAS_2, 0x0380);
3007 regmap_write(rt5682s->regmap, RT5682S_GLB_CLK, 0x8000);
3008 regmap_write(rt5682s->regmap, RT5682S_ADDA_CLK_1, 0x1001);
3009 regmap_write(rt5682s->regmap, RT5682S_CHOP_DAC_2, 0x3030);
3010 regmap_write(rt5682s->regmap, RT5682S_CHOP_ADC, 0xb000);
3011 regmap_write(rt5682s->regmap, RT5682S_STO1_ADC_MIXER, 0x686c);
3012 regmap_write(rt5682s->regmap, RT5682S_CAL_REC, 0x5151);
3013 regmap_write(rt5682s->regmap, RT5682S_HP_CALIB_CTRL_2, 0x0321);
3014 regmap_write(rt5682s->regmap, RT5682S_HP_LOGIC_CTRL_2, 0x0004);
3015 regmap_write(rt5682s->regmap, RT5682S_HP_CALIB_CTRL_1, 0x7c00);
3016 regmap_write(rt5682s->regmap, RT5682S_HP_CALIB_CTRL_1, 0xfc00);
3019 regmap_read(rt5682s->regmap, RT5682S_HP_CALIB_ST_1, &value);
3027 dev_err(rt5682s->component->dev, "HP Calibration Failure\n");
3030 regmap_write(rt5682s->regmap, RT5682S_MICBIAS_2, 0x0180);
3031 regmap_write(rt5682s->regmap, RT5682S_CAL_REC, 0x5858);
3032 regmap_write(rt5682s->regmap, RT5682S_STO1_ADC_MIXER, 0xc0c4);
3033 regmap_write(rt5682s->regmap, RT5682S_HP_CALIB_CTRL_2, 0x0320);
3034 regmap_write(rt5682s->regmap, RT5682S_PWR_DIG_1, 0x00c0);
3035 regmap_write(rt5682s->regmap, RT5682S_PWR_ANLG_1, 0x0800);
3036 regmap_write(rt5682s->regmap, RT5682S_GLB_CLK, 0x0000);
3038 mutex_unlock(&rt5682s->calibrate_mutex);
3056 .name = "rt5682s-aif1",
3075 .name = "rt5682s-aif2",
3091 struct device *dev = regmap_get_device(rt5682s->regmap);
3094 ret = regulator_disable(rt5682s->supplies[RT5682S_SUPPLY_AVDD].consumer);
3098 ret = regulator_disable(rt5682s->supplies[RT5682S_SUPPLY_DBVDD].consumer);
3102 ret = regulator_disable(rt5682s->supplies[RT5682S_SUPPLY_LDO1_IN].consumer);
3104 dev_err(dev, "Failed to disable supply LDO1-IN: %d\n", ret);
3108 ret = regulator_disable(rt5682s->supplies[RT5682S_SUPPLY_MICVDD].consumer);
3115 struct rt5682s_platform_data *pdata = dev_get_platdata(&i2c->dev);
3120 rt5682s = devm_kzalloc(&i2c->dev, sizeof(struct rt5682s_priv), GFP_KERNEL);
3122 return -ENOMEM;
3126 rt5682s->pdata = i2s_default_platform_data;
3129 rt5682s->pdata = *pdata;
3131 rt5682s_parse_dt(rt5682s, &i2c->dev);
3133 rt5682s->regmap = devm_regmap_init_i2c(i2c, &rt5682s_regmap);
3134 if (IS_ERR(rt5682s->regmap)) {
3135 ret = PTR_ERR(rt5682s->regmap);
3136 dev_err(&i2c->dev, "Failed to allocate register map: %d\n", ret);
3140 for (i = 0; i < ARRAY_SIZE(rt5682s->supplies); i++)
3141 rt5682s->supplies[i].supply = rt5682s_supply_names[i];
3143 ret = devm_regulator_bulk_get(&i2c->dev,
3144 ARRAY_SIZE(rt5682s->supplies), rt5682s->supplies);
3146 dev_err(&i2c->dev, "Failed to request supplies: %d\n", ret);
3150 ret = devm_add_action_or_reset(&i2c->dev, rt5682s_i2c_disable_regulators, rt5682s);
3154 ret = regulator_enable(rt5682s->supplies[RT5682S_SUPPLY_MICVDD].consumer);
3156 dev_err(&i2c->dev, "Failed to enable supply MICVDD: %d\n", ret);
3161 ret = regulator_enable(rt5682s->supplies[RT5682S_SUPPLY_AVDD].consumer);
3163 dev_err(&i2c->dev, "Failed to enable supply AVDD: %d\n", ret);
3167 ret = regulator_enable(rt5682s->supplies[RT5682S_SUPPLY_DBVDD].consumer);
3169 dev_err(&i2c->dev, "Failed to enable supply DBVDD: %d\n", ret);
3173 ret = regulator_enable(rt5682s->supplies[RT5682S_SUPPLY_LDO1_IN].consumer);
3175 dev_err(&i2c->dev, "Failed to enable supply LDO1-IN: %d\n", ret);
3179 rt5682s->ldo1_en = devm_gpiod_get_optional(&i2c->dev,
3180 "realtek,ldo1-en",
3182 if (IS_ERR(rt5682s->ldo1_en)) {
3183 dev_err(&i2c->dev, "Fail gpio request ldo1_en\n");
3184 return PTR_ERR(rt5682s->ldo1_en);
3190 regmap_read(rt5682s->regmap, RT5682S_DEVICE_ID, &val);
3192 dev_err(&i2c->dev, "Device with ID register %x is not rt5682s\n", val);
3193 return -ENODEV;
3197 rt5682s_apply_patch_list(rt5682s, &i2c->dev);
3199 regmap_update_bits(rt5682s->regmap, RT5682S_PWR_DIG_2,
3203 mutex_init(&rt5682s->calibrate_mutex);
3204 mutex_init(&rt5682s->sar_mutex);
3205 mutex_init(&rt5682s->wclk_mutex);
3208 regmap_update_bits(rt5682s->regmap, RT5682S_MICBIAS_2,
3211 regmap_update_bits(rt5682s->regmap, RT5682S_PWR_ANLG_1,
3213 regmap_update_bits(rt5682s->regmap, RT5682S_HP_LOGIC_CTRL_2,
3215 regmap_update_bits(rt5682s->regmap, RT5682S_HP_CHARGE_PUMP_2,
3217 regmap_update_bits(rt5682s->regmap, RT5682S_HP_AMP_DET_CTL_1,
3220 /* DMIC data pin */
3221 switch (rt5682s->pdata.dmic1_data_pin) {
3225 regmap_update_bits(rt5682s->regmap, RT5682S_DMIC_CTRL_1,
3227 regmap_update_bits(rt5682s->regmap, RT5682S_GPIO_CTRL_1,
3231 regmap_update_bits(rt5682s->regmap, RT5682S_DMIC_CTRL_1,
3233 regmap_update_bits(rt5682s->regmap, RT5682S_GPIO_CTRL_1,
3237 dev_warn(&i2c->dev, "invalid DMIC_DAT pin\n");
3241 /* DMIC clk pin */
3242 switch (rt5682s->pdata.dmic1_clk_pin) {
3246 regmap_update_bits(rt5682s->regmap, RT5682S_GPIO_CTRL_1,
3250 regmap_update_bits(rt5682s->regmap, RT5682S_GPIO_CTRL_1,
3252 if (rt5682s->pdata.dmic_clk_driving_high)
3253 regmap_update_bits(rt5682s->regmap, RT5682S_PAD_DRIVING_CTRL,
3257 dev_warn(&i2c->dev, "invalid DMIC_CLK pin\n");
3262 switch (rt5682s->pdata.ldo_dacref) {
3266 regmap_update_bits(rt5682s->regmap, RT5682S_BIAS_CUR_CTRL_7,
3270 regmap_update_bits(rt5682s->regmap, RT5682S_BIAS_CUR_CTRL_7,
3274 regmap_update_bits(rt5682s->regmap, RT5682S_BIAS_CUR_CTRL_7,
3278 dev_warn(&i2c->dev, "invalid LDO output setting.\n");
3282 INIT_DELAYED_WORK(&rt5682s->jack_detect_work, rt5682s_jack_detect_handler);
3283 INIT_DELAYED_WORK(&rt5682s->jd_check_work, rt5682s_jd_check_handler);
3285 if (i2c->irq) {
3286 ret = devm_request_threaded_irq(&i2c->dev, i2c->irq, NULL, rt5682s_irq,
3290 rt5682s->irq = i2c->irq;
3292 dev_err(&i2c->dev, "Failed to request IRQ: %d\n", ret);
3295 return devm_snd_soc_register_component(&i2c->dev, &rt5682s_soc_component_dev,
3303 disable_irq(client->irq);
3304 cancel_delayed_work_sync(&rt5682s->jack_detect_work);
3305 cancel_delayed_work_sync(&rt5682s->jd_check_work);
3347 MODULE_DESCRIPTION("ASoC RT5682I-VS driver");