Lines Matching +full:adc +full:- +full:sample +full:- +full:hold +full:- +full:time
1 // SPDX-License-Identifier: GPL-2.0-only
3 // rt5682.c -- RT5682 ALSA SoC audio component driver
25 #include <sound/soc-dapm.h>
38 "LDO1-IN",
60 ret = regmap_multi_reg_write(rt5682->regmap, patch_list, in rt5682_apply_patch_list()
749 static const DECLARE_TLV_DB_SCALE(dac_vol_tlv, -6525, 75, 0);
750 static const DECLARE_TLV_DB_SCALE(adc_vol_tlv, -1725, 75, 0);
785 SOC_DAPM_ENUM("IF2 ADC Swap Mux", rt5682_if2_adc_enum);
788 SOC_DAPM_ENUM("IF1 01 ADC Swap Mux", rt5682_if1_01_adc_enum);
791 SOC_DAPM_ENUM("IF1 23 ADC Swap Mux", rt5682_if1_23_adc_enum);
794 SOC_DAPM_ENUM("IF1 45 ADC Swap Mux", rt5682_if1_45_adc_enum);
797 SOC_DAPM_ENUM("IF1 67 ADC Swap Mux", rt5682_if1_67_adc_enum);
817 regmap_write(rt5682->regmap, RT5682_RESET, 0); in rt5682_reset()
818 if (!rt5682->is_sdw) in rt5682_reset()
819 regmap_write(rt5682->regmap, RT5682_I2C_MODE, 1); in rt5682_reset()
824 * rt5682_sel_asrc_clk_src - select ASRC clock source for a set of filters
847 return -EINVAL; in rt5682_sel_asrc_clk_src()
873 dev_dbg(component->dev, "%s btn_type=%x\n", __func__, btn_type); in rt5682_button_detect()
894 if (rt5682->is_sdw) in rt5682_enable_push_button_irq()
918 * rt5682_headset_detect - Detect headset.
929 struct snd_soc_dapm_context *dapm = &component->dapm; in rt5682_headset_detect()
966 rt5682->jack_type = SND_JACK_HEADSET; in rt5682_headset_detect()
972 rt5682->jack_type = SND_JACK_HEADPHONE; in rt5682_headset_detect()
1005 rt5682->jack_type = 0; in rt5682_headset_detect()
1008 dev_dbg(component->dev, "jack_type = %d\n", rt5682->jack_type); in rt5682_headset_detect()
1009 return rt5682->jack_type; in rt5682_headset_detect()
1017 rt5682->hs_jack = hs_jack; in rt5682_set_jack_detect()
1019 if (rt5682->is_sdw && !rt5682->first_hw_init) in rt5682_set_jack_detect()
1023 regmap_update_bits(rt5682->regmap, RT5682_IRQ_CTRL_2, in rt5682_set_jack_detect()
1025 regmap_update_bits(rt5682->regmap, RT5682_RC_CLK_CTRL, in rt5682_set_jack_detect()
1027 cancel_delayed_work_sync(&rt5682->jack_detect_work); in rt5682_set_jack_detect()
1032 if (!rt5682->is_sdw) { in rt5682_set_jack_detect()
1033 switch (rt5682->pdata.jd_src) { in rt5682_set_jack_detect()
1048 regmap_update_bits(rt5682->regmap, RT5682_GPIO_CTRL_1, in rt5682_set_jack_detect()
1050 regmap_update_bits(rt5682->regmap, RT5682_RC_CLK_CTRL, in rt5682_set_jack_detect()
1054 regmap_update_bits(rt5682->regmap, RT5682_PWR_ANLG_2, in rt5682_set_jack_detect()
1056 regmap_update_bits(rt5682->regmap, RT5682_IRQ_CTRL_2, in rt5682_set_jack_detect()
1059 regmap_update_bits(rt5682->regmap, RT5682_4BTN_IL_CMD_4, in rt5682_set_jack_detect()
1060 0x7f7f, (rt5682->pdata.btndet_delay << 8 | in rt5682_set_jack_detect()
1061 rt5682->pdata.btndet_delay)); in rt5682_set_jack_detect()
1062 regmap_update_bits(rt5682->regmap, RT5682_4BTN_IL_CMD_5, in rt5682_set_jack_detect()
1063 0x7f7f, (rt5682->pdata.btndet_delay << 8 | in rt5682_set_jack_detect()
1064 rt5682->pdata.btndet_delay)); in rt5682_set_jack_detect()
1065 regmap_update_bits(rt5682->regmap, RT5682_4BTN_IL_CMD_6, in rt5682_set_jack_detect()
1066 0x7f7f, (rt5682->pdata.btndet_delay << 8 | in rt5682_set_jack_detect()
1067 rt5682->pdata.btndet_delay)); in rt5682_set_jack_detect()
1068 regmap_update_bits(rt5682->regmap, RT5682_4BTN_IL_CMD_7, in rt5682_set_jack_detect()
1069 0x7f7f, (rt5682->pdata.btndet_delay << 8 | in rt5682_set_jack_detect()
1070 rt5682->pdata.btndet_delay)); in rt5682_set_jack_detect()
1072 &rt5682->jack_detect_work, in rt5682_set_jack_detect()
1077 regmap_update_bits(rt5682->regmap, RT5682_IRQ_CTRL_2, in rt5682_set_jack_detect()
1079 regmap_update_bits(rt5682->regmap, RT5682_RC_CLK_CTRL, in rt5682_set_jack_detect()
1084 dev_warn(component->dev, "Wrong JD source\n"); in rt5682_set_jack_detect()
1099 if (!rt5682->component || in rt5682_jack_detect_handler()
1100 !snd_soc_card_is_instantiated(rt5682->component->card)) { in rt5682_jack_detect_handler()
1103 &rt5682->jack_detect_work, msecs_to_jiffies(15)); in rt5682_jack_detect_handler()
1107 if (rt5682->is_sdw) { in rt5682_jack_detect_handler()
1108 if (pm_runtime_status_suspended(rt5682->slave->dev.parent)) { in rt5682_jack_detect_handler()
1109 dev_dbg(&rt5682->slave->dev, in rt5682_jack_detect_handler()
1116 dapm = snd_soc_component_get_dapm(rt5682->component); in rt5682_jack_detect_handler()
1119 mutex_lock(&rt5682->calibrate_mutex); in rt5682_jack_detect_handler()
1121 val = snd_soc_component_read(rt5682->component, RT5682_AJD1_CTRL) in rt5682_jack_detect_handler()
1125 if (rt5682->jack_type == 0) { in rt5682_jack_detect_handler()
1127 rt5682->jack_type = in rt5682_jack_detect_handler()
1128 rt5682_headset_detect(rt5682->component, 1); in rt5682_jack_detect_handler()
1129 rt5682->irq_work_delay_time = 0; in rt5682_jack_detect_handler()
1130 } else if ((rt5682->jack_type & SND_JACK_HEADSET) == in rt5682_jack_detect_handler()
1133 rt5682->jack_type = SND_JACK_HEADSET; in rt5682_jack_detect_handler()
1134 btn_type = rt5682_button_detect(rt5682->component); in rt5682_jack_detect_handler()
1137 * one click, double click and hold. However, in rt5682_jack_detect_handler()
1146 rt5682->jack_type |= SND_JACK_BTN_0; in rt5682_jack_detect_handler()
1151 rt5682->jack_type |= SND_JACK_BTN_1; in rt5682_jack_detect_handler()
1156 rt5682->jack_type |= SND_JACK_BTN_2; in rt5682_jack_detect_handler()
1161 rt5682->jack_type |= SND_JACK_BTN_3; in rt5682_jack_detect_handler()
1166 dev_err(rt5682->component->dev, in rt5682_jack_detect_handler()
1174 rt5682->jack_type = rt5682_headset_detect(rt5682->component, 0); in rt5682_jack_detect_handler()
1175 rt5682->irq_work_delay_time = 50; in rt5682_jack_detect_handler()
1178 mutex_unlock(&rt5682->calibrate_mutex); in rt5682_jack_detect_handler()
1181 snd_soc_jack_report(rt5682->hs_jack, rt5682->jack_type, in rt5682_jack_detect_handler()
1186 if (!rt5682->is_sdw) { in rt5682_jack_detect_handler()
1187 if (rt5682->jack_type & (SND_JACK_BTN_0 | SND_JACK_BTN_1 | in rt5682_jack_detect_handler()
1189 schedule_delayed_work(&rt5682->jd_check_work, 0); in rt5682_jack_detect_handler()
1191 cancel_delayed_work_sync(&rt5682->jd_check_work); in rt5682_jack_detect_handler()
1205 /* ADC Digital Volume Control */
1206 SOC_DOUBLE("STO1 ADC Capture Switch", RT5682_STO1_ADC_DIG_VOL,
1208 SOC_DOUBLE_TLV("STO1 ADC Capture Volume", RT5682_STO1_ADC_DIG_VOL,
1211 /* ADC Boost Volume Control */
1212 SOC_DOUBLE_TLV("STO1 ADC Boost Gain Volume", RT5682_STO1_ADC_BOOST,
1222 if (rt5682->sysclk < target) { in rt5682_div_sel()
1223 dev_err(rt5682->component->dev, in rt5682_div_sel()
1224 "sysclk rate %d is too low\n", rt5682->sysclk); in rt5682_div_sel()
1228 for (i = 0; i < size - 1; i++) { in rt5682_div_sel()
1229 dev_dbg(rt5682->component->dev, "div[%d]=%d\n", i, div[i]); in rt5682_div_sel()
1230 if (target * div[i] == rt5682->sysclk) in rt5682_div_sel()
1232 if (target * div[i + 1] > rt5682->sysclk) { in rt5682_div_sel()
1233 dev_dbg(rt5682->component->dev, in rt5682_div_sel()
1235 rt5682->sysclk); in rt5682_div_sel()
1240 if (target * div[i] < rt5682->sysclk) in rt5682_div_sel()
1241 dev_err(rt5682->component->dev, in rt5682_div_sel()
1242 "sysclk rate %d is too high\n", rt5682->sysclk); in rt5682_div_sel()
1244 return size - 1; in rt5682_div_sel()
1248 * set_dmic_clk - Set parameter of dmic.
1261 snd_soc_dapm_to_component(w->dapm); in set_dmic_clk()
1266 if (rt5682->pdata.dmic_clk_rate) in set_dmic_clk()
1267 dmic_clk_rate = rt5682->pdata.dmic_clk_rate; in set_dmic_clk()
1281 snd_soc_dapm_to_component(w->dapm); in set_filter_clk()
1287 if (rt5682->is_sdw) in set_filter_clk()
1292 if (w->shift == RT5682_PWR_ADC_S1F_BIT && in set_filter_clk()
1294 ref = 256 * rt5682->lrck[RT5682_AIF2]; in set_filter_clk()
1296 ref = 256 * rt5682->lrck[RT5682_AIF1]; in set_filter_clk()
1300 if (w->shift == RT5682_PWR_ADC_S1F_BIT) in set_filter_clk()
1308 /* select over sample rate */ in set_filter_clk()
1310 if (rt5682->sysclk <= 12288000 * div_o[idx]) in set_filter_clk()
1326 snd_soc_dapm_to_component(w->dapm); in is_sys_clk_from_pll1()
1341 snd_soc_dapm_to_component(w->dapm); in is_sys_clk_from_pll2()
1356 snd_soc_dapm_to_component(w->dapm); in is_using_asrc()
1358 switch (w->shift) { in is_using_asrc()
1397 SOC_DAPM_SINGLE("Stereo ADC Switch", RT5682_AD_DA_MIXER,
1404 SOC_DAPM_SINGLE("Stereo ADC Switch", RT5682_AD_DA_MIXER,
1431 /* MX-26 [13] [5] */
1433 "DAC MIX", "ADC"
1450 /* STO1 ADC Source */
1451 /* MX-26 [11:10] [3:2] */
1471 /* MX-26 [12] [4] */
1490 /* MX-79 [6:4] I2S1 ADC data location */
1507 SOC_DAPM_ENUM("IF1 ADC Slot location", rt5682_if1_adc_slot_enum);
1510 /* MX-2B [4], MX-2B [0]*/
1541 snd_soc_dapm_to_component(w->dapm); in rt5682_hp_event()
1580 snd_soc_dapm_to_component(w->dapm); in set_dmic_power()
1584 if (rt5682->pdata.dmic_delay) in set_dmic_power()
1585 delay = rt5682->pdata.dmic_delay; in set_dmic_power()
1602 if (!rt5682->jack_type) { in set_dmic_power()
1603 if (!snd_soc_dapm_get_pin_status(w->dapm, "MICBIAS")) in set_dmic_power()
1606 if (!snd_soc_dapm_get_pin_status(w->dapm, "Vref2")) in set_dmic_power()
1620 snd_soc_dapm_to_component(w->dapm); in rt5682_set_verf()
1624 switch (w->shift) { in rt5682_set_verf()
1639 switch (w->shift) { in rt5682_set_verf()
1709 SND_SOC_DAPM_SUPPLY_S("ADC STO1 ASRC", 1, RT5682_PLL_TRACK_1,
1757 /* ADC Mux */
1758 SND_SOC_DAPM_MUX("Stereo1 ADC L1 Mux", SND_SOC_NOPM, 0, 0,
1760 SND_SOC_DAPM_MUX("Stereo1 ADC R1 Mux", SND_SOC_NOPM, 0, 0,
1762 SND_SOC_DAPM_MUX("Stereo1 ADC L2 Mux", SND_SOC_NOPM, 0, 0,
1764 SND_SOC_DAPM_MUX("Stereo1 ADC R2 Mux", SND_SOC_NOPM, 0, 0,
1766 SND_SOC_DAPM_MUX("Stereo1 ADC L Mux", SND_SOC_NOPM, 0, 0,
1768 SND_SOC_DAPM_MUX("Stereo1 ADC R Mux", SND_SOC_NOPM, 0, 0,
1773 /* ADC Mixer */
1774 SND_SOC_DAPM_SUPPLY("ADC Stereo1 Filter", RT5682_PWR_DIG_2,
1777 SND_SOC_DAPM_MIXER("Stereo1 ADC MIXL", RT5682_STO1_ADC_DIG_VOL,
1780 SND_SOC_DAPM_MIXER("Stereo1 ADC MIXR", RT5682_STO1_ADC_DIG_VOL,
1784 /* ADC PGA */
1785 SND_SOC_DAPM_PGA("Stereo1 ADC MIX", SND_SOC_NOPM, 0, 0, NULL, 0),
1799 SND_SOC_DAPM_MUX("IF1 01 ADC Swap Mux", SND_SOC_NOPM, 0, 0,
1801 SND_SOC_DAPM_MUX("IF1 23 ADC Swap Mux", SND_SOC_NOPM, 0, 0,
1803 SND_SOC_DAPM_MUX("IF1 45 ADC Swap Mux", SND_SOC_NOPM, 0, 0,
1805 SND_SOC_DAPM_MUX("IF1 67 ADC Swap Mux", SND_SOC_NOPM, 0, 0,
1807 SND_SOC_DAPM_MUX("IF2 ADC Swap Mux", SND_SOC_NOPM, 0, 0,
1896 {"ADC Stereo1 Filter", NULL, "PLL1", is_sys_clk_from_pll1},
1897 {"ADC Stereo1 Filter", NULL, "PLL2B", is_sys_clk_from_pll2},
1898 {"ADC Stereo1 Filter", NULL, "PLL2F", is_sys_clk_from_pll2},
1904 {"ADC Stereo1 Filter", NULL, "ADC STO1 ASRC", is_using_asrc},
1906 {"ADC STO1 ASRC", NULL, "AD ASRC"},
1907 {"ADC STO1 ASRC", NULL, "DA ASRC"},
1908 {"ADC STO1 ASRC", NULL, "CLKDET"},
1934 {"Stereo1 ADC L Mux", "ADC1 L", "ADC1 L"},
1935 {"Stereo1 ADC L Mux", "ADC1 R", "ADC1 R"},
1936 {"Stereo1 ADC R Mux", "ADC1 L", "ADC1 L"},
1937 {"Stereo1 ADC R Mux", "ADC1 R", "ADC1 R"},
1939 {"Stereo1 ADC L1 Mux", "ADC", "Stereo1 ADC L Mux"},
1940 {"Stereo1 ADC L1 Mux", "DAC MIX", "Stereo1 DAC MIXL"},
1941 {"Stereo1 ADC L2 Mux", "DMIC", "DMIC L1"},
1942 {"Stereo1 ADC L2 Mux", "DAC MIX", "Stereo1 DAC MIXL"},
1944 {"Stereo1 ADC R1 Mux", "ADC", "Stereo1 ADC R Mux"},
1945 {"Stereo1 ADC R1 Mux", "DAC MIX", "Stereo1 DAC MIXR"},
1946 {"Stereo1 ADC R2 Mux", "DMIC", "DMIC R1"},
1947 {"Stereo1 ADC R2 Mux", "DAC MIX", "Stereo1 DAC MIXR"},
1949 {"Stereo1 ADC MIXL", "ADC1 Switch", "Stereo1 ADC L1 Mux"},
1950 {"Stereo1 ADC MIXL", "ADC2 Switch", "Stereo1 ADC L2 Mux"},
1951 {"Stereo1 ADC MIXL", NULL, "ADC Stereo1 Filter"},
1953 {"Stereo1 ADC MIXR", "ADC1 Switch", "Stereo1 ADC R1 Mux"},
1954 {"Stereo1 ADC MIXR", "ADC2 Switch", "Stereo1 ADC R2 Mux"},
1955 {"Stereo1 ADC MIXR", NULL, "ADC Stereo1 Filter"},
1957 {"Stereo1 ADC MIX", NULL, "Stereo1 ADC MIXL"},
1958 {"Stereo1 ADC MIX", NULL, "Stereo1 ADC MIXR"},
1960 {"IF1 01 ADC Swap Mux", "L/R", "Stereo1 ADC MIX"},
1961 {"IF1 01 ADC Swap Mux", "L/L", "Stereo1 ADC MIX"},
1962 {"IF1 01 ADC Swap Mux", "R/L", "Stereo1 ADC MIX"},
1963 {"IF1 01 ADC Swap Mux", "R/R", "Stereo1 ADC MIX"},
1964 {"IF1 23 ADC Swap Mux", "L/R", "Stereo1 ADC MIX"},
1965 {"IF1 23 ADC Swap Mux", "R/L", "Stereo1 ADC MIX"},
1966 {"IF1 23 ADC Swap Mux", "L/L", "Stereo1 ADC MIX"},
1967 {"IF1 23 ADC Swap Mux", "R/R", "Stereo1 ADC MIX"},
1968 {"IF1 45 ADC Swap Mux", "L/R", "Stereo1 ADC MIX"},
1969 {"IF1 45 ADC Swap Mux", "R/L", "Stereo1 ADC MIX"},
1970 {"IF1 45 ADC Swap Mux", "L/L", "Stereo1 ADC MIX"},
1971 {"IF1 45 ADC Swap Mux", "R/R", "Stereo1 ADC MIX"},
1972 {"IF1 67 ADC Swap Mux", "L/R", "Stereo1 ADC MIX"},
1973 {"IF1 67 ADC Swap Mux", "R/L", "Stereo1 ADC MIX"},
1974 {"IF1 67 ADC Swap Mux", "L/L", "Stereo1 ADC MIX"},
1975 {"IF1 67 ADC Swap Mux", "R/R", "Stereo1 ADC MIX"},
1977 {"IF1_ADC Mux", "Slot 0", "IF1 01 ADC Swap Mux"},
1978 {"IF1_ADC Mux", "Slot 2", "IF1 23 ADC Swap Mux"},
1979 {"IF1_ADC Mux", "Slot 4", "IF1 45 ADC Swap Mux"},
1980 {"IF1_ADC Mux", "Slot 6", "IF1 67 ADC Swap Mux"},
1984 {"IF2 ADC Swap Mux", "L/R", "Stereo1 ADC MIX"},
1985 {"IF2 ADC Swap Mux", "R/L", "Stereo1 ADC MIX"},
1986 {"IF2 ADC Swap Mux", "L/L", "Stereo1 ADC MIX"},
1987 {"IF2 ADC Swap Mux", "R/R", "Stereo1 ADC MIX"},
1988 {"ADCDAT Mux", "ADCDAT2", "IF2 ADC Swap Mux"},
2016 {"DAC1 MIXL", "Stereo ADC Switch", "Stereo1 ADC MIXL"},
2018 {"DAC1 MIXR", "Stereo ADC Switch", "Stereo1 ADC MIXR"},
2064 struct snd_soc_component *component = dai->component; in rt5682_set_tdm_slot()
2090 return -EINVAL; in rt5682_set_tdm_slot()
2099 return -EINVAL; in rt5682_set_tdm_slot()
2119 return -EINVAL; in rt5682_set_tdm_slot()
2133 struct snd_soc_component *component = dai->component; in rt5682_hw_params()
2138 rt5682->lrck[dai->id] = params_rate(params); in rt5682_hw_params()
2139 pre_div = rl6231_get_clk_info(rt5682->sysclk, rt5682->lrck[dai->id]); in rt5682_hw_params()
2143 dev_err(component->dev, "Unsupported frame size: %d\n", in rt5682_hw_params()
2145 return -EINVAL; in rt5682_hw_params()
2148 dev_dbg(dai->dev, "lrck is %dHz and pre_div is %d for iis %d\n", in rt5682_hw_params()
2149 rt5682->lrck[dai->id], pre_div, dai->id); in rt5682_hw_params()
2171 return -EINVAL; in rt5682_hw_params()
2174 switch (dai->id) { in rt5682_hw_params()
2178 if (rt5682->master[RT5682_AIF1]) { in rt5682_hw_params()
2183 (rt5682->sysclk_src) << RT5682_I2S_CLK_SRC_SFT); in rt5682_hw_params()
2197 if (rt5682->master[RT5682_AIF2]) { in rt5682_hw_params()
2212 dev_err(component->dev, "Invalid dai->id: %d\n", dai->id); in rt5682_hw_params()
2213 return -EINVAL; in rt5682_hw_params()
2221 struct snd_soc_component *component = dai->component; in rt5682_set_dai_fmt()
2227 rt5682->master[dai->id] = 1; in rt5682_set_dai_fmt()
2230 rt5682->master[dai->id] = 0; in rt5682_set_dai_fmt()
2233 return -EINVAL; in rt5682_set_dai_fmt()
2244 if (dai->id == RT5682_AIF1) in rt5682_set_dai_fmt()
2247 return -EINVAL; in rt5682_set_dai_fmt()
2250 if (dai->id == RT5682_AIF1) in rt5682_set_dai_fmt()
2254 return -EINVAL; in rt5682_set_dai_fmt()
2257 return -EINVAL; in rt5682_set_dai_fmt()
2276 return -EINVAL; in rt5682_set_dai_fmt()
2279 switch (dai->id) { in rt5682_set_dai_fmt()
2287 tdm_ctrl | rt5682->master[dai->id]); in rt5682_set_dai_fmt()
2290 if (rt5682->master[dai->id] == 0) in rt5682_set_dai_fmt()
2297 dev_err(component->dev, "Invalid dai->id: %d\n", dai->id); in rt5682_set_dai_fmt()
2298 return -EINVAL; in rt5682_set_dai_fmt()
2309 if (freq == rt5682->sysclk && clk_id == rt5682->sysclk_src) in rt5682_set_component_sysclk()
2330 dev_err(component->dev, "Invalid clock id (%d)\n", clk_id); in rt5682_set_component_sysclk()
2331 return -EINVAL; in rt5682_set_component_sysclk()
2336 if (rt5682->master[RT5682_AIF2]) { in rt5682_set_component_sysclk()
2342 rt5682->sysclk = freq; in rt5682_set_component_sysclk()
2343 rt5682->sysclk_src = clk_id; in rt5682_set_component_sysclk()
2345 dev_dbg(component->dev, "Sysclk is %dHz and clock id is %d\n", in rt5682_set_component_sysclk()
2360 if (source == rt5682->pll_src[pll_id] && in rt5682_set_component_pll()
2361 freq_in == rt5682->pll_in[pll_id] && in rt5682_set_component_pll()
2362 freq_out == rt5682->pll_out[pll_id]) in rt5682_set_component_pll()
2366 dev_dbg(component->dev, "PLL disabled\n"); in rt5682_set_component_pll()
2368 rt5682->pll_in[pll_id] = 0; in rt5682_set_component_pll()
2369 rt5682->pll_out[pll_id] = 0; in rt5682_set_component_pll()
2383 dev_err(component->dev, "Unknown PLL2 Source %d\n", in rt5682_set_component_pll()
2385 return -EINVAL; in rt5682_set_component_pll()
2395 dev_err(component->dev, "Unsupported input clock %d\n", in rt5682_set_component_pll()
2399 dev_dbg(component->dev, "PLL2F: fin=%d fout=%d bypass=%d m=%d n=%d k=%d\n", in rt5682_set_component_pll()
2407 dev_err(component->dev, "Unsupported input clock %d\n", in rt5682_set_component_pll()
2411 dev_dbg(component->dev, "PLL2B: fin=%d fout=%d bypass=%d m=%d n=%d k=%d\n", in rt5682_set_component_pll()
2451 dev_err(component->dev, "Unknown PLL1 Source %d\n", in rt5682_set_component_pll()
2453 return -EINVAL; in rt5682_set_component_pll()
2458 dev_err(component->dev, "Unsupported input clock %d\n", in rt5682_set_component_pll()
2463 dev_dbg(component->dev, "bypass=%d m=%d n=%d k=%d\n", in rt5682_set_component_pll()
2474 rt5682->pll_in[pll_id] = freq_in; in rt5682_set_component_pll()
2475 rt5682->pll_out[pll_id] = freq_out; in rt5682_set_component_pll()
2476 rt5682->pll_src[pll_id] = source; in rt5682_set_component_pll()
2483 struct snd_soc_component *component = dai->component; in rt5682_set_bclk1_ratio()
2486 rt5682->bclk[dai->id] = ratio; in rt5682_set_bclk1_ratio()
2506 dev_err(dai->dev, "Invalid bclk1 ratio %d\n", ratio); in rt5682_set_bclk1_ratio()
2507 return -EINVAL; in rt5682_set_bclk1_ratio()
2515 struct snd_soc_component *component = dai->component; in rt5682_set_bclk2_ratio()
2518 rt5682->bclk[dai->id] = ratio; in rt5682_set_bclk2_ratio()
2532 dev_err(dai->dev, "Invalid bclk2 ratio %d\n", ratio); in rt5682_set_bclk2_ratio()
2533 return -EINVAL; in rt5682_set_bclk2_ratio()
2546 regmap_update_bits(rt5682->regmap, RT5682_PWR_ANLG_1, in rt5682_set_bias_level()
2548 regmap_update_bits(rt5682->regmap, RT5682_PWR_DIG_1, in rt5682_set_bias_level()
2554 regmap_update_bits(rt5682->regmap, RT5682_PWR_DIG_1, in rt5682_set_bias_level()
2558 regmap_update_bits(rt5682->regmap, RT5682_PWR_DIG_1, in rt5682_set_bias_level()
2560 regmap_update_bits(rt5682->regmap, RT5682_PWR_ANLG_1, in rt5682_set_bias_level()
2577 if (!rt5682->master[RT5682_AIF1]) { in rt5682_clk_check()
2578 dev_dbg(rt5682->i2c_dev, "sysclk/dai not set correctly\n"); in rt5682_clk_check()
2593 return -EINVAL; in rt5682_wclk_prepare()
2595 component = rt5682->component; in rt5682_wclk_prepare()
2633 component = rt5682->component; in rt5682_wclk_unprepare()
2640 if (!rt5682->jack_type) in rt5682_wclk_unprepare()
2666 if (rt5682->lrck[RT5682_AIF1] != CLK_48 && in rt5682_wclk_recalc_rate()
2667 rt5682->lrck[RT5682_AIF1] != CLK_44) { in rt5682_wclk_recalc_rate()
2668 dev_warn(rt5682->i2c_dev, "%s: clk %s only support %d or %d Hz output\n", in rt5682_wclk_recalc_rate()
2673 return rt5682->lrck[RT5682_AIF1]; in rt5682_wclk_recalc_rate()
2685 return -EINVAL; in rt5682_wclk_round_rate()
2691 dev_warn(rt5682->i2c_dev, "%s: clk %s only support %d or %d Hz output\n", in rt5682_wclk_round_rate()
2712 return -EINVAL; in rt5682_wclk_set_rate()
2714 component = rt5682->component; in rt5682_wclk_set_rate()
2725 dev_warn(rt5682->i2c_dev, in rt5682_wclk_set_rate()
2730 dev_warn(rt5682->i2c_dev, "clk %s only support %d Hz input\n", in rt5682_wclk_set_rate()
2744 rt5682->lrck[RT5682_AIF1] = rate; in rt5682_wclk_set_rate()
2746 pre_div = rl6231_get_clk_info(rt5682->sysclk, rate); in rt5682_wclk_set_rate()
2751 (rt5682->sysclk_src) << RT5682_I2S_CLK_SRC_SFT); in rt5682_wclk_set_rate()
2764 regmap_read(rt5682->regmap, RT5682_TDM_TCON_CTRL, &bclks_per_wclk); in rt5682_bclk_recalc_rate()
2805 return -EINVAL; in rt5682_bclk_round_rate()
2830 return -EINVAL; in rt5682_bclk_set_rate()
2832 component = rt5682->component; in rt5682_bclk_set_rate()
2837 if (dai->id == RT5682_AIF1) in rt5682_bclk_set_rate()
2840 dev_err(rt5682->i2c_dev, "dai %d not found in component\n", in rt5682_bclk_set_rate()
2842 return -ENODEV; in rt5682_bclk_set_rate()
2862 struct device *dev = rt5682->i2c_dev; in rt5682_register_dai_clks()
2863 struct rt5682_platform_data *pdata = &rt5682->pdata; in rt5682_register_dai_clks()
2871 dai_clk_hw = &rt5682->dai_clks_hw[i]; in rt5682_register_dai_clks()
2876 if (rt5682->mclk) { in rt5682_register_dai_clks()
2877 parent = __clk_get_hw(rt5682->mclk); in rt5682_register_dai_clks()
2884 parent = &rt5682->dai_clks_hw[RT5682_DAI_WCLK_IDX]; in rt5682_register_dai_clks()
2890 return -EINVAL; in rt5682_register_dai_clks()
2893 init.name = pdata->dai_clk_names[i]; in rt5682_register_dai_clks()
2896 dai_clk_hw->init = &init; in rt5682_register_dai_clks()
2905 if (dev->of_node) { in rt5682_register_dai_clks()
2928 unsigned long time; in rt5682_probe() local
2929 struct snd_soc_dapm_context *dapm = &component->dapm; in rt5682_probe()
2931 rt5682->component = component; in rt5682_probe()
2933 if (rt5682->is_sdw) { in rt5682_probe()
2934 slave = rt5682->slave; in rt5682_probe()
2935 time = wait_for_completion_timeout( in rt5682_probe()
2936 &slave->initialization_complete, in rt5682_probe()
2938 if (!time) { in rt5682_probe()
2939 dev_err(&slave->dev, "Initialization not complete, timed out\n"); in rt5682_probe()
2940 return -ETIMEDOUT; in rt5682_probe()
2963 if (rt5682->is_sdw) in rt5682_suspend()
2966 if (rt5682->irq) in rt5682_suspend()
2967 disable_irq(rt5682->irq); in rt5682_suspend()
2969 cancel_delayed_work_sync(&rt5682->jack_detect_work); in rt5682_suspend()
2970 cancel_delayed_work_sync(&rt5682->jd_check_work); in rt5682_suspend()
2971 if (rt5682->hs_jack && (rt5682->jack_type & SND_JACK_HEADSET) == SND_JACK_HEADSET) { in rt5682_suspend()
2990 /* enter SAR ADC power saving mode */ in rt5682_suspend()
3006 regcache_cache_only(rt5682->regmap, true); in rt5682_suspend()
3007 regcache_mark_dirty(rt5682->regmap); in rt5682_suspend()
3015 if (rt5682->is_sdw) in rt5682_resume()
3018 regcache_cache_only(rt5682->regmap, false); in rt5682_resume()
3019 regcache_sync(rt5682->regmap); in rt5682_resume()
3021 if (rt5682->hs_jack && (rt5682->jack_type & SND_JACK_HEADSET) == SND_JACK_HEADSET) { in rt5682_resume()
3033 rt5682->jack_type = 0; in rt5682_resume()
3035 &rt5682->jack_detect_work, msecs_to_jiffies(0)); in rt5682_resume()
3037 if (rt5682->irq) in rt5682_resume()
3038 enable_irq(rt5682->irq); in rt5682_resume()
3085 device_property_read_u32(dev, "realtek,dmic1-data-pin", in rt5682_parse_dt()
3086 &rt5682->pdata.dmic1_data_pin); in rt5682_parse_dt()
3087 device_property_read_u32(dev, "realtek,dmic1-clk-pin", in rt5682_parse_dt()
3088 &rt5682->pdata.dmic1_clk_pin); in rt5682_parse_dt()
3089 device_property_read_u32(dev, "realtek,jd-src", in rt5682_parse_dt()
3090 &rt5682->pdata.jd_src); in rt5682_parse_dt()
3091 device_property_read_u32(dev, "realtek,btndet-delay", in rt5682_parse_dt()
3092 &rt5682->pdata.btndet_delay); in rt5682_parse_dt()
3093 device_property_read_u32(dev, "realtek,dmic-clk-rate-hz", in rt5682_parse_dt()
3094 &rt5682->pdata.dmic_clk_rate); in rt5682_parse_dt()
3095 device_property_read_u32(dev, "realtek,dmic-delay-ms", in rt5682_parse_dt()
3096 &rt5682->pdata.dmic_delay); in rt5682_parse_dt()
3098 if (device_property_read_string_array(dev, "clock-output-names", in rt5682_parse_dt()
3099 rt5682->pdata.dai_clk_names, in rt5682_parse_dt()
3102 rt5682->pdata.dai_clk_names[RT5682_DAI_WCLK_IDX], in rt5682_parse_dt()
3103 rt5682->pdata.dai_clk_names[RT5682_DAI_BCLK_IDX]); in rt5682_parse_dt()
3105 rt5682->pdata.dmic_clk_driving_high = device_property_read_bool(dev, in rt5682_parse_dt()
3106 "realtek,dmic-clk-driving-high"); in rt5682_parse_dt()
3114 rt5682->ldo1_en = devm_gpiod_get_optional(dev, in rt5682_get_ldo1()
3115 "realtek,ldo1-en", in rt5682_get_ldo1()
3117 if (IS_ERR(rt5682->ldo1_en)) { in rt5682_get_ldo1()
3119 return PTR_ERR(rt5682->ldo1_en); in rt5682_get_ldo1()
3130 mutex_lock(&rt5682->calibrate_mutex); in rt5682_calibrate()
3133 regmap_write(rt5682->regmap, RT5682_I2C_CTRL, 0x000f); in rt5682_calibrate()
3134 regmap_write(rt5682->regmap, RT5682_PWR_ANLG_1, 0xa2af); in rt5682_calibrate()
3136 regmap_write(rt5682->regmap, RT5682_PWR_ANLG_1, 0xf2af); in rt5682_calibrate()
3137 regmap_write(rt5682->regmap, RT5682_MICBIAS_2, 0x0300); in rt5682_calibrate()
3138 regmap_write(rt5682->regmap, RT5682_GLB_CLK, 0x8000); in rt5682_calibrate()
3139 regmap_write(rt5682->regmap, RT5682_PWR_DIG_1, 0x0100); in rt5682_calibrate()
3140 regmap_write(rt5682->regmap, RT5682_HP_IMP_SENS_CTRL_19, 0x3800); in rt5682_calibrate()
3141 regmap_write(rt5682->regmap, RT5682_CHOP_DAC, 0x3000); in rt5682_calibrate()
3142 regmap_write(rt5682->regmap, RT5682_CALIB_ADC_CTRL, 0x7005); in rt5682_calibrate()
3143 regmap_write(rt5682->regmap, RT5682_STO1_ADC_MIXER, 0x686c); in rt5682_calibrate()
3144 regmap_write(rt5682->regmap, RT5682_CAL_REC, 0x0d0d); in rt5682_calibrate()
3145 regmap_write(rt5682->regmap, RT5682_HP_CALIB_CTRL_2, 0x0321); in rt5682_calibrate()
3146 regmap_write(rt5682->regmap, RT5682_HP_LOGIC_CTRL_2, 0x0004); in rt5682_calibrate()
3147 regmap_write(rt5682->regmap, RT5682_HP_CALIB_CTRL_1, 0x7c00); in rt5682_calibrate()
3148 regmap_write(rt5682->regmap, RT5682_HP_CALIB_CTRL_3, 0x06a1); in rt5682_calibrate()
3149 regmap_write(rt5682->regmap, RT5682_A_DAC1_MUX, 0x0311); in rt5682_calibrate()
3150 regmap_write(rt5682->regmap, RT5682_HP_CALIB_CTRL_1, 0x7c00); in rt5682_calibrate()
3152 regmap_write(rt5682->regmap, RT5682_HP_CALIB_CTRL_1, 0xfc00); in rt5682_calibrate()
3155 regmap_read(rt5682->regmap, RT5682_HP_CALIB_STA_1, &value); in rt5682_calibrate()
3163 dev_err(rt5682->component->dev, "HP Calibration Failure\n"); in rt5682_calibrate()
3166 regmap_write(rt5682->regmap, RT5682_PWR_ANLG_1, 0x002f); in rt5682_calibrate()
3167 regmap_write(rt5682->regmap, RT5682_MICBIAS_2, 0x0080); in rt5682_calibrate()
3168 regmap_write(rt5682->regmap, RT5682_GLB_CLK, 0x0000); in rt5682_calibrate()
3169 regmap_write(rt5682->regmap, RT5682_PWR_DIG_1, 0x0000); in rt5682_calibrate()
3170 regmap_write(rt5682->regmap, RT5682_CHOP_DAC, 0x2000); in rt5682_calibrate()
3171 regmap_write(rt5682->regmap, RT5682_CALIB_ADC_CTRL, 0x2005); in rt5682_calibrate()
3172 regmap_write(rt5682->regmap, RT5682_STO1_ADC_MIXER, 0xc0c4); in rt5682_calibrate()
3173 regmap_write(rt5682->regmap, RT5682_CAL_REC, 0x0c0c); in rt5682_calibrate()
3175 mutex_unlock(&rt5682->calibrate_mutex); in rt5682_calibrate()