Lines Matching refs:clk_src
1216 * @clk_src: clock source
1227 unsigned int filter_mask, unsigned int clk_src)
1237 switch (clk_src) {
1261 | (clk_src << RT5677_DA_STO_CLK_SEL_SFT);
1267 | (clk_src << RT5677_DA_MONO2L_CLK_SEL_SFT);
1273 | (clk_src << RT5677_DA_MONO2R_CLK_SEL_SFT);
1284 | (clk_src << RT5677_DA_MONO3L_CLK_SEL_SFT);
1290 | (clk_src << RT5677_DA_MONO3R_CLK_SEL_SFT);
1296 | (clk_src << RT5677_DA_MONO4L_CLK_SEL_SFT);
1302 | (clk_src << RT5677_DA_MONO4R_CLK_SEL_SFT);
1313 | (clk_src << RT5677_AD_STO1_CLK_SEL_SFT);
1319 | (clk_src << RT5677_AD_STO2_CLK_SEL_SFT);
1325 | (clk_src << RT5677_AD_STO3_CLK_SEL_SFT);
1331 | (clk_src << RT5677_AD_STO4_CLK_SEL_SFT);
1342 | (clk_src << RT5677_AD_MONOL_CLK_SEL_SFT);
1348 | (clk_src << RT5677_AD_MONOR_CLK_SEL_SFT);
1359 | (clk_src << RT5677_DSP_OB_0_3_CLK_SEL_SFT);
1365 | (clk_src << RT5677_DSP_OB_4_7_CLK_SEL_SFT);
1376 | ((clk_src - 1) << RT5677_I2S1_CLK_SEL_SFT);
1382 | ((clk_src - 1) << RT5677_I2S2_CLK_SEL_SFT);
1388 | ((clk_src - 1) << RT5677_I2S3_CLK_SEL_SFT);
1394 | ((clk_src - 1) << RT5677_I2S4_CLK_SEL_SFT);