Lines Matching +full:headset +full:- +full:detect +full:- +full:gpios
1 // SPDX-License-Identifier: GPL-2.0-only
3 * rt5677.c -- RT5677 ALSA SoC audio codec driver
29 #include <sound/soc-dapm.h>
35 #include "rt5677-spi.h"
552 * rt5677_dsp_mode_i2c_write_addr - Write value to address on DSP mode.
563 struct snd_soc_component *component = rt5677->component;
566 mutex_lock(&rt5677->dsp_cmd_lock);
568 ret = regmap_write(rt5677->regmap_physical, RT5677_DSP_I2C_ADDR_MSB,
571 dev_err(component->dev, "Failed to set addr msb value: %d\n", ret);
575 ret = regmap_write(rt5677->regmap_physical, RT5677_DSP_I2C_ADDR_LSB,
578 dev_err(component->dev, "Failed to set addr lsb value: %d\n", ret);
582 ret = regmap_write(rt5677->regmap_physical, RT5677_DSP_I2C_DATA_MSB,
585 dev_err(component->dev, "Failed to set data msb value: %d\n", ret);
589 ret = regmap_write(rt5677->regmap_physical, RT5677_DSP_I2C_DATA_LSB,
592 dev_err(component->dev, "Failed to set data lsb value: %d\n", ret);
596 ret = regmap_write(rt5677->regmap_physical, RT5677_DSP_I2C_OP_CODE,
599 dev_err(component->dev, "Failed to set op code value: %d\n", ret);
604 mutex_unlock(&rt5677->dsp_cmd_lock);
610 * rt5677_dsp_mode_i2c_read_addr - Read value from address on DSP mode.
621 struct snd_soc_component *component = rt5677->component;
625 mutex_lock(&rt5677->dsp_cmd_lock);
627 ret = regmap_write(rt5677->regmap_physical, RT5677_DSP_I2C_ADDR_MSB,
630 dev_err(component->dev, "Failed to set addr msb value: %d\n", ret);
634 ret = regmap_write(rt5677->regmap_physical, RT5677_DSP_I2C_ADDR_LSB,
637 dev_err(component->dev, "Failed to set addr lsb value: %d\n", ret);
641 ret = regmap_write(rt5677->regmap_physical, RT5677_DSP_I2C_OP_CODE,
644 dev_err(component->dev, "Failed to set op code value: %d\n", ret);
648 regmap_read(rt5677->regmap_physical, RT5677_DSP_I2C_DATA_MSB, &msb);
649 regmap_read(rt5677->regmap_physical, RT5677_DSP_I2C_DATA_LSB, &lsb);
653 mutex_unlock(&rt5677->dsp_cmd_lock);
659 * rt5677_dsp_mode_i2c_write - Write register on DSP mode.
675 * rt5677_dsp_mode_i2c_read - Read register on DSP mode.
697 regmap_update_bits(rt5677->regmap, RT5677_PWR_DSP1,
699 rt5677->is_dsp_mode = true;
701 regmap_update_bits(rt5677->regmap, RT5677_PWR_DSP1,
703 rt5677->is_dsp_mode = false;
709 struct snd_soc_dapm_context *dapm = snd_soc_component_to_dapm(rt5677->component);
718 regmap_update_bits(rt5677->regmap, RT5677_DMIC_CTRL1,
722 regmap_update_bits(rt5677->regmap, RT5677_CLK_TREE_CTRL1,
726 regmap_write(rt5677->regmap, RT5677_GLB_CLK2,
730 regmap_write(rt5677->regmap, RT5677_VAD_CTRL2, 0x013f);
732 regmap_write(rt5677->regmap, RT5677_VAD_CTRL3, 0x0ae5);
737 regmap_update_bits(rt5677->regmap, RT5677_VAD_CTRL4,
740 /* Minimum frame level within a pre-determined duration = 32 frames
743 * SAD Buffer Over-Writing = enable
750 regmap_write(rt5677->regmap, RT5677_VAD_CTRL1,
756 /* VAD/SAD is not routed to the IRQ output (i.e. MX-BE[14] = 0), but it
763 regmap_update_bits(rt5677->regmap, RT5677_PR_BASE + RT5677_BIAS_CUR4,
769 regmap_update_bits(rt5677->regmap, RT5677_PWR_ANLG1,
776 regmap_update_bits(rt5677->regmap, RT5677_PWR_ANLG2,
786 regmap_write(rt5677->regmap, RT5677_PWR_DSP2,
799 regmap_write(rt5677->regmap, RT5677_PWR_DSP1,
813 struct snd_soc_component *component = rt5677->component;
820 return -ENOMEM;
826 if (strncmp(elf_hdr->e_ident, ELFMAG, sizeof(ELFMAG) - 1))
827 dev_err(component->dev, "Wrong ELF header prefix\n");
828 if (elf_hdr->e_ehsize != sizeof(Elf32_Ehdr))
829 dev_err(component->dev, "Wrong ELF header size\n");
830 if (elf_hdr->e_machine != EM_XTENSA)
831 dev_err(component->dev, "Wrong DSP code file\n");
833 if (len < elf_hdr->e_phoff)
834 return -ENOMEM;
835 pr_hdr = (Elf32_Phdr *)(buf + elf_hdr->e_phoff);
836 for (i = 0; i < elf_hdr->e_phnum; i++) {
838 if (pr_hdr->p_paddr && pr_hdr->p_filesz) {
839 dev_info(component->dev, "Load 0x%x bytes to 0x%x\n",
840 pr_hdr->p_filesz, pr_hdr->p_paddr);
842 ret = rt5677_spi_write(pr_hdr->p_paddr,
843 buf + pr_hdr->p_offset,
844 pr_hdr->p_filesz);
846 dev_err(component->dev, "Load firmware failed %d\n",
857 struct device *dev = rt5677->component->dev;
866 dev_info(dev, "Requested rt5677_elf_vad (%zu)\n", fwp->size);
868 ret = rt5677_parse_and_load_dsp(rt5677, fwp->data, fwp->size);
876 rt5677->dsp_vad_en_request = on;
877 rt5677->dsp_vad_en = on;
880 return -ENXIO;
882 schedule_delayed_work(&rt5677->dsp_work, 0);
891 bool enable = rt5677->dsp_vad_en;
895 dev_info(rt5677->component->dev, "DSP VAD: enable=%d, activity=%d\n",
902 * output so that jack detect works. When a hotword is detected,
905 * the GPIO1 pin, due to either jack detect event or hotword
916 regmap_read(rt5677->regmap, RT5677_PWR_DSP_ST, &val);
922 dev_err(rt5677->component->dev, "DSP Boot Timed Out!");
937 regmap_update_bits(rt5677->regmap, RT5677_PWR_DSP1,
943 mutex_lock(&rt5677->irq_lock);
945 regmap_update_bits(rt5677->regmap, RT5677_PWR_DSP1,
951 regmap_write(rt5677->regmap, RT5677_VAD_CTRL1, 0x2184);
953 /* Set GPIO1 pin back to be IRQ output for jack detect */
954 regmap_update_bits(rt5677->regmap, RT5677_GPIO_CTRL1,
957 mutex_unlock(&rt5677->irq_lock);
961 static const DECLARE_TLV_DB_SCALE(dac_vol_tlv, -6525, 75, 0);
962 static const DECLARE_TLV_DB_SCALE(adc_vol_tlv, -1725, 75, 0);
964 static const DECLARE_TLV_DB_SCALE(st_vol_tlv, -4650, 150, 0);
983 ucontrol->value.integer.value[0] = rt5677->dsp_vad_en_request;
993 rt5677_set_dsp_vad(component, !!ucontrol->value.integer.value[0]);
1075 * set_dmic_clk - Set parameter of dmic.
1087 struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm);
1091 rate = rt5677->sysclk / rl6231_get_pre_div(rt5677->regmap,
1095 dev_err(component->dev, "Failed to set DMIC clock\n");
1097 regmap_update_bits(rt5677->regmap, RT5677_DMIC_CTRL1,
1105 struct snd_soc_component *component = snd_soc_dapm_to_component(source->dapm);
1109 regmap_read(rt5677->regmap, RT5677_GLB_CLK1, &val);
1120 struct snd_soc_component *component = snd_soc_dapm_to_component(source->dapm);
1124 if (source->reg == RT5677_ASRC_1) {
1125 switch (source->shift) {
1146 switch (source->shift) {
1188 regmap_read(rt5677->regmap, reg, &val);
1203 struct snd_soc_component *component = snd_soc_dapm_to_component(source->dapm);
1206 if (rt5677->sysclk > rt5677->lrck[RT5677_AIF1] * 384)
1213 * rt5677_sel_asrc_clk_src - select ASRC clock source for a set of filters
1254 return -EINVAL;
1277 regmap_update_bits(rt5677->regmap, RT5677_ASRC_3, asrc3_mask,
1306 regmap_update_bits(rt5677->regmap, RT5677_ASRC_4, asrc4_mask,
1335 regmap_update_bits(rt5677->regmap, RT5677_ASRC_5, asrc5_mask,
1352 regmap_update_bits(rt5677->regmap, RT5677_ASRC_6, asrc6_mask,
1369 regmap_update_bits(rt5677->regmap, RT5677_ASRC_7, asrc7_mask,
1376 | ((clk_src - 1) << RT5677_I2S1_CLK_SEL_SFT);
1382 | ((clk_src - 1) << RT5677_I2S2_CLK_SEL_SFT);
1388 | ((clk_src - 1) << RT5677_I2S3_CLK_SEL_SFT);
1394 | ((clk_src - 1) << RT5677_I2S4_CLK_SEL_SFT);
1398 regmap_update_bits(rt5677->regmap, RT5677_ASRC_8, asrc8_mask,
1408 struct snd_soc_component *component = snd_soc_dapm_to_component(source->dapm);
1412 switch (source->shift) {
1414 regmap_read(rt5677->regmap, RT5677_ASRC_5, &asrc_setting);
1420 regmap_read(rt5677->regmap, RT5677_ASRC_5, &asrc_setting);
1426 regmap_read(rt5677->regmap, RT5677_ASRC_5, &asrc_setting);
1432 regmap_read(rt5677->regmap, RT5677_ASRC_5, &asrc_setting);
1438 regmap_read(rt5677->regmap, RT5677_ASRC_6, &asrc_setting);
1444 regmap_read(rt5677->regmap, RT5677_ASRC_6, &asrc_setting);
1737 /* DAC1 L/R Source */ /* MX-29 [10:8] */
1750 /* ADDA1 L/R Source */ /* MX-29 [1:0] */
1763 /*DAC2 L/R Source*/ /* MX-1B [6:4] [2:0] */
1788 /*DAC3 L/R Source*/ /* MX-16 [6:4] [2:0] */
1813 /*DAC4 L/R Source*/ /* MX-16 [14:12] [10:8] */
1838 /* In/OutBound Source Pass SRC */ /* MX-A5 [3] [4] [0] [1] [2] */
1878 /* Stereo ADC Source 2 */ /* MX-27 MX26 MX25 [11:10] */
1904 /* DMIC Source */ /* MX-28 [9:8][1:0] MX-27 MX-26 MX-25 MX-24 [9:8] */
1951 /* Stereo2 ADC Source */ /* MX-26 [0] */
1963 /* Stereo1 ADC Source 1 */ /* MX-27 MX26 MX25 [13:12] */
1989 /* Mono ADC Left Source 2 */ /* MX-28 [11:10] */
2001 /* Mono ADC Left Source 1 */ /* MX-28 [13:12] */
2013 /* Mono ADC Right Source 2 */ /* MX-28 [3:2] */
2025 /* Mono ADC Right Source 1 */ /* MX-28 [5:4] */
2037 /* Stereo4 ADC Source 2 */ /* MX-24 [11:10] */
2050 /* Stereo4 ADC Source 1 */ /* MX-24 [13:12] */
2062 /* InBound0/1 Source */ /* MX-A3 [14:12] */
2075 /* InBound2/3 Source */ /* MX-A3 [10:8] */
2088 /* InBound4/5 Source */ /* MX-A3 [6:4] */
2101 /* InBound6 Source */ /* MX-A3 [2:0] */
2114 /* InBound7 Source */ /* MX-A4 [14:12] */
2127 /* InBound8 Source */ /* MX-A4 [10:8] */
2140 /* InBound9 Source */ /* MX-A4 [6:4] */
2153 /* VAD Source */ /* MX-9F [6:4] */
2166 /* Sidetone Source */ /* MX-13 [11:9] */
2178 /* DAC1/2 Source */ /* MX-15 [1:0] */
2190 /* DAC3 Source */ /* MX-15 [5:4] */
2202 /* PDM channel Source */ /* MX-31 [13:12][9:8][5:4][1:0] */
2235 /* TDM IF1/2 SLB ADC1 Data Selection */ /* MX-3C MX-41 [5:4] MX-08 [1:0] */
2261 /* TDM IF1/2 SLB ADC2 Data Selection */ /* MX-3C MX-41 [7:6] MX-08 [3:2] */
2287 /* TDM IF1/2 SLB ADC3 Data Selection */ /* MX-3C MX-41 [9:8] MX-08 [5:4] */
2313 /* TDM IF1/2 SLB ADC4 Data Selection */ /* MX-3C MX-41 [11:10] MX-08 [7:6] */
2339 /* Interface3/4 ADC Data Input */ /* MX-2F [3:0] MX-30 [7:4] */
2359 /* TDM IF1/2 ADC Data Selection */ /* MX-3B MX-40 [7:6][5:4][3:2][1:0] */
2420 /* TDM IF1 ADC Data Selection */ /* MX-3C [2:0] */
2433 /* TDM IF2 ADC Data Selection */ /* MX-41[2:0] */
2446 /* TDM IF1/2 DAC Data Selection */ /* MX-3E[14:12][10:8][6:4][2:0]
2447 MX-3F[14:12][10:8][6:4][2:0]
2448 MX-43[14:12][10:8][6:4][2:0]
2449 MX-44[14:12][10:8][6:4][2:0] */
2569 struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm);
2574 regmap_update_bits(rt5677->regmap, RT5677_PWR_ANLG2,
2579 regmap_update_bits(rt5677->regmap, RT5677_PWR_ANLG2,
2593 struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm);
2598 regmap_update_bits(rt5677->regmap, RT5677_PWR_ANLG2,
2603 regmap_update_bits(rt5677->regmap, RT5677_PWR_ANLG2,
2617 struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm);
2622 regmap_update_bits(rt5677->regmap, RT5677_PLL1_CTRL2, 0x2, 0x2);
2626 regmap_update_bits(rt5677->regmap, RT5677_PLL1_CTRL2, 0x2, 0x0);
2639 struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm);
2644 regmap_update_bits(rt5677->regmap, RT5677_PLL2_CTRL2, 0x2, 0x2);
2648 regmap_update_bits(rt5677->regmap, RT5677_PLL2_CTRL2, 0x2, 0x0);
2661 struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm);
2666 regmap_update_bits(rt5677->regmap, RT5677_PWR_ANLG2,
2673 regmap_update_bits(rt5677->regmap, RT5677_PWR_ANLG2,
2688 struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm);
2694 regmap_read(rt5677->regmap, RT5677_TDM1_CTRL2, &value);
2696 regmap_update_bits(rt5677->regmap, RT5677_TDM1_CTRL1,
2711 struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm);
2717 regmap_read(rt5677->regmap, RT5677_TDM2_CTRL2, &value);
2719 regmap_update_bits(rt5677->regmap, RT5677_TDM2_CTRL1,
2734 struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm);
2741 !rt5677->is_vref_slow) {
2743 regmap_update_bits(rt5677->regmap, RT5677_PWR_ANLG1,
2746 rt5677->is_vref_slow = true;
3733 * there is an active path going from system playback -> "DAC1 FS" ->
3734 * IB01 Mux -> DSP Buffer -> hotword stream. This wrong path confuses
4290 struct snd_soc_component *component = dai->component;
4295 rt5677->lrck[dai->id] = params_rate(params);
4296 pre_div = rl6231_get_clk_info(rt5677->sysclk, rt5677->lrck[dai->id]);
4298 dev_err(component->dev, "Unsupported clock setting: sysclk=%dHz lrck=%dHz\n",
4299 rt5677->sysclk, rt5677->lrck[dai->id]);
4300 return -EINVAL;
4304 dev_err(component->dev, "Unsupported frame size: %d\n", frame_size);
4305 return -EINVAL;
4308 rt5677->bclk[dai->id] = rt5677->lrck[dai->id] * (32 << bclk_ms);
4310 dev_dbg(dai->dev, "bclk is %dHz and lrck is %dHz\n",
4311 rt5677->bclk[dai->id], rt5677->lrck[dai->id]);
4312 dev_dbg(dai->dev, "bclk_ms is %d and pre_div is %d for iis %d\n",
4313 bclk_ms, pre_div, dai->id);
4328 return -EINVAL;
4331 switch (dai->id) {
4335 regmap_update_bits(rt5677->regmap, RT5677_I2S1_SDP,
4337 regmap_update_bits(rt5677->regmap, RT5677_CLK_TREE_CTRL1,
4343 regmap_update_bits(rt5677->regmap, RT5677_I2S2_SDP,
4345 regmap_update_bits(rt5677->regmap, RT5677_CLK_TREE_CTRL1,
4352 regmap_update_bits(rt5677->regmap, RT5677_I2S3_SDP,
4354 regmap_update_bits(rt5677->regmap, RT5677_CLK_TREE_CTRL1,
4361 regmap_update_bits(rt5677->regmap, RT5677_I2S4_SDP,
4363 regmap_update_bits(rt5677->regmap, RT5677_CLK_TREE_CTRL1,
4375 struct snd_soc_component *component = dai->component;
4381 rt5677->master[dai->id] = 1;
4385 rt5677->master[dai->id] = 0;
4388 return -EINVAL;
4398 return -EINVAL;
4414 return -EINVAL;
4417 switch (dai->id) {
4419 regmap_update_bits(rt5677->regmap, RT5677_I2S1_SDP,
4424 regmap_update_bits(rt5677->regmap, RT5677_I2S2_SDP,
4429 regmap_update_bits(rt5677->regmap, RT5677_I2S3_SDP,
4434 regmap_update_bits(rt5677->regmap, RT5677_I2S4_SDP,
4449 struct snd_soc_component *component = dai->component;
4453 if (freq == rt5677->sysclk && clk_id == rt5677->sysclk_src)
4467 dev_err(component->dev, "Invalid clock id (%d)\n", clk_id);
4468 return -EINVAL;
4470 regmap_update_bits(rt5677->regmap, RT5677_GLB_CLK1,
4472 rt5677->sysclk = freq;
4473 rt5677->sysclk_src = clk_id;
4475 dev_dbg(dai->dev, "Sysclk is %dHz and clock id is %d\n", freq, clk_id);
4481 * rt5677_pll_calc - Calcualte PLL M/N/K code.
4494 return -EINVAL;
4502 struct snd_soc_component *component = dai->component;
4507 if (source == rt5677->pll_src && freq_in == rt5677->pll_in &&
4508 freq_out == rt5677->pll_out)
4512 dev_dbg(component->dev, "PLL disabled\n");
4514 rt5677->pll_in = 0;
4515 rt5677->pll_out = 0;
4516 regmap_update_bits(rt5677->regmap, RT5677_GLB_CLK1,
4523 regmap_update_bits(rt5677->regmap, RT5677_GLB_CLK1,
4530 switch (dai->id) {
4532 regmap_update_bits(rt5677->regmap, RT5677_GLB_CLK1,
4536 regmap_update_bits(rt5677->regmap, RT5677_GLB_CLK1,
4540 regmap_update_bits(rt5677->regmap, RT5677_GLB_CLK1,
4544 regmap_update_bits(rt5677->regmap, RT5677_GLB_CLK1,
4552 dev_err(component->dev, "Unknown PLL source %d\n", source);
4553 return -EINVAL;
4558 dev_err(component->dev, "Unsupported input clock %d\n", freq_in);
4562 dev_dbg(component->dev, "m_bypass=%d m=%d n=%d k=%d\n",
4566 regmap_write(rt5677->regmap, RT5677_PLL1_CTRL1,
4568 regmap_write(rt5677->regmap, RT5677_PLL1_CTRL2,
4572 rt5677->pll_in = freq_in;
4573 rt5677->pll_out = freq_out;
4574 rt5677->pll_src = source;
4582 struct snd_soc_component *component = dai->component;
4622 switch (dai->id) {
4624 regmap_update_bits(rt5677->regmap, RT5677_TDM1_CTRL1, 0x1f00,
4626 regmap_update_bits(rt5677->regmap, RT5677_DIG_MISC, 0x8000,
4630 regmap_update_bits(rt5677->regmap, RT5677_TDM2_CTRL1, 0x1f00,
4632 regmap_update_bits(rt5677->regmap, RT5677_DIG_MISC, 0x80,
4656 regmap_update_bits(rt5677->regmap, RT5677_PWR_ANLG1,
4660 regmap_update_bits(rt5677->regmap,
4663 regmap_update_bits(rt5677->regmap, RT5677_PWR_ANLG1,
4669 rt5677->is_vref_slow = false;
4670 regmap_update_bits(rt5677->regmap, RT5677_PWR_ANLG2,
4672 regmap_update_bits(rt5677->regmap, RT5677_DIG_MISC,
4679 rt5677->dsp_vad_en_request) {
4680 /* Re-enable the DSP if it was turned off at suspend */
4681 rt5677->dsp_vad_en = true;
4683 schedule_delayed_work(&rt5677->dsp_work,
4689 flush_delayed_work(&rt5677->dsp_work);
4690 if (rt5677->is_dsp_mode) {
4692 rt5677->dsp_vad_en = false;
4693 schedule_delayed_work(&rt5677->dsp_work, 0);
4694 flush_delayed_work(&rt5677->dsp_work);
4697 regmap_update_bits(rt5677->regmap, RT5677_DIG_MISC, 0x1, 0x0);
4698 regmap_write(rt5677->regmap, RT5677_PWR_DIG1, 0x0000);
4699 regmap_write(rt5677->regmap, RT5677_PWR_ANLG1,
4702 regmap_update_bits(rt5677->regmap, RT5677_PWR_ANLG2,
4704 regmap_update_bits(rt5677->regmap,
4707 if (rt5677->dsp_vad_en)
4724 return regmap_update_bits(rt5677->regmap, reg, m << shift, v << shift);
4754 ret = regmap_read(rt5677->regmap, RT5677_GPIO_ST, &value);
4772 * 0 - floating
4773 * 1 - pull down
4774 * 2 - pull up
4783 shift = 2 * (1 - offset);
4784 regmap_update_bits(rt5677->regmap,
4791 shift = 2 * (9 - offset);
4792 regmap_update_bits(rt5677->regmap,
4808 if ((rt5677->pdata.jd1_gpio == 1 && offset == RT5677_GPIO1) ||
4809 (rt5677->pdata.jd1_gpio == 2 &&
4811 (rt5677->pdata.jd1_gpio == 3 &&
4814 } else if ((rt5677->pdata.jd2_gpio == 1 && offset == RT5677_GPIO4) ||
4815 (rt5677->pdata.jd2_gpio == 2 &&
4817 (rt5677->pdata.jd2_gpio == 3 &&
4820 } else if ((rt5677->pdata.jd3_gpio == 1 &&
4822 (rt5677->pdata.jd3_gpio == 2 &&
4824 (rt5677->pdata.jd3_gpio == 3 &&
4828 return -ENXIO;
4831 return irq_create_mapping(rt5677->domain, irq);
4850 rt5677->gpio_chip = rt5677_template_chip;
4851 rt5677->gpio_chip.ngpio = RT5677_GPIO_NUM;
4852 rt5677->gpio_chip.parent = &i2c->dev;
4853 rt5677->gpio_chip.base = -1;
4855 ret = gpiochip_add_data(&rt5677->gpio_chip, rt5677);
4857 dev_err(&i2c->dev, "Failed to add GPIOs: %d\n", ret);
4864 gpiochip_remove(&rt5677->gpio_chip);
4887 rt5677->component = component;
4889 if (rt5677->pdata.dmic2_clk_pin == RT5677_DMIC_CLK2) {
4901 regmap_update_bits(rt5677->regmap, RT5677_DIG_MISC,
4903 regmap_write(rt5677->regmap, RT5677_PWR_DSP2,
4907 rt5677_gpio_config(rt5677, i, rt5677->pdata.gpio_config[i]);
4909 mutex_init(&rt5677->dsp_cmd_lock);
4910 mutex_init(&rt5677->dsp_pri_lock);
4919 cancel_delayed_work_sync(&rt5677->dsp_work);
4921 regmap_write(rt5677->regmap, RT5677_RESET, 0x10ec);
4922 gpiod_set_value_cansleep(rt5677->pow_ldo2, 0);
4923 gpiod_set_value_cansleep(rt5677->reset_pin, 1);
4931 if (rt5677->irq) {
4932 cancel_delayed_work_sync(&rt5677->resume_irq_check);
4933 disable_irq(rt5677->irq);
4936 if (!rt5677->dsp_vad_en) {
4937 regcache_cache_only(rt5677->regmap, true);
4938 regcache_mark_dirty(rt5677->regmap);
4940 gpiod_set_value_cansleep(rt5677->pow_ldo2, 0);
4941 gpiod_set_value_cansleep(rt5677->reset_pin, 1);
4951 if (!rt5677->dsp_vad_en) {
4952 rt5677->pll_src = 0;
4953 rt5677->pll_in = 0;
4954 rt5677->pll_out = 0;
4955 gpiod_set_value_cansleep(rt5677->pow_ldo2, 1);
4956 gpiod_set_value_cansleep(rt5677->reset_pin, 0);
4957 if (rt5677->pow_ldo2 || rt5677->reset_pin)
4960 regcache_cache_only(rt5677->regmap, false);
4961 regcache_sync(rt5677->regmap);
4964 if (rt5677->irq) {
4965 enable_irq(rt5677->irq);
4966 schedule_delayed_work(&rt5677->resume_irq_check, 0);
4981 if (rt5677->is_dsp_mode) {
4983 mutex_lock(&rt5677->dsp_pri_lock);
4987 mutex_unlock(&rt5677->dsp_pri_lock);
4992 regmap_read(rt5677->regmap_physical, reg, val);
5003 if (rt5677->is_dsp_mode) {
5005 mutex_lock(&rt5677->dsp_pri_lock);
5010 mutex_unlock(&rt5677->dsp_pri_lock);
5015 regmap_write(rt5677->regmap_physical, reg, val);
5040 .name = "rt5677-aif1",
5059 .name = "rt5677-aif2",
5078 .name = "rt5677-aif3",
5097 .name = "rt5677-aif4",
5116 .name = "rt5677-slimbus",
5135 .name = "rt5677-dspbuffer",
5216 rt5677->pdata.in1_diff =
5218 device_property_read_bool(dev, "realtek,in1-differential");
5220 rt5677->pdata.in2_diff =
5222 device_property_read_bool(dev, "realtek,in2-differential");
5224 rt5677->pdata.lout1_diff =
5226 device_property_read_bool(dev, "realtek,lout1-differential");
5228 rt5677->pdata.lout2_diff =
5230 device_property_read_bool(dev, "realtek,lout2-differential");
5232 rt5677->pdata.lout3_diff =
5234 device_property_read_bool(dev, "realtek,lout3-differential");
5236 device_property_read_u8_array(dev, "realtek,gpio-config",
5237 rt5677->pdata.gpio_config,
5242 rt5677->pdata.dmic2_clk_pin = val;
5245 !device_property_read_u32(dev, "realtek,jd1-gpio", &val))
5246 rt5677->pdata.jd1_gpio = val;
5249 !device_property_read_u32(dev, "realtek,jd2-gpio", &val))
5250 rt5677->pdata.jd2_gpio = val;
5253 !device_property_read_u32(dev, "realtek,jd3-gpio", &val))
5254 rt5677->pdata.jd3_gpio = val;
5285 if (!rt5677->is_dsp_mode)
5288 if (regmap_read(rt5677->regmap, RT5677_GPIO_CTRL1, ®_gpio))
5295 /* Set GPIO1 pin back to be IRQ output for jack detect */
5296 regmap_update_bits(rt5677->regmap, RT5677_GPIO_CTRL1,
5309 mutex_lock(&rt5677->irq_lock);
5327 ret = regmap_read(rt5677->regmap, RT5677_IRQ_CTRL1, ®_irq);
5329 dev_err(rt5677->dev, "failed reading IRQ status: %d\n",
5338 virq = irq_find_mapping(rt5677->domain, i);
5357 ret = regmap_write(rt5677->regmap, RT5677_IRQ_CTRL1, reg_irq);
5359 dev_err(rt5677->dev, "failed updating IRQ status: %d\n",
5366 mutex_unlock(&rt5677->irq_lock);
5380 * at resume. If the headset is plugged/unplugged when the device is
5386 /* Call all enabled jack detect irq handlers again. This is needed in
5389 * scheduled by soc-jack may run and read wrong jack gpio values, since
5392 * Without this explicit check, unplug the headset right after suspend
5393 * starts, then after resume the headset is still shown as plugged in.
5395 mutex_lock(&rt5677->irq_lock);
5397 if (rt5677->irq_en & rt5677_irq_descs[i].enable_mask) {
5398 virq = irq_find_mapping(rt5677->domain, i);
5403 mutex_unlock(&rt5677->irq_lock);
5410 mutex_lock(&rt5677->irq_lock);
5417 // Set the enable/disable bits for the jack detect IRQs.
5418 regmap_update_bits(rt5677->regmap, RT5677_IRQ_CTRL1,
5420 RT5677_EN_IRQ_GPIO_JD3, rt5677->irq_en);
5421 mutex_unlock(&rt5677->irq_lock);
5428 rt5677->irq_en |= rt5677_irq_descs[data->hwirq].enable_mask;
5435 rt5677->irq_en &= ~rt5677_irq_descs[data->hwirq].enable_mask;
5449 struct rt5677_priv *rt5677 = h->host_data;
5470 if (!rt5677->pdata.jd1_gpio &&
5471 !rt5677->pdata.jd2_gpio &&
5472 !rt5677->pdata.jd3_gpio)
5475 if (!i2c->irq) {
5476 dev_err(&i2c->dev, "No interrupt specified\n");
5477 return -EINVAL;
5480 mutex_init(&rt5677->irq_lock);
5481 INIT_DELAYED_WORK(&rt5677->resume_irq_check, rt5677_resume_irq_check);
5488 regmap_update_bits(rt5677->regmap, RT5677_DIG_MISC,
5492 regmap_update_bits(rt5677->regmap, RT5677_GEN_CTRL1, 0xff, 0xff);
5495 if (rt5677->pdata.jd1_gpio) {
5497 jd_val |= rt5677->pdata.jd1_gpio << RT5677_SEL_GPIO_JD1_SFT;
5499 if (rt5677->pdata.jd2_gpio) {
5501 jd_val |= rt5677->pdata.jd2_gpio << RT5677_SEL_GPIO_JD2_SFT;
5503 if (rt5677->pdata.jd3_gpio) {
5505 jd_val |= rt5677->pdata.jd3_gpio << RT5677_SEL_GPIO_JD3_SFT;
5507 regmap_update_bits(rt5677->regmap, RT5677_JD_CTRL1, jd_mask, jd_val);
5510 regmap_update_bits(rt5677->regmap, RT5677_GPIO_CTRL1,
5514 rt5677->domain = irq_domain_create_linear(dev_fwnode(&i2c->dev),
5516 if (!rt5677->domain) {
5517 dev_err(&i2c->dev, "Failed to create IRQ domain\n");
5518 return -ENOMEM;
5521 ret = devm_request_threaded_irq(&i2c->dev, i2c->irq, NULL, rt5677_irq,
5525 dev_err(&i2c->dev, "Failed to request IRQ: %d\n", ret);
5527 rt5677->irq = i2c->irq;
5534 struct device *dev = &i2c->dev;
5539 rt5677 = devm_kzalloc(&i2c->dev, sizeof(struct rt5677_priv),
5542 return -ENOMEM;
5544 rt5677->dev = &i2c->dev;
5545 rt5677->set_dsp_vad = rt5677_set_dsp_vad;
5546 INIT_DELAYED_WORK(&rt5677->dsp_work, rt5677_dsp_work);
5549 rt5677->type = (enum rt5677_type)(uintptr_t)device_get_match_data(dev);
5550 if (rt5677->type == 0)
5551 return -EINVAL;
5553 rt5677_read_device_properties(rt5677, &i2c->dev);
5555 /* pow-ldo2 and reset are optional. The codec pins may be statically
5556 * connected on the board without gpios. If the gpio device property
5559 rt5677->pow_ldo2 = devm_gpiod_get_optional(&i2c->dev,
5560 "realtek,pow-ldo2", GPIOD_OUT_HIGH);
5561 if (IS_ERR(rt5677->pow_ldo2)) {
5562 ret = PTR_ERR(rt5677->pow_ldo2);
5563 dev_err(&i2c->dev, "Failed to request POW_LDO2: %d\n", ret);
5566 rt5677->reset_pin = devm_gpiod_get_optional(&i2c->dev,
5568 if (IS_ERR(rt5677->reset_pin)) {
5569 ret = PTR_ERR(rt5677->reset_pin);
5570 dev_err(&i2c->dev, "Failed to request RESET: %d\n", ret);
5574 if (rt5677->pow_ldo2 || rt5677->reset_pin) {
5582 rt5677->regmap_physical = devm_regmap_init_i2c(i2c,
5584 if (IS_ERR(rt5677->regmap_physical)) {
5585 ret = PTR_ERR(rt5677->regmap_physical);
5586 dev_err(&i2c->dev, "Failed to allocate register map: %d\n",
5591 rt5677->regmap = devm_regmap_init(&i2c->dev, NULL, i2c, &rt5677_regmap);
5592 if (IS_ERR(rt5677->regmap)) {
5593 ret = PTR_ERR(rt5677->regmap);
5594 dev_err(&i2c->dev, "Failed to allocate register map: %d\n",
5599 regmap_read(rt5677->regmap, RT5677_VENDOR_ID2, &val);
5601 dev_err(&i2c->dev,
5603 return -ENODEV;
5606 regmap_write(rt5677->regmap, RT5677_RESET, 0x10ec);
5608 ret = regmap_register_patch(rt5677->regmap, init_list,
5611 dev_warn(&i2c->dev, "Failed to apply regmap patch: %d\n", ret);
5613 if (rt5677->pdata.in1_diff)
5614 regmap_update_bits(rt5677->regmap, RT5677_IN1,
5617 if (rt5677->pdata.in2_diff)
5618 regmap_update_bits(rt5677->regmap, RT5677_IN1,
5621 if (rt5677->pdata.lout1_diff)
5622 regmap_update_bits(rt5677->regmap, RT5677_LOUT1,
5625 if (rt5677->pdata.lout2_diff)
5626 regmap_update_bits(rt5677->regmap, RT5677_LOUT1,
5629 if (rt5677->pdata.lout3_diff)
5630 regmap_update_bits(rt5677->regmap, RT5677_LOUT1,
5633 if (rt5677->pdata.dmic2_clk_pin == RT5677_DMIC_CLK2) {
5634 regmap_update_bits(rt5677->regmap, RT5677_GEN_CTRL2,
5642 if (rt5677->pdata.micbias1_vdd_3v3)
5643 regmap_update_bits(rt5677->regmap, RT5677_MICBIAS,
5650 dev_err(&i2c->dev, "Failed to initialize irq: %d\n", ret);
5652 return devm_snd_soc_register_component(&i2c->dev,