Lines Matching +full:asrc +full:- +full:clk +full:- +full:map

1 // SPDX-License-Identifier: GPL-2.0-only
3 * rt5677.c -- RT5677 ALSA SoC audio codec driver
29 #include <sound/soc-dapm.h>
35 #include "rt5677-spi.h"
552 * rt5677_dsp_mode_i2c_write_addr - Write value to address on DSP mode.
563 struct snd_soc_component *component = rt5677->component;
566 mutex_lock(&rt5677->dsp_cmd_lock);
568 ret = regmap_write(rt5677->regmap_physical, RT5677_DSP_I2C_ADDR_MSB,
571 dev_err(component->dev, "Failed to set addr msb value: %d\n", ret);
575 ret = regmap_write(rt5677->regmap_physical, RT5677_DSP_I2C_ADDR_LSB,
578 dev_err(component->dev, "Failed to set addr lsb value: %d\n", ret);
582 ret = regmap_write(rt5677->regmap_physical, RT5677_DSP_I2C_DATA_MSB,
585 dev_err(component->dev, "Failed to set data msb value: %d\n", ret);
589 ret = regmap_write(rt5677->regmap_physical, RT5677_DSP_I2C_DATA_LSB,
592 dev_err(component->dev, "Failed to set data lsb value: %d\n", ret);
596 ret = regmap_write(rt5677->regmap_physical, RT5677_DSP_I2C_OP_CODE,
599 dev_err(component->dev, "Failed to set op code value: %d\n", ret);
604 mutex_unlock(&rt5677->dsp_cmd_lock);
610 * rt5677_dsp_mode_i2c_read_addr - Read value from address on DSP mode.
621 struct snd_soc_component *component = rt5677->component;
625 mutex_lock(&rt5677->dsp_cmd_lock);
627 ret = regmap_write(rt5677->regmap_physical, RT5677_DSP_I2C_ADDR_MSB,
630 dev_err(component->dev, "Failed to set addr msb value: %d\n", ret);
634 ret = regmap_write(rt5677->regmap_physical, RT5677_DSP_I2C_ADDR_LSB,
637 dev_err(component->dev, "Failed to set addr lsb value: %d\n", ret);
641 ret = regmap_write(rt5677->regmap_physical, RT5677_DSP_I2C_OP_CODE,
644 dev_err(component->dev, "Failed to set op code value: %d\n", ret);
648 regmap_read(rt5677->regmap_physical, RT5677_DSP_I2C_DATA_MSB, &msb);
649 regmap_read(rt5677->regmap_physical, RT5677_DSP_I2C_DATA_LSB, &lsb);
653 mutex_unlock(&rt5677->dsp_cmd_lock);
659 * rt5677_dsp_mode_i2c_write - Write register on DSP mode.
675 * rt5677_dsp_mode_i2c_read - Read register on DSP mode.
697 regmap_update_bits(rt5677->regmap, RT5677_PWR_DSP1,
699 rt5677->is_dsp_mode = true;
701 regmap_update_bits(rt5677->regmap, RT5677_PWR_DSP1,
703 rt5677->is_dsp_mode = false;
710 snd_soc_component_get_dapm(rt5677->component);
717 * DMIC CLK = 256 * fs / 12
719 regmap_update_bits(rt5677->regmap, RT5677_DMIC_CTRL1,
723 regmap_update_bits(rt5677->regmap, RT5677_CLK_TREE_CTRL1,
727 regmap_write(rt5677->regmap, RT5677_GLB_CLK2,
731 regmap_write(rt5677->regmap, RT5677_VAD_CTRL2, 0x013f);
733 regmap_write(rt5677->regmap, RT5677_VAD_CTRL3, 0x0ae5);
738 regmap_update_bits(rt5677->regmap, RT5677_VAD_CTRL4,
741 /* Minimum frame level within a pre-determined duration = 32 frames
744 * SAD Buffer Over-Writing = enable
751 regmap_write(rt5677->regmap, RT5677_VAD_CTRL1,
757 /* VAD/SAD is not routed to the IRQ output (i.e. MX-BE[14] = 0), but it
764 regmap_update_bits(rt5677->regmap, RT5677_PR_BASE + RT5677_BIAS_CUR4,
770 regmap_update_bits(rt5677->regmap, RT5677_PWR_ANLG1,
777 regmap_update_bits(rt5677->regmap, RT5677_PWR_ANLG2,
787 regmap_write(rt5677->regmap, RT5677_PWR_DSP2,
800 regmap_write(rt5677->regmap, RT5677_PWR_DSP1,
814 struct snd_soc_component *component = rt5677->component;
821 return -ENOMEM;
827 if (strncmp(elf_hdr->e_ident, ELFMAG, sizeof(ELFMAG) - 1))
828 dev_err(component->dev, "Wrong ELF header prefix\n");
829 if (elf_hdr->e_ehsize != sizeof(Elf32_Ehdr))
830 dev_err(component->dev, "Wrong ELF header size\n");
831 if (elf_hdr->e_machine != EM_XTENSA)
832 dev_err(component->dev, "Wrong DSP code file\n");
834 if (len < elf_hdr->e_phoff)
835 return -ENOMEM;
836 pr_hdr = (Elf32_Phdr *)(buf + elf_hdr->e_phoff);
837 for (i = 0; i < elf_hdr->e_phnum; i++) {
839 if (pr_hdr->p_paddr && pr_hdr->p_filesz) {
840 dev_info(component->dev, "Load 0x%x bytes to 0x%x\n",
841 pr_hdr->p_filesz, pr_hdr->p_paddr);
843 ret = rt5677_spi_write(pr_hdr->p_paddr,
844 buf + pr_hdr->p_offset,
845 pr_hdr->p_filesz);
847 dev_err(component->dev, "Load firmware failed %d\n",
858 struct device *dev = rt5677->component->dev;
867 dev_info(dev, "Requested rt5677_elf_vad (%zu)\n", fwp->size);
869 ret = rt5677_parse_and_load_dsp(rt5677, fwp->data, fwp->size);
877 rt5677->dsp_vad_en_request = on;
878 rt5677->dsp_vad_en = on;
881 return -ENXIO;
883 schedule_delayed_work(&rt5677->dsp_work, 0);
892 bool enable = rt5677->dsp_vad_en;
896 dev_info(rt5677->component->dev, "DSP VAD: enable=%d, activity=%d\n",
917 regmap_read(rt5677->regmap, RT5677_PWR_DSP_ST, &val);
923 dev_err(rt5677->component->dev, "DSP Boot Timed Out!");
938 regmap_update_bits(rt5677->regmap, RT5677_PWR_DSP1,
944 mutex_lock(&rt5677->irq_lock);
946 regmap_update_bits(rt5677->regmap, RT5677_PWR_DSP1,
952 regmap_write(rt5677->regmap, RT5677_VAD_CTRL1, 0x2184);
955 regmap_update_bits(rt5677->regmap, RT5677_GPIO_CTRL1,
958 mutex_unlock(&rt5677->irq_lock);
962 static const DECLARE_TLV_DB_SCALE(dac_vol_tlv, -6525, 75, 0);
963 static const DECLARE_TLV_DB_SCALE(adc_vol_tlv, -1725, 75, 0);
965 static const DECLARE_TLV_DB_SCALE(st_vol_tlv, -4650, 150, 0);
984 ucontrol->value.integer.value[0] = rt5677->dsp_vad_en_request;
994 rt5677_set_dsp_vad(component, !!ucontrol->value.integer.value[0]);
1076 * set_dmic_clk - Set parameter of dmic.
1088 struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm);
1092 rate = rt5677->sysclk / rl6231_get_pre_div(rt5677->regmap,
1096 dev_err(component->dev, "Failed to set DMIC clock\n");
1098 regmap_update_bits(rt5677->regmap, RT5677_DMIC_CTRL1,
1106 struct snd_soc_component *component = snd_soc_dapm_to_component(source->dapm);
1110 regmap_read(rt5677->regmap, RT5677_GLB_CLK1, &val);
1121 struct snd_soc_component *component = snd_soc_dapm_to_component(source->dapm);
1125 if (source->reg == RT5677_ASRC_1) {
1126 switch (source->shift) {
1147 switch (source->shift) {
1189 regmap_read(rt5677->regmap, reg, &val);
1204 struct snd_soc_component *component = snd_soc_dapm_to_component(source->dapm);
1207 if (rt5677->sysclk > rt5677->lrck[RT5677_AIF1] * 384)
1214 * rt5677_sel_asrc_clk_src - select ASRC clock source for a set of filters
1219 * The ASRC function is for asynchronous MCLK and LRCK. Also, since RT5677 can
1220 * only support standard 32fs or 64fs i2s format, ASRC should be enabled to
1222 * ASRC function will track i2s clock and generate a corresponding system clock
1224 * set of filters specified by the mask. And the codec driver will turn on ASRC
1225 * for these filters if ASRC is selected as their clock source.
1255 return -EINVAL;
1258 /* ASRC 3 */
1278 regmap_update_bits(rt5677->regmap, RT5677_ASRC_3, asrc3_mask,
1281 /* ASRC 4 */
1307 regmap_update_bits(rt5677->regmap, RT5677_ASRC_4, asrc4_mask,
1310 /* ASRC 5 */
1336 regmap_update_bits(rt5677->regmap, RT5677_ASRC_5, asrc5_mask,
1339 /* ASRC 6 */
1353 regmap_update_bits(rt5677->regmap, RT5677_ASRC_6, asrc6_mask,
1356 /* ASRC 7 */
1370 regmap_update_bits(rt5677->regmap, RT5677_ASRC_7, asrc7_mask,
1373 /* ASRC 8 */
1377 | ((clk_src - 1) << RT5677_I2S1_CLK_SEL_SFT);
1383 | ((clk_src - 1) << RT5677_I2S2_CLK_SEL_SFT);
1389 | ((clk_src - 1) << RT5677_I2S3_CLK_SEL_SFT);
1395 | ((clk_src - 1) << RT5677_I2S4_CLK_SEL_SFT);
1399 regmap_update_bits(rt5677->regmap, RT5677_ASRC_8, asrc8_mask,
1409 struct snd_soc_component *component = snd_soc_dapm_to_component(source->dapm);
1413 switch (source->shift) {
1415 regmap_read(rt5677->regmap, RT5677_ASRC_5, &asrc_setting);
1421 regmap_read(rt5677->regmap, RT5677_ASRC_5, &asrc_setting);
1427 regmap_read(rt5677->regmap, RT5677_ASRC_5, &asrc_setting);
1433 regmap_read(rt5677->regmap, RT5677_ASRC_5, &asrc_setting);
1439 regmap_read(rt5677->regmap, RT5677_ASRC_6, &asrc_setting);
1445 regmap_read(rt5677->regmap, RT5677_ASRC_6, &asrc_setting);
1738 /* DAC1 L/R Source */ /* MX-29 [10:8] */
1751 /* ADDA1 L/R Source */ /* MX-29 [1:0] */
1764 /*DAC2 L/R Source*/ /* MX-1B [6:4] [2:0] */
1789 /*DAC3 L/R Source*/ /* MX-16 [6:4] [2:0] */
1814 /*DAC4 L/R Source*/ /* MX-16 [14:12] [10:8] */
1839 /* In/OutBound Source Pass SRC */ /* MX-A5 [3] [4] [0] [1] [2] */
1879 /* Stereo ADC Source 2 */ /* MX-27 MX26 MX25 [11:10] */
1905 /* DMIC Source */ /* MX-28 [9:8][1:0] MX-27 MX-26 MX-25 MX-24 [9:8] */
1952 /* Stereo2 ADC Source */ /* MX-26 [0] */
1964 /* Stereo1 ADC Source 1 */ /* MX-27 MX26 MX25 [13:12] */
1990 /* Mono ADC Left Source 2 */ /* MX-28 [11:10] */
2002 /* Mono ADC Left Source 1 */ /* MX-28 [13:12] */
2014 /* Mono ADC Right Source 2 */ /* MX-28 [3:2] */
2026 /* Mono ADC Right Source 1 */ /* MX-28 [5:4] */
2038 /* Stereo4 ADC Source 2 */ /* MX-24 [11:10] */
2051 /* Stereo4 ADC Source 1 */ /* MX-24 [13:12] */
2063 /* InBound0/1 Source */ /* MX-A3 [14:12] */
2076 /* InBound2/3 Source */ /* MX-A3 [10:8] */
2089 /* InBound4/5 Source */ /* MX-A3 [6:4] */
2102 /* InBound6 Source */ /* MX-A3 [2:0] */
2115 /* InBound7 Source */ /* MX-A4 [14:12] */
2128 /* InBound8 Source */ /* MX-A4 [10:8] */
2141 /* InBound9 Source */ /* MX-A4 [6:4] */
2154 /* VAD Source */ /* MX-9F [6:4] */
2167 /* Sidetone Source */ /* MX-13 [11:9] */
2179 /* DAC1/2 Source */ /* MX-15 [1:0] */
2191 /* DAC3 Source */ /* MX-15 [5:4] */
2203 /* PDM channel Source */ /* MX-31 [13:12][9:8][5:4][1:0] */
2236 /* TDM IF1/2 SLB ADC1 Data Selection */ /* MX-3C MX-41 [5:4] MX-08 [1:0] */
2262 /* TDM IF1/2 SLB ADC2 Data Selection */ /* MX-3C MX-41 [7:6] MX-08 [3:2] */
2288 /* TDM IF1/2 SLB ADC3 Data Selection */ /* MX-3C MX-41 [9:8] MX-08 [5:4] */
2314 /* TDM IF1/2 SLB ADC4 Data Selection */ /* MX-3C MX-41 [11:10] MX-08 [7:6] */
2340 /* Interface3/4 ADC Data Input */ /* MX-2F [3:0] MX-30 [7:4] */
2360 /* TDM IF1/2 ADC Data Selection */ /* MX-3B MX-40 [7:6][5:4][3:2][1:0] */
2421 /* TDM IF1 ADC Data Selection */ /* MX-3C [2:0] */
2434 /* TDM IF2 ADC Data Selection */ /* MX-41[2:0] */
2447 /* TDM IF1/2 DAC Data Selection */ /* MX-3E[14:12][10:8][6:4][2:0]
2448 MX-3F[14:12][10:8][6:4][2:0]
2449 MX-43[14:12][10:8][6:4][2:0]
2450 MX-44[14:12][10:8][6:4][2:0] */
2570 struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm);
2575 regmap_update_bits(rt5677->regmap, RT5677_PWR_ANLG2,
2580 regmap_update_bits(rt5677->regmap, RT5677_PWR_ANLG2,
2594 struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm);
2599 regmap_update_bits(rt5677->regmap, RT5677_PWR_ANLG2,
2604 regmap_update_bits(rt5677->regmap, RT5677_PWR_ANLG2,
2618 struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm);
2623 regmap_update_bits(rt5677->regmap, RT5677_PLL1_CTRL2, 0x2, 0x2);
2627 regmap_update_bits(rt5677->regmap, RT5677_PLL1_CTRL2, 0x2, 0x0);
2640 struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm);
2645 regmap_update_bits(rt5677->regmap, RT5677_PLL2_CTRL2, 0x2, 0x2);
2649 regmap_update_bits(rt5677->regmap, RT5677_PLL2_CTRL2, 0x2, 0x0);
2662 struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm);
2667 regmap_update_bits(rt5677->regmap, RT5677_PWR_ANLG2,
2674 regmap_update_bits(rt5677->regmap, RT5677_PWR_ANLG2,
2689 struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm);
2695 regmap_read(rt5677->regmap, RT5677_TDM1_CTRL2, &value);
2697 regmap_update_bits(rt5677->regmap, RT5677_TDM1_CTRL1,
2712 struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm);
2718 regmap_read(rt5677->regmap, RT5677_TDM2_CTRL2, &value);
2720 regmap_update_bits(rt5677->regmap, RT5677_TDM2_CTRL1,
2735 struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm);
2741 !rt5677->is_vref_slow) {
2743 regmap_update_bits(rt5677->regmap, RT5677_PWR_ANLG1,
2746 rt5677->is_vref_slow = true;
2780 /* ASRC */
2781 SND_SOC_DAPM_SUPPLY_S("I2S1 ASRC", 1, RT5677_ASRC_1, 0, 0, NULL, 0),
2782 SND_SOC_DAPM_SUPPLY_S("I2S2 ASRC", 1, RT5677_ASRC_1, 1, 0, NULL, 0),
2783 SND_SOC_DAPM_SUPPLY_S("I2S3 ASRC", 1, RT5677_ASRC_1, 2, 0, NULL, 0),
2784 SND_SOC_DAPM_SUPPLY_S("I2S4 ASRC", 1, RT5677_ASRC_1, 3, 0, NULL, 0),
2785 SND_SOC_DAPM_SUPPLY_S("DAC STO ASRC", 1, RT5677_ASRC_2, 14, 0,
2787 SND_SOC_DAPM_SUPPLY_S("DAC MONO2 L ASRC", 1, RT5677_ASRC_2, 13, 0, NULL,
2789 SND_SOC_DAPM_SUPPLY_S("DAC MONO2 R ASRC", 1, RT5677_ASRC_2, 12, 0, NULL,
2791 SND_SOC_DAPM_SUPPLY_S("DAC MONO3 L ASRC", 1, RT5677_ASRC_1, 15, 0, NULL,
2793 SND_SOC_DAPM_SUPPLY_S("DAC MONO3 R ASRC", 1, RT5677_ASRC_1, 14, 0, NULL,
2795 SND_SOC_DAPM_SUPPLY_S("DAC MONO4 L ASRC", 1, RT5677_ASRC_1, 13, 0, NULL,
2797 SND_SOC_DAPM_SUPPLY_S("DAC MONO4 R ASRC", 1, RT5677_ASRC_1, 12, 0, NULL,
2799 SND_SOC_DAPM_SUPPLY_S("DMIC STO1 ASRC", 1, RT5677_ASRC_2, 11, 0, NULL,
2801 SND_SOC_DAPM_SUPPLY_S("DMIC STO2 ASRC", 1, RT5677_ASRC_2, 10, 0, NULL,
2803 SND_SOC_DAPM_SUPPLY_S("DMIC STO3 ASRC", 1, RT5677_ASRC_2, 9, 0, NULL,
2805 SND_SOC_DAPM_SUPPLY_S("DMIC STO4 ASRC", 1, RT5677_ASRC_2, 8, 0, NULL,
2807 SND_SOC_DAPM_SUPPLY_S("DMIC MONO L ASRC", 1, RT5677_ASRC_2, 7, 0, NULL,
2809 SND_SOC_DAPM_SUPPLY_S("DMIC MONO R ASRC", 1, RT5677_ASRC_2, 6, 0, NULL,
2811 SND_SOC_DAPM_SUPPLY_S("ADC STO1 ASRC", 1, RT5677_ASRC_2, 5, 0, NULL, 0),
2812 SND_SOC_DAPM_SUPPLY_S("ADC STO2 ASRC", 1, RT5677_ASRC_2, 4, 0, NULL, 0),
2813 SND_SOC_DAPM_SUPPLY_S("ADC STO3 ASRC", 1, RT5677_ASRC_2, 3, 0, NULL, 0),
2814 SND_SOC_DAPM_SUPPLY_S("ADC STO4 ASRC", 1, RT5677_ASRC_2, 2, 0, NULL, 0),
2815 SND_SOC_DAPM_SUPPLY_S("ADC MONO L ASRC", 1, RT5677_ASRC_2, 1, 0, NULL,
2817 SND_SOC_DAPM_SUPPLY_S("ADC MONO R ASRC", 1, RT5677_ASRC_2, 0, 0, NULL,
2857 SND_SOC_DAPM_SUPPLY("DMIC CLK", SND_SOC_NOPM, 0, 0,
3342 { "Stereo1 DMIC Mux", NULL, "DMIC STO1 ASRC", rt5677_dmic_use_asrc },
3343 { "Stereo2 DMIC Mux", NULL, "DMIC STO2 ASRC", rt5677_dmic_use_asrc },
3344 { "Stereo3 DMIC Mux", NULL, "DMIC STO3 ASRC", rt5677_dmic_use_asrc },
3345 { "Stereo4 DMIC Mux", NULL, "DMIC STO4 ASRC", rt5677_dmic_use_asrc },
3346 { "Mono DMIC L Mux", NULL, "DMIC MONO L ASRC", rt5677_dmic_use_asrc },
3347 { "Mono DMIC R Mux", NULL, "DMIC MONO R ASRC", rt5677_dmic_use_asrc },
3348 { "I2S1", NULL, "I2S1 ASRC", can_use_asrc},
3349 { "I2S2", NULL, "I2S2 ASRC", can_use_asrc},
3350 { "I2S3", NULL, "I2S3 ASRC", can_use_asrc},
3351 { "I2S4", NULL, "I2S4 ASRC", can_use_asrc},
3353 { "dac stereo1 filter", NULL, "DAC STO ASRC", is_using_asrc },
3354 { "dac mono2 left filter", NULL, "DAC MONO2 L ASRC", is_using_asrc },
3355 { "dac mono2 right filter", NULL, "DAC MONO2 R ASRC", is_using_asrc },
3356 { "dac mono3 left filter", NULL, "DAC MONO3 L ASRC", is_using_asrc },
3357 { "dac mono3 right filter", NULL, "DAC MONO3 R ASRC", is_using_asrc },
3358 { "dac mono4 left filter", NULL, "DAC MONO4 L ASRC", is_using_asrc },
3359 { "dac mono4 right filter", NULL, "DAC MONO4 R ASRC", is_using_asrc },
3360 { "adc stereo1 filter", NULL, "ADC STO1 ASRC", is_using_asrc },
3361 { "adc stereo2 filter", NULL, "ADC STO2 ASRC", is_using_asrc },
3362 { "adc stereo3 filter", NULL, "ADC STO3 ASRC", is_using_asrc },
3363 { "adc stereo4 filter", NULL, "ADC STO4 ASRC", is_using_asrc },
3364 { "adc mono left filter", NULL, "ADC MONO L ASRC", is_using_asrc },
3365 { "adc mono right filter", NULL, "ADC MONO R ASRC", is_using_asrc },
3376 { "DMIC L1", NULL, "DMIC CLK" },
3377 { "DMIC R1", NULL, "DMIC CLK" },
3378 { "DMIC L2", NULL, "DMIC CLK" },
3379 { "DMIC R2", NULL, "DMIC CLK" },
3380 { "DMIC L3", NULL, "DMIC CLK" },
3381 { "DMIC R3", NULL, "DMIC CLK" },
3382 { "DMIC L4", NULL, "DMIC CLK" },
3383 { "DMIC R4", NULL, "DMIC CLK" },
3733 * there is an active path going from system playback -> "DAC1 FS" ->
3734 * IB01 Mux -> DSP Buffer -> hotword stream. This wrong path confuses
4290 struct snd_soc_component *component = dai->component;
4295 rt5677->lrck[dai->id] = params_rate(params);
4296 pre_div = rl6231_get_clk_info(rt5677->sysclk, rt5677->lrck[dai->id]);
4298 dev_err(component->dev, "Unsupported clock setting: sysclk=%dHz lrck=%dHz\n",
4299 rt5677->sysclk, rt5677->lrck[dai->id]);
4300 return -EINVAL;
4304 dev_err(component->dev, "Unsupported frame size: %d\n", frame_size);
4305 return -EINVAL;
4308 rt5677->bclk[dai->id] = rt5677->lrck[dai->id] * (32 << bclk_ms);
4310 dev_dbg(dai->dev, "bclk is %dHz and lrck is %dHz\n",
4311 rt5677->bclk[dai->id], rt5677->lrck[dai->id]);
4312 dev_dbg(dai->dev, "bclk_ms is %d and pre_div is %d for iis %d\n",
4313 bclk_ms, pre_div, dai->id);
4328 return -EINVAL;
4331 switch (dai->id) {
4335 regmap_update_bits(rt5677->regmap, RT5677_I2S1_SDP,
4337 regmap_update_bits(rt5677->regmap, RT5677_CLK_TREE_CTRL1,
4343 regmap_update_bits(rt5677->regmap, RT5677_I2S2_SDP,
4345 regmap_update_bits(rt5677->regmap, RT5677_CLK_TREE_CTRL1,
4352 regmap_update_bits(rt5677->regmap, RT5677_I2S3_SDP,
4354 regmap_update_bits(rt5677->regmap, RT5677_CLK_TREE_CTRL1,
4361 regmap_update_bits(rt5677->regmap, RT5677_I2S4_SDP,
4363 regmap_update_bits(rt5677->regmap, RT5677_CLK_TREE_CTRL1,
4375 struct snd_soc_component *component = dai->component;
4381 rt5677->master[dai->id] = 1;
4385 rt5677->master[dai->id] = 0;
4388 return -EINVAL;
4398 return -EINVAL;
4414 return -EINVAL;
4417 switch (dai->id) {
4419 regmap_update_bits(rt5677->regmap, RT5677_I2S1_SDP,
4424 regmap_update_bits(rt5677->regmap, RT5677_I2S2_SDP,
4429 regmap_update_bits(rt5677->regmap, RT5677_I2S3_SDP,
4434 regmap_update_bits(rt5677->regmap, RT5677_I2S4_SDP,
4449 struct snd_soc_component *component = dai->component;
4453 if (freq == rt5677->sysclk && clk_id == rt5677->sysclk_src)
4467 dev_err(component->dev, "Invalid clock id (%d)\n", clk_id);
4468 return -EINVAL;
4470 regmap_update_bits(rt5677->regmap, RT5677_GLB_CLK1,
4472 rt5677->sysclk = freq;
4473 rt5677->sysclk_src = clk_id;
4475 dev_dbg(dai->dev, "Sysclk is %dHz and clock id is %d\n", freq, clk_id);
4481 * rt5677_pll_calc - Calcualte PLL M/N/K code.
4494 return -EINVAL;
4502 struct snd_soc_component *component = dai->component;
4507 if (source == rt5677->pll_src && freq_in == rt5677->pll_in &&
4508 freq_out == rt5677->pll_out)
4512 dev_dbg(component->dev, "PLL disabled\n");
4514 rt5677->pll_in = 0;
4515 rt5677->pll_out = 0;
4516 regmap_update_bits(rt5677->regmap, RT5677_GLB_CLK1,
4523 regmap_update_bits(rt5677->regmap, RT5677_GLB_CLK1,
4530 switch (dai->id) {
4532 regmap_update_bits(rt5677->regmap, RT5677_GLB_CLK1,
4536 regmap_update_bits(rt5677->regmap, RT5677_GLB_CLK1,
4540 regmap_update_bits(rt5677->regmap, RT5677_GLB_CLK1,
4544 regmap_update_bits(rt5677->regmap, RT5677_GLB_CLK1,
4552 dev_err(component->dev, "Unknown PLL source %d\n", source);
4553 return -EINVAL;
4558 dev_err(component->dev, "Unsupported input clock %d\n", freq_in);
4562 dev_dbg(component->dev, "m_bypass=%d m=%d n=%d k=%d\n",
4566 regmap_write(rt5677->regmap, RT5677_PLL1_CTRL1,
4568 regmap_write(rt5677->regmap, RT5677_PLL1_CTRL2,
4572 rt5677->pll_in = freq_in;
4573 rt5677->pll_out = freq_out;
4574 rt5677->pll_src = source;
4582 struct snd_soc_component *component = dai->component;
4622 switch (dai->id) {
4624 regmap_update_bits(rt5677->regmap, RT5677_TDM1_CTRL1, 0x1f00,
4626 regmap_update_bits(rt5677->regmap, RT5677_DIG_MISC, 0x8000,
4630 regmap_update_bits(rt5677->regmap, RT5677_TDM2_CTRL1, 0x1f00,
4632 regmap_update_bits(rt5677->regmap, RT5677_DIG_MISC, 0x80,
4656 regmap_update_bits(rt5677->regmap, RT5677_PWR_ANLG1,
4660 regmap_update_bits(rt5677->regmap,
4663 regmap_update_bits(rt5677->regmap, RT5677_PWR_ANLG1,
4669 rt5677->is_vref_slow = false;
4670 regmap_update_bits(rt5677->regmap, RT5677_PWR_ANLG2,
4672 regmap_update_bits(rt5677->regmap, RT5677_DIG_MISC,
4679 rt5677->dsp_vad_en_request) {
4680 /* Re-enable the DSP if it was turned off at suspend */
4681 rt5677->dsp_vad_en = true;
4683 schedule_delayed_work(&rt5677->dsp_work,
4689 flush_delayed_work(&rt5677->dsp_work);
4690 if (rt5677->is_dsp_mode) {
4692 rt5677->dsp_vad_en = false;
4693 schedule_delayed_work(&rt5677->dsp_work, 0);
4694 flush_delayed_work(&rt5677->dsp_work);
4697 regmap_update_bits(rt5677->regmap, RT5677_DIG_MISC, 0x1, 0x0);
4698 regmap_write(rt5677->regmap, RT5677_PWR_DIG1, 0x0000);
4699 regmap_write(rt5677->regmap, RT5677_PWR_ANLG1,
4702 regmap_update_bits(rt5677->regmap, RT5677_PWR_ANLG2,
4704 regmap_update_bits(rt5677->regmap,
4707 if (rt5677->dsp_vad_en)
4724 return regmap_update_bits(rt5677->regmap, reg, m << shift, v << shift);
4753 ret = regmap_read(rt5677->regmap, RT5677_GPIO_ST, &value);
4771 * 0 - floating
4772 * 1 - pull down
4773 * 2 - pull up
4782 shift = 2 * (1 - offset);
4783 regmap_update_bits(rt5677->regmap,
4790 shift = 2 * (9 - offset);
4791 regmap_update_bits(rt5677->regmap,
4807 if ((rt5677->pdata.jd1_gpio == 1 && offset == RT5677_GPIO1) ||
4808 (rt5677->pdata.jd1_gpio == 2 &&
4810 (rt5677->pdata.jd1_gpio == 3 &&
4813 } else if ((rt5677->pdata.jd2_gpio == 1 && offset == RT5677_GPIO4) ||
4814 (rt5677->pdata.jd2_gpio == 2 &&
4816 (rt5677->pdata.jd2_gpio == 3 &&
4819 } else if ((rt5677->pdata.jd3_gpio == 1 &&
4821 (rt5677->pdata.jd3_gpio == 2 &&
4823 (rt5677->pdata.jd3_gpio == 3 &&
4827 return -ENXIO;
4830 return irq_create_mapping(rt5677->domain, irq);
4849 rt5677->gpio_chip = rt5677_template_chip;
4850 rt5677->gpio_chip.ngpio = RT5677_GPIO_NUM;
4851 rt5677->gpio_chip.parent = &i2c->dev;
4852 rt5677->gpio_chip.base = -1;
4854 ret = gpiochip_add_data(&rt5677->gpio_chip, rt5677);
4856 dev_err(&i2c->dev, "Failed to add GPIOs: %d\n", ret);
4863 gpiochip_remove(&rt5677->gpio_chip);
4886 rt5677->component = component;
4888 if (rt5677->pdata.dmic2_clk_pin == RT5677_DMIC_CLK2) {
4900 regmap_update_bits(rt5677->regmap, RT5677_DIG_MISC,
4902 regmap_write(rt5677->regmap, RT5677_PWR_DSP2,
4906 rt5677_gpio_config(rt5677, i, rt5677->pdata.gpio_config[i]);
4908 mutex_init(&rt5677->dsp_cmd_lock);
4909 mutex_init(&rt5677->dsp_pri_lock);
4918 cancel_delayed_work_sync(&rt5677->dsp_work);
4920 regmap_write(rt5677->regmap, RT5677_RESET, 0x10ec);
4921 gpiod_set_value_cansleep(rt5677->pow_ldo2, 0);
4922 gpiod_set_value_cansleep(rt5677->reset_pin, 1);
4930 if (rt5677->irq) {
4931 cancel_delayed_work_sync(&rt5677->resume_irq_check);
4932 disable_irq(rt5677->irq);
4935 if (!rt5677->dsp_vad_en) {
4936 regcache_cache_only(rt5677->regmap, true);
4937 regcache_mark_dirty(rt5677->regmap);
4939 gpiod_set_value_cansleep(rt5677->pow_ldo2, 0);
4940 gpiod_set_value_cansleep(rt5677->reset_pin, 1);
4950 if (!rt5677->dsp_vad_en) {
4951 rt5677->pll_src = 0;
4952 rt5677->pll_in = 0;
4953 rt5677->pll_out = 0;
4954 gpiod_set_value_cansleep(rt5677->pow_ldo2, 1);
4955 gpiod_set_value_cansleep(rt5677->reset_pin, 0);
4956 if (rt5677->pow_ldo2 || rt5677->reset_pin)
4959 regcache_cache_only(rt5677->regmap, false);
4960 regcache_sync(rt5677->regmap);
4963 if (rt5677->irq) {
4964 enable_irq(rt5677->irq);
4965 schedule_delayed_work(&rt5677->resume_irq_check, 0);
4980 if (rt5677->is_dsp_mode) {
4982 mutex_lock(&rt5677->dsp_pri_lock);
4986 mutex_unlock(&rt5677->dsp_pri_lock);
4991 regmap_read(rt5677->regmap_physical, reg, val);
5002 if (rt5677->is_dsp_mode) {
5004 mutex_lock(&rt5677->dsp_pri_lock);
5009 mutex_unlock(&rt5677->dsp_pri_lock);
5014 regmap_write(rt5677->regmap_physical, reg, val);
5039 .name = "rt5677-aif1",
5058 .name = "rt5677-aif2",
5077 .name = "rt5677-aif3",
5096 .name = "rt5677-aif4",
5115 .name = "rt5677-slimbus",
5134 .name = "rt5677-dspbuffer",
5215 rt5677->pdata.in1_diff =
5217 device_property_read_bool(dev, "realtek,in1-differential");
5219 rt5677->pdata.in2_diff =
5221 device_property_read_bool(dev, "realtek,in2-differential");
5223 rt5677->pdata.lout1_diff =
5225 device_property_read_bool(dev, "realtek,lout1-differential");
5227 rt5677->pdata.lout2_diff =
5229 device_property_read_bool(dev, "realtek,lout2-differential");
5231 rt5677->pdata.lout3_diff =
5233 device_property_read_bool(dev, "realtek,lout3-differential");
5235 device_property_read_u8_array(dev, "realtek,gpio-config",
5236 rt5677->pdata.gpio_config,
5241 rt5677->pdata.dmic2_clk_pin = val;
5244 !device_property_read_u32(dev, "realtek,jd1-gpio", &val))
5245 rt5677->pdata.jd1_gpio = val;
5248 !device_property_read_u32(dev, "realtek,jd2-gpio", &val))
5249 rt5677->pdata.jd2_gpio = val;
5252 !device_property_read_u32(dev, "realtek,jd3-gpio", &val))
5253 rt5677->pdata.jd3_gpio = val;
5284 if (!rt5677->is_dsp_mode)
5287 if (regmap_read(rt5677->regmap, RT5677_GPIO_CTRL1, &reg_gpio))
5295 regmap_update_bits(rt5677->regmap, RT5677_GPIO_CTRL1,
5308 mutex_lock(&rt5677->irq_lock);
5326 ret = regmap_read(rt5677->regmap, RT5677_IRQ_CTRL1, &reg_irq);
5328 dev_err(rt5677->dev, "failed reading IRQ status: %d\n",
5337 virq = irq_find_mapping(rt5677->domain, i);
5356 ret = regmap_write(rt5677->regmap, RT5677_IRQ_CTRL1, reg_irq);
5358 dev_err(rt5677->dev, "failed updating IRQ status: %d\n",
5365 mutex_unlock(&rt5677->irq_lock);
5388 * scheduled by soc-jack may run and read wrong jack gpio values, since
5394 mutex_lock(&rt5677->irq_lock);
5396 if (rt5677->irq_en & rt5677_irq_descs[i].enable_mask) {
5397 virq = irq_find_mapping(rt5677->domain, i);
5402 mutex_unlock(&rt5677->irq_lock);
5409 mutex_lock(&rt5677->irq_lock);
5417 regmap_update_bits(rt5677->regmap, RT5677_IRQ_CTRL1,
5419 RT5677_EN_IRQ_GPIO_JD3, rt5677->irq_en);
5420 mutex_unlock(&rt5677->irq_lock);
5427 rt5677->irq_en |= rt5677_irq_descs[data->hwirq].enable_mask;
5434 rt5677->irq_en &= ~rt5677_irq_descs[data->hwirq].enable_mask;
5448 struct rt5677_priv *rt5677 = h->host_data;
5459 .map = rt5677_irq_map,
5469 if (!rt5677->pdata.jd1_gpio &&
5470 !rt5677->pdata.jd2_gpio &&
5471 !rt5677->pdata.jd3_gpio)
5474 if (!i2c->irq) {
5475 dev_err(&i2c->dev, "No interrupt specified\n");
5476 return -EINVAL;
5479 mutex_init(&rt5677->irq_lock);
5480 INIT_DELAYED_WORK(&rt5677->resume_irq_check, rt5677_resume_irq_check);
5487 regmap_update_bits(rt5677->regmap, RT5677_DIG_MISC,
5491 regmap_update_bits(rt5677->regmap, RT5677_GEN_CTRL1, 0xff, 0xff);
5494 if (rt5677->pdata.jd1_gpio) {
5496 jd_val |= rt5677->pdata.jd1_gpio << RT5677_SEL_GPIO_JD1_SFT;
5498 if (rt5677->pdata.jd2_gpio) {
5500 jd_val |= rt5677->pdata.jd2_gpio << RT5677_SEL_GPIO_JD2_SFT;
5502 if (rt5677->pdata.jd3_gpio) {
5504 jd_val |= rt5677->pdata.jd3_gpio << RT5677_SEL_GPIO_JD3_SFT;
5506 regmap_update_bits(rt5677->regmap, RT5677_JD_CTRL1, jd_mask, jd_val);
5509 regmap_update_bits(rt5677->regmap, RT5677_GPIO_CTRL1,
5513 rt5677->domain = irq_domain_create_linear(dev_fwnode(&i2c->dev),
5515 if (!rt5677->domain) {
5516 dev_err(&i2c->dev, "Failed to create IRQ domain\n");
5517 return -ENOMEM;
5520 ret = devm_request_threaded_irq(&i2c->dev, i2c->irq, NULL, rt5677_irq,
5524 dev_err(&i2c->dev, "Failed to request IRQ: %d\n", ret);
5526 rt5677->irq = i2c->irq;
5533 struct device *dev = &i2c->dev;
5538 rt5677 = devm_kzalloc(&i2c->dev, sizeof(struct rt5677_priv),
5541 return -ENOMEM;
5543 rt5677->dev = &i2c->dev;
5544 rt5677->set_dsp_vad = rt5677_set_dsp_vad;
5545 INIT_DELAYED_WORK(&rt5677->dsp_work, rt5677_dsp_work);
5548 rt5677->type = (enum rt5677_type)(uintptr_t)device_get_match_data(dev);
5549 if (rt5677->type == 0)
5550 return -EINVAL;
5552 rt5677_read_device_properties(rt5677, &i2c->dev);
5554 /* pow-ldo2 and reset are optional. The codec pins may be statically
5558 rt5677->pow_ldo2 = devm_gpiod_get_optional(&i2c->dev,
5559 "realtek,pow-ldo2", GPIOD_OUT_HIGH);
5560 if (IS_ERR(rt5677->pow_ldo2)) {
5561 ret = PTR_ERR(rt5677->pow_ldo2);
5562 dev_err(&i2c->dev, "Failed to request POW_LDO2: %d\n", ret);
5565 rt5677->reset_pin = devm_gpiod_get_optional(&i2c->dev,
5567 if (IS_ERR(rt5677->reset_pin)) {
5568 ret = PTR_ERR(rt5677->reset_pin);
5569 dev_err(&i2c->dev, "Failed to request RESET: %d\n", ret);
5573 if (rt5677->pow_ldo2 || rt5677->reset_pin) {
5581 rt5677->regmap_physical = devm_regmap_init_i2c(i2c,
5583 if (IS_ERR(rt5677->regmap_physical)) {
5584 ret = PTR_ERR(rt5677->regmap_physical);
5585 dev_err(&i2c->dev, "Failed to allocate register map: %d\n",
5590 rt5677->regmap = devm_regmap_init(&i2c->dev, NULL, i2c, &rt5677_regmap);
5591 if (IS_ERR(rt5677->regmap)) {
5592 ret = PTR_ERR(rt5677->regmap);
5593 dev_err(&i2c->dev, "Failed to allocate register map: %d\n",
5598 regmap_read(rt5677->regmap, RT5677_VENDOR_ID2, &val);
5600 dev_err(&i2c->dev,
5602 return -ENODEV;
5605 regmap_write(rt5677->regmap, RT5677_RESET, 0x10ec);
5607 ret = regmap_register_patch(rt5677->regmap, init_list,
5610 dev_warn(&i2c->dev, "Failed to apply regmap patch: %d\n", ret);
5612 if (rt5677->pdata.in1_diff)
5613 regmap_update_bits(rt5677->regmap, RT5677_IN1,
5616 if (rt5677->pdata.in2_diff)
5617 regmap_update_bits(rt5677->regmap, RT5677_IN1,
5620 if (rt5677->pdata.lout1_diff)
5621 regmap_update_bits(rt5677->regmap, RT5677_LOUT1,
5624 if (rt5677->pdata.lout2_diff)
5625 regmap_update_bits(rt5677->regmap, RT5677_LOUT1,
5628 if (rt5677->pdata.lout3_diff)
5629 regmap_update_bits(rt5677->regmap, RT5677_LOUT1,
5632 if (rt5677->pdata.dmic2_clk_pin == RT5677_DMIC_CLK2) {
5633 regmap_update_bits(rt5677->regmap, RT5677_GEN_CTRL2,
5641 if (rt5677->pdata.micbias1_vdd_3v3)
5642 regmap_update_bits(rt5677->regmap, RT5677_MICBIAS,
5649 dev_err(&i2c->dev, "Failed to initialize irq: %d\n", ret);
5651 return devm_snd_soc_register_component(&i2c->dev,