Lines Matching +full:8 +full:- +full:15
1 /* SPDX-License-Identifier: GPL-2.0-only */
3 * rt5670.h -- RT5670 ALSA SoC audio driver
17 /* I/O - Output */
20 /* I/O - Input */
26 /* I/O - ADC/DAC/DMIC */
34 /* Mixer - D-D */
47 /* Mixer - PDM */
56 /* Mixer - ADC */
61 /* Mixer - DAC */
77 /* Format - ADC/DAC */
86 /* Format - TDM Control */
91 /* Function - Analog */
121 /* Function - Digital */
213 #define RT5670_L_MUTE (0x1 << 15)
214 #define RT5670_L_MUTE_SFT 15
217 #define RT5670_L_VOL_MASK (0x3f << 8)
218 #define RT5670_L_VOL_SFT 8
232 #define RT5670_CBJ_JD_MIC_EN (0x1 << 8)
243 #define RT5670_BST_MASK2 (0xf<<8)
244 #define RT5670_BST_SFT2 8
251 #define RT5670_INL_SEL_MASK (0x1 << 15)
252 #define RT5670_INL_SEL_SFT 15
253 #define RT5670_INL_SEL_IN4P (0x0 << 15)
254 #define RT5670_INL_SEL_MONOP (0x1 << 15)
255 #define RT5670_INL_VOL_MASK (0x1f << 8)
256 #define RT5670_INL_VOL_SFT 8
267 #define RT5670_M_ST_DACR2 (0x1 << 8)
268 #define RT5670_M_ST_DACR2_SFT 8
275 #define RT5670_DAC_L1_VOL_MASK (0xff << 8)
276 #define RT5670_DAC_L1_VOL_SFT 8
281 #define RT5670_DAC_L2_VOL_MASK (0xff << 8)
282 #define RT5670_DAC_L2_VOL_SFT 8
297 #define RT5670_ADC_L_VOL_MASK (0x7f << 8)
298 #define RT5670_ADC_L_VOL_SFT 8
303 #define RT5670_MONO_ADC_L_VOL_MASK (0x7f << 8)
304 #define RT5670_MONO_ADC_L_VOL_SFT 8
315 #define RT5670_STO2_ADC_L_BST_MASK (0x3 << 8)
316 #define RT5670_STO2_ADC_L_BST_SFT 8
323 #define RT5670_STO2_ADC_SRC_MASK (0x1 << 15)
324 #define RT5670_STO2_ADC_SRC_SFT 15
339 #define RT5670_DMIC_SRC_MASK (0x3 << 8)
340 #define RT5670_DMIC_SRC_SFT 8
361 #define RT5670_MONO_DMIC_L_SRC_MASK (0x3 << 8)
362 #define RT5670_MONO_DMIC_L_SRC_SFT 8
377 #define RT5670_M_ADCMIX_L (0x1 << 15)
378 #define RT5670_M_ADCMIX_L_SFT 15
387 #define RT5670_DAC1_L_SEL_MASK (0x3 << 8)
388 #define RT5670_DAC1_L_SEL_SFT 8
389 #define RT5670_DAC1_L_SEL_IF1 (0x0 << 8)
390 #define RT5670_DAC1_L_SEL_IF2 (0x1 << 8)
391 #define RT5670_DAC1_L_SEL_IF3 (0x2 << 8)
392 #define RT5670_DAC1_L_SEL_IF4 (0x3 << 8)
409 #define RT5670_DAC_R1_STO_L_VOL_MASK (0x1 << 8)
410 #define RT5670_DAC_R1_STO_L_VOL_SFT 8
451 #define RT5670_M_STO_L_DAC_L (0x1 << 15)
452 #define RT5670_M_STO_L_DAC_L_SFT 15
465 #define RT5670_DAC_R2_DAC_R_VOL_MASK (0x1 << 8)
466 #define RT5670_DAC_R2_DAC_R_VOL_SFT 8
497 #define RT5670_TXDP_L_VOL_MASK (0x7f << 8)
498 #define RT5670_TXDP_L_VOL_SFT 8
503 #define RT5670_IF1_ADC2_IN_SEL (0x1 << 15)
504 #define RT5670_IF1_ADC2_IN_SFT 15
509 #define RT5670_IF2_ADC_SEL_MASK (0x3 << 8)
510 #define RT5670_IF2_ADC_SEL_SFT 8
517 #define RT5670_PDM1_L_MASK (0x1 << 15)
518 #define RT5670_PDM1_L_SFT 15
531 #define RT5670_M_PDM2_R (0x1 << 8)
532 #define RT5670_M_PDM2_R_SFT 8
584 #define RT5670_M_DAC2_HM (0x1 << 15)
585 #define RT5670_M_DAC2_HM_SFT 15
602 #define RT5670_M_DAC_R2_MA (0x1 << 15)
603 #define RT5670_M_DAC_R2_MA_SFT 15
614 #define RT5670_M_DAC_L2_MM (0x1 << 8)
615 #define RT5670_M_DAC_L2_MM_SFT 8
680 #define RT5670_M_DAC_L1_LM (0x1 << 15)
681 #define RT5670_M_DAC_L1_LM_SFT 15
692 #define RT5670_PWR_I2S1 (0x1 << 15)
693 #define RT5670_PWR_I2S1_BIT 15
712 #define RT5670_PWR_ADC_S1F (0x1 << 15)
713 #define RT5670_PWR_ADC_S1F_BIT 15
726 #define RT5670_PWR_ADC_S2F (0x1 << 8)
727 #define RT5670_PWR_ADC_S2F_BIT 8
734 #define RT5670_PWR_VREF1 (0x1 << 15)
735 #define RT5670_PWR_VREF1_BIT 15
758 #define RT5670_PWR_BST1 (0x1 << 15)
759 #define RT5670_PWR_BST1_BIT 15
778 #define RT5670_PWR_OM_L (0x1 << 15)
779 #define RT5670_PWR_OM_L_BIT 15
794 #define RT5670_PWR_IN_R (0x1 << 8)
795 #define RT5670_PWR_IN_R_BIT 8
800 #define RT5670_I2S_MS_MASK (0x1 << 15)
801 #define RT5670_I2S_MS_SFT 15
802 #define RT5670_I2S_MS_M (0x0 << 15)
803 #define RT5670_I2S_MS_S (0x1 << 15)
811 #define RT5670_I2S_I_CP_MASK (0x3 << 8)
812 #define RT5670_I2S_I_CP_SFT 8
813 #define RT5670_I2S_I_CP_OFF (0x0 << 8)
814 #define RT5670_I2S_I_CP_U_LAW (0x1 << 8)
815 #define RT5670_I2S_I_CP_A_LAW (0x2 << 8)
840 #define RT5670_I2S_BCLK_MS1_MASK (0x1 << 15)
841 #define RT5670_I2S_BCLK_MS1_SFT 15
842 #define RT5670_I2S_BCLK_MS1_32 (0x0 << 15)
843 #define RT5670_I2S_BCLK_MS1_64 (0x1 << 15)
858 #define RT5670_I2S_PD2_MASK (0x7 << 8)
859 #define RT5670_I2S_PD2_SFT 8
860 #define RT5670_I2S_PD2_1 (0x0 << 8)
861 #define RT5670_I2S_PD2_2 (0x1 << 8)
862 #define RT5670_I2S_PD2_3 (0x2 << 8)
863 #define RT5670_I2S_PD2_4 (0x3 << 8)
864 #define RT5670_I2S_PD2_6 (0x4 << 8)
865 #define RT5670_I2S_PD2_8 (0x5 << 8)
866 #define RT5670_I2S_PD2_12 (0x6 << 8)
867 #define RT5670_I2S_PD2_16 (0x7 << 8)
914 #define RT5670_DMIC_1_EN_MASK (0x1 << 15)
915 #define RT5670_DMIC_1_EN_SFT 15
916 #define RT5670_DMIC_1_DIS (0x0 << 15)
917 #define RT5670_DMIC_1_EN (0x1 << 15)
938 #define RT5670_DMIC_2R_LH_MASK (0x1 << 8)
939 #define RT5670_DMIC_2R_LH_SFT 8
940 #define RT5670_DMIC_2R_LH_FALLING (0x0 << 8)
941 #define RT5670_DMIC_2R_LH_RISING (0x1 << 8)
966 #define RT5670_SCLK_SRC_RCCLK (0x2 << 14) /* 15MHz */
996 #define RT5670_STO_T_MASK (0x1 << 15)
997 #define RT5670_STO_T_SFT 15
998 #define RT5670_STO_T_SCLK (0x0 << 15)
999 #define RT5670_STO_T_LRCK1 (0x1 << 15)
1012 #define RT5670_DMIC_2_M_MASK (0x1 << 8)
1013 #define RT5670_DMIC_2_M_SFT 8
1014 #define RT5670_DMIC_2_M_NOR (0x0 << 8)
1015 #define RT5670_DMIC_2_M_ASYN (0x1 << 8)
1028 #define RT5670_DA_MONOL_CLK_SEL_MASK (0xf << 8)
1029 #define RT5670_DA_MONOL_CLK_SEL_SFT 8
1038 #define RT5670_DOWN_CLK_SEL_MASK (0xf << 8)
1039 #define RT5670_DOWN_CLK_SEL_SFT 8
1048 #define RT5670_I2S2_PD_MASK (0x7 << 8)
1049 #define RT5670_I2S2_PD_SFT 8
1056 #define RT5670_HP_OC_TH_MASK (0x3 << 8)
1057 #define RT5670_HP_OC_TH_SFT 8
1058 #define RT5670_HP_OC_TH_90 (0x0 << 8)
1059 #define RT5670_HP_OC_TH_105 (0x1 << 8)
1060 #define RT5670_HP_OC_TH_120 (0x2 << 8)
1061 #define RT5670_HP_OC_TH_135 (0x3 << 8)
1068 #define RT5670_AUTO_PD_MASK (0x1 << 8)
1069 #define RT5670_AUTO_PD_SFT 8
1070 #define RT5670_AUTO_PD_DIS (0x0 << 8)
1071 #define RT5670_AUTO_PD_EN (0x1 << 8)
1088 #define RT5670_SMT_TRIG_MASK (0x1 << 15)
1089 #define RT5670_SMT_TRIG_SFT 15
1090 #define RT5670_SMT_TRIG_DIS (0x0 << 15)
1091 #define RT5670_SMT_TRIG_EN (0x1 << 15)
1096 #define RT5670_HP_R_SMT_MASK (0x1 << 8)
1097 #define RT5670_HP_R_SMT_SFT 8
1098 #define RT5670_HP_R_SMT_DIS (0x0 << 8)
1099 #define RT5670_HP_R_SMT_EN (0x1 << 8)
1150 #define RT5670_MRES_MASK (0x3 << 8)
1151 #define RT5670_MRES_SFT 8
1152 #define RT5670_MRES_15MO (0x0 << 8)
1153 #define RT5670_MRES_25MO (0x1 << 8)
1154 #define RT5670_MRES_35MO (0x2 << 8)
1155 #define RT5670_MRES_45MO (0x3 << 8)
1170 #define RT5670_CP_FQ1_MASK (0x7 << 8)
1171 #define RT5670_CP_FQ1_SFT 8
1194 #define RT5670_PM_HP_MASK (0x3 << 8)
1195 #define RT5670_PM_HP_SFT 8
1196 #define RT5670_PM_HP_LV (0x0 << 8)
1197 #define RT5670_PM_HP_MV (0x1 << 8)
1198 #define RT5670_PM_HP_HV (0x2 << 8)
1207 #define RT5670_PVDD_DET_MASK (0x1 << 15)
1208 #define RT5670_PVDD_DET_SFT 15
1209 #define RT5670_PVDD_DET_DIS (0x0 << 15)
1210 #define RT5670_PVDD_DET_EN (0x1 << 15)
1217 #define RT5670_MIC1_BS_MASK (0x1 << 15)
1218 #define RT5670_MIC1_BS_SFT 15
1219 #define RT5670_MIC1_BS_9AV (0x0 << 15)
1220 #define RT5670_MIC1_BS_75AV (0x1 << 15)
1242 #define RT5670_MIC2_OVCD_MASK (0x1 << 8)
1243 #define RT5670_MIC2_OVCD_SFT 8
1244 #define RT5670_MIC2_OVCD_DIS (0x0 << 8)
1245 #define RT5670_MIC2_OVCD_EN (0x1 << 8)
1267 #define RT5670_VAD_SEL_MASK (0x3 << 8)
1268 #define RT5670_VAD_SEL_SFT 8
1271 #define RT5670_EQ_SRC_MASK (0x1 << 15)
1272 #define RT5670_EQ_SRC_SFT 15
1273 #define RT5670_EQ_SRC_DAC (0x0 << 15)
1274 #define RT5670_EQ_SRC_ADC (0x1 << 15)
1281 #define RT5670_EQ_DITH_MASK (0x3 << 8)
1282 #define RT5670_EQ_DITH_SFT 8
1283 #define RT5670_EQ_DITH_NOR (0x0 << 8)
1284 #define RT5670_EQ_DITH_LSB (0x1 << 8)
1285 #define RT5670_EQ_DITH_LSB_1 (0x2 << 8)
1286 #define RT5670_EQ_DITH_LSB_2 (0x3 << 8)
1289 #define RT5670_EQ_HPF1_M_MASK (0x1 << 8)
1290 #define RT5670_EQ_HPF1_M_SFT 8
1291 #define RT5670_EQ_HPF1_M_HI (0x0 << 8)
1292 #define RT5670_EQ_HPF1_M_1ST (0x1 << 8)
1328 #define RT5670_MT_MASK (0x1 << 15)
1329 #define RT5670_MT_SFT 15
1330 #define RT5670_MT_DIS (0x0 << 15)
1331 #define RT5670_MT_EN (0x1 << 15)
1334 #define RT5670_DRC_AGC_P_MASK (0x1 << 15)
1335 #define RT5670_DRC_AGC_P_SFT 15
1336 #define RT5670_DRC_AGC_P_DAC (0x0 << 15)
1337 #define RT5670_DRC_AGC_P_ADC (0x1 << 15)
1344 #define RT5670_DRC_AGC_AR_MASK (0x1f << 8)
1345 #define RT5670_DRC_AGC_AR_SFT 8
1358 #define RT5670_DRC_AGC_POB_MASK (0x3f << 8)
1359 #define RT5670_DRC_AGC_POB_SFT 8
1411 #define RT5670_JD_SPL_TRG_MASK (0x1 << 8)
1412 #define RT5670_JD_SPL_TRG_SFT 8
1413 #define RT5670_JD_SPL_TRG_LO (0x0 << 8)
1414 #define RT5670_JD_SPL_TRG_HI (0x1 << 8)
1449 #define RT5670_IRQ_JD_MASK (0x1 << 15)
1450 #define RT5670_IRQ_JD_SFT 15
1451 #define RT5670_IRQ_JD_BP (0x0 << 15)
1452 #define RT5670_IRQ_JD_NOR (0x1 << 15)
1479 #define RT5670_IRQ_MB1_OC_MASK (0x1 << 15)
1480 #define RT5670_IRQ_MB1_OC_SFT 15
1481 #define RT5670_IRQ_MB1_OC_BP (0x0 << 15)
1482 #define RT5670_IRQ_MB1_OC_NOR (0x1 << 15)
1509 #define RT5670_GP1_PIN_MASK (0x1 << 15)
1510 #define RT5670_GP1_PIN_SFT 15
1511 #define RT5670_GP1_PIN_GPIO1 (0x0 << 15)
1512 #define RT5670_GP1_PIN_IRQ (0x1 << 15)
1534 #define RT5670_I2S2_PIN_MASK (0x1 << 8)
1535 #define RT5670_I2S2_PIN_SFT 8
1536 #define RT5670_I2S2_PIN_I2S (0x0 << 8)
1537 #define RT5670_I2S2_PIN_GPIO (0x1 << 8)
1578 #define RT5670_GP3_PF_MASK (0x1 << 8)
1579 #define RT5670_GP3_PF_SFT 8
1580 #define RT5670_GP3_PF_IN (0x0 << 8)
1581 #define RT5670_GP3_PF_OUT (0x1 << 8)
1620 #define RT5670_SCB_SWAP_MASK (0x1 << 15)
1621 #define RT5670_SCB_SWAP_SFT 15
1622 #define RT5670_SCB_SWAP_DIS (0x0 << 15)
1623 #define RT5670_SCB_SWAP_EN (0x1 << 15)
1630 #define RT5670_BB_MASK (0x1 << 15)
1631 #define RT5670_BB_SFT 15
1632 #define RT5670_BB_DIS (0x0 << 15)
1633 #define RT5670_BB_EN (0x1 << 15)
1642 #define RT5670_M_BB_R_MASK (0x1 << 8)
1643 #define RT5670_M_BB_R_SFT 8
1652 #define RT5670_M_MP3_L_MASK (0x1 << 15)
1653 #define RT5670_M_MP3_L_SFT 15
1660 #define RT5670_EG_MP3_MASK (0x1f << 8)
1661 #define RT5670_EG_MP3_SFT 8
1676 #define RT5670_OG_MP3_MASK (0x1f << 8)
1677 #define RT5670_OG_MP3_SFT 8
1682 #define RT5670_3D_CF_MASK (0x1 << 15)
1683 #define RT5670_3D_CF_SFT 15
1684 #define RT5670_3D_CF_DIS (0x0 << 15)
1685 #define RT5670_3D_CF_EN (0x1 << 15)
1702 #define RT5670_M_3D_D2H_MASK (0x1 << 8)
1703 #define RT5670_M_3D_D2H_SFT 8
1710 #define RT5670_2ND_HPF_MASK (0x1 << 15)
1711 #define RT5670_2ND_HPF_SFT 15
1712 #define RT5670_2ND_HPF_DIS (0x0 << 15)
1713 #define RT5670_2ND_HPF_EN (0x1 << 15)
1720 #define RT5670_HPF_CF_R_MASK (0x7 << 8)
1721 #define RT5670_HPF_CF_R_SFT 8
1769 #define RT5670_SV_MASK (0x1 << 15)
1770 #define RT5670_SV_SFT 15
1771 #define RT5670_SV_DIS (0x0 << 15)
1772 #define RT5670_SV_EN (0x1 << 15)
1796 #define RT5670_M_ZCD_RM_R (0x1 << 8)
1805 #define RT5670_ZCD_HP_MASK (0x1 << 15)
1806 #define RT5670_ZCD_HP_SFT 15
1807 #define RT5670_ZCD_HP_DIS (0x0 << 15)
1808 #define RT5670_ZCD_HP_EN (0x1 << 15)
1817 #define RT5670_3D_SPK_MASK (0x1 << 15)
1818 #define RT5670_3D_SPK_SFT 15
1819 #define RT5670_3D_SPK_DIS (0x0 << 15)
1820 #define RT5670_3D_SPK_EN (0x1 << 15)
1823 #define RT5670_3D_SPK_CG_MASK (0x1f << 8)
1824 #define RT5670_3D_SPK_CG_SFT 8
1829 #define RT5670_WND_MASK (0x1 << 15)
1830 #define RT5670_WND_SFT 15
1831 #define RT5670_WND_DIS (0x0 << 15)
1832 #define RT5670_WND_EN (0x1 << 15)
1854 /* Wind Noise Detection Control 8 (0x73) */
1855 #define RT5670_WND_WIND_MASK (0x1 << 13) /* Read-Only */
1857 #define RT5670_WND_STRONG_MASK (0x1 << 12) /* Read-Only */