Lines Matching +full:8 +full:- +full:15
1 /* SPDX-License-Identifier: GPL-2.0-only */
3 * rt5665.h -- RT5665/RT5658 ALSA SoC audio driver
21 /* I/O - Output */
30 /* I/O - Input */
36 /* I/O - Speaker */
44 /* I/O - ADC/DAC/DMIC */
58 /* Mixer - D-D */
70 /* Mixer - PDM */
76 /* Mixer - ADC */
88 /* Mixer - DAC */
112 /* Format - ADC/DAC */
120 /* Format - TDM Control */
129 /* Function - Analog */
158 /* Function - Digital */
431 #define RT5665_L_MUTE (0x1 << 15)
432 #define RT5665_L_MUTE_SFT 15
439 #define RT5665_L_VOL_MASK (0x3f << 8)
440 #define RT5665_L_VOL_SFT 8
445 #define RT5665_G_HP (0xf << 8)
446 #define RT5665_G_HP_SFT 8
451 #define RT5665_BST_CBJ_MASK (0xf << 8)
452 #define RT5665_BST_CBJ_SFT 8
455 #define RT5665_IN1_DF_MASK (0x1 << 15)
456 #define RT5665_IN1_DF 15
457 #define RT5665_BST1_MASK (0x7f << 8)
458 #define RT5665_BST1_SFT 8
465 #define RT5665_IN3_DF_MASK (0x1 << 15)
466 #define RT5665_IN3_DF 15
467 #define RT5665_BST3_MASK (0x7f << 8)
468 #define RT5665_BST3_SFT 8
475 #define RT5665_INL_VOL_MASK (0x1f << 8)
476 #define RT5665_INL_VOL_SFT 8
481 #define RT5665_EMB_JD_EN (0x1 << 15)
482 #define RT5665_EMB_JD_EN_SFT 15
489 #define RT5665_POL_FAST_OFF_MASK (0x1 << 8)
490 #define RT5665_POL_FAST_OFF_HIGH (0x1 << 8)
491 #define RT5665_POL_FAST_OFF_LOW (0x0 << 8)
525 #define RT5665_SIL_DET_MASK (0x1 << 15)
526 #define RT5665_SIL_DET_DIS (0x0 << 15)
527 #define RT5665_SIL_DET_EN (0x1 << 15)
546 #define RT5665_DAC_L1_VOL_MASK (0xff << 8)
547 #define RT5665_DAC_L1_VOL_SFT 8
552 #define RT5665_DAC_L2_VOL_MASK (0xff << 8)
553 #define RT5665_DAC_L2_VOL_SFT 8
568 #define RT5665_ADC_L_VOL_MASK (0x7f << 8)
569 #define RT5665_ADC_L_VOL_SFT 8
574 #define RT5665_MONO_ADC_L_VOL_MASK (0x7f << 8)
575 #define RT5665_MONO_ADC_L_VOL_SFT 8
598 #define RT5665_M_STO1_ADC_L1 (0x1 << 15)
599 #define RT5665_M_STO1_ADC_L1_SFT 15
612 #define RT5665_STO1_DMIC_SRC_MASK (0x1 << 8)
613 #define RT5665_STO1_DMIC_SRC_SFT 8
614 #define RT5665_STO1_DMIC_SRC_DMIC2 (0x1 << 8)
615 #define RT5665_STO1_DMIC_SRC_DMIC1 (0x0 << 8)
631 #define RT5665_M_MONO_ADC_L1 (0x1 << 15)
632 #define RT5665_M_MONO_ADC_L1_SFT 15
643 #define RT5665_MONO_DMIC_L_SRC_MASK (0x1 << 8)
644 #define RT5665_MONO_DMIC_L_SRC_SFT 8
661 #define RT5665_M_STO2_ADC_L1 (0x1 << 15)
662 #define RT5665_M_STO2_ADC_L1_UN (0x0 << 15)
663 #define RT5665_M_STO2_ADC_L1_SFT 15
676 #define RT5665_STO2_DMIC_SRC_MASK (0x1 << 8)
677 #define RT5665_STO2_DMIC_SRC_SFT 8
678 #define RT5665_STO2_DMIC_SRC_DMIC2 (0x1 << 8)
679 #define RT5665_STO2_DMIC_SRC_DMIC1 (0x0 << 8)
695 #define RT5665_M_ADCMIX_L (0x1 << 15)
696 #define RT5665_M_ADCMIX_L_SFT 15
701 #define RT5665_DAC1_L_SEL_MASK (0x3 << 8)
702 #define RT5665_DAC1_L_SEL_SFT 8
709 #define RT5665_M_DAC_L1_STO_L (0x1 << 15)
710 #define RT5665_M_DAC_L1_STO_L_SFT 15
723 #define RT5665_G_DAC_R2_STO_L_MASK (0x1 << 8)
724 #define RT5665_G_DAC_R2_STO_L_SFT 8
743 #define RT5665_M_DAC_L1_MONO_L (0x1 << 15)
744 #define RT5665_M_DAC_L1_MONO_L_SFT 15
757 #define RT5665_G_DAC_R2_MONO_L_MASK (0x1 << 8)
758 #define RT5665_G_DAC_R2_MONO_L_SFT 8
777 #define RT5665_M_DAC_L1_STO2_L (0x1 << 15)
778 #define RT5665_M_DAC_L1_STO2_L_SFT 15
791 #define RT5665_M_ST_DAC_R1 (0x1 << 8)
792 #define RT5665_M_ST_DAC_R1_SFT 8
809 #define RT5665_DAC_MIX_R_MASK (0x3 << 8)
810 #define RT5665_DAC_MIX_R_SFT 8
827 #define RT5665_IF2_1_ADC_SEL_MASK (0x3 << 8)
828 #define RT5665_IF2_1_ADC_SEL_SFT 8
851 #define RT5665_PDM1_R_MASK (0x3 << 8)
852 #define RT5665_PDM1_R_SFT 8
958 #define RT5665_M_SPKVOLR_SPKOMIX (0x1 << 8)
959 #define RT5665_M_SPKVOLR_SPKOMIX_SFT 8
966 #define RT5665_M_DAC_L2_MA (0x1 << 8)
967 #define RT5665_M_DAC_L2_MA_SFT 8
1016 #define RT5665_M_DAC_L2_LM (0x1 << 15)
1017 #define RT5665_M_DAC_L2_LM_SFT 15
1029 #define RT5665_PWR_I2S1_1 (0x1 << 15)
1030 #define RT5665_PWR_I2S1_1_BIT 15
1043 #define RT5665_PWR_LDO (0x1 << 8)
1044 #define RT5665_PWR_LDO_BIT 8
1059 #define RT5665_PWR_ADC_S1F (0x1 << 15)
1060 #define RT5665_PWR_ADC_S1F_BIT 15
1073 #define RT5665_PWR_DAC_MF_R (0x1 << 8)
1074 #define RT5665_PWR_DAC_MF_R_BIT 8
1079 #define RT5665_PWR_VREF1 (0x1 << 15)
1080 #define RT5665_PWR_VREF1_BIT 15
1093 #define RT5665_PWR_LM (0x1 << 8)
1094 #define RT5665_PWR_LM_BIT 8
1114 #define RT5665_PWR_BST1 (0x1 << 15)
1115 #define RT5665_PWR_BST1_BIT 15
1150 #define RT5665_PWR_BST_L (0x1 << 8)
1151 #define RT5665_PWR_BST_L_BIT 8
1162 #define RT5665_PWR_RM2_L (0x1 << 15)
1163 #define RT5665_PWR_RM2_L_BIT 15
1194 #define RT5665_PWR_IN_R (0x1 << 8)
1195 #define RT5665_PWR_IN_R_BIT 8
1202 #define RT5665_SYS_CLK_DET 15
1209 #define RT5665_DMIC_1_EN_MASK (0x1 << 15)
1210 #define RT5665_DMIC_1_EN_SFT 15
1211 #define RT5665_DMIC_1_DIS (0x0 << 15)
1212 #define RT5665_DMIC_1_EN (0x1 << 15)
1248 #define RT5665_I2S_MS_MASK (0x1 << 15)
1249 #define RT5665_I2S_MS_SFT 15
1250 #define RT5665_I2S_MS_M (0x0 << 15)
1251 #define RT5665_I2S_MS_S (0x1 << 15)
1256 #define RT5665_I2S_BP_MASK (0x1 << 8)
1257 #define RT5665_I2S_BP_SFT 8
1258 #define RT5665_I2S_BP_NOR (0x0 << 8)
1259 #define RT5665_I2S_BP_INV (0x1 << 8)
1286 #define RT5665_I2S_M_PD2_MASK (0x7 << 8)
1287 #define RT5665_I2S_M_PD2_SFT 8
1288 #define RT5665_I2S_M_PD2_1 (0x0 << 8)
1289 #define RT5665_I2S_M_PD2_2 (0x1 << 8)
1290 #define RT5665_I2S_M_PD2_3 (0x2 << 8)
1291 #define RT5665_I2S_M_PD2_4 (0x3 << 8)
1292 #define RT5665_I2S_M_PD2_6 (0x4 << 8)
1293 #define RT5665_I2S_M_PD2_8 (0x5 << 8)
1294 #define RT5665_I2S_M_PD2_12 (0x6 << 8)
1295 #define RT5665_I2S_M_PD2_16 (0x7 << 8)
1313 #define RT5665_I2S_BCLK_MS2_MASK (0x1 << 15)
1314 #define RT5665_I2S_BCLK_MS2_SFT 15
1315 #define RT5665_I2S_BCLK_MS2_32 (0x0 << 15)
1316 #define RT5665_I2S_BCLK_MS2_64 (0x1 << 15)
1331 #define RT5665_I2S_PD3_MASK (0x7 << 8)
1332 #define RT5665_I2S_PD3_SFT 8
1333 #define RT5665_I2S_PD3_1 (0x0 << 8)
1334 #define RT5665_I2S_PD3_2 (0x1 << 8)
1335 #define RT5665_I2S_PD3_3 (0x2 << 8)
1336 #define RT5665_I2S_PD3_4 (0x3 << 8)
1337 #define RT5665_I2S_PD3_6 (0x4 << 8)
1338 #define RT5665_I2S_PD3_8 (0x5 << 8)
1339 #define RT5665_I2S_PD3_12 (0x6 << 8)
1340 #define RT5665_I2S_PD3_16 (0x7 << 8)
1353 #define RT5665_I2S1_MODE_MASK (0x1 << 15)
1354 #define RT5665_I2S1_MODE_I2S (0x0 << 15)
1355 #define RT5665_I2S1_MODE_TDM (0x1 << 15)
1361 #define RT5665_TDM_OUT_CH_MASK (0x3 << 8)
1362 #define RT5665_TDM_OUT_CH_2 (0x0 << 8)
1363 #define RT5665_TDM_OUT_CH_4 (0x1 << 8)
1364 #define RT5665_TDM_OUT_CH_6 (0x2 << 8)
1365 #define RT5665_TDM_OUT_CH_8 (0x3 << 8)
1382 #define RT5665_I2S1_1_DS_ADC_SLOT67_SFT 8
1391 #define RT5665_IF1_ADC3_SEL_SFT 8
1403 #define RT5665_PLL1_SRC_MASK (0x7 << 8)
1404 #define RT5665_PLL1_SRC_SFT 8
1405 #define RT5665_PLL1_SRC_MCLK (0x0 << 8)
1406 #define RT5665_PLL1_SRC_BCLK1 (0x1 << 8)
1407 #define RT5665_PLL1_SRC_BCLK2 (0x2 << 8)
1408 #define RT5665_PLL1_SRC_BCLK3 (0x3 << 8)
1433 #define RT5665_I2S3_ASRC_MASK (0x1 << 15)
1434 #define RT5665_I2S3_ASRC_SFT 15
1447 #define RT5665_DMIC_STO1_ASRC_MASK (0x1 << 8)
1448 #define RT5665_DMIC_STO1_ASRC_SFT 8
1467 #define RT5665_DA_STO2_CLK_SEL_MASK (0x7 << 8)
1468 #define RT5665_DA_STO2_CLK_SEL_SFT 8
1477 #define RT5665_AD_STO2_CLK_SEL_MASK (0x7 << 8)
1478 #define RT5665_AD_STO2_CLK_SEL_SFT 8
1487 #define RT5665_I2S2_RATE_MASK (0xf << 8)
1488 #define RT5665_I2S2_RATE_SFT 8
1512 #define RT5665_MRES_MASK (0x3 << 8)
1513 #define RT5665_MRES_SFT 8
1514 #define RT5665_MRES_15MO (0x0 << 8)
1515 #define RT5665_MRES_25MO (0x1 << 8)
1516 #define RT5665_MRES_35MO (0x2 << 8)
1517 #define RT5665_MRES_45MO (0x3 << 8)
1532 #define RT5665_CP_FQ1_MASK (0x7 << 8)
1533 #define RT5665_CP_FQ1_SFT 8
1556 #define RT5665_PM_HP_MASK (0x3 << 8)
1557 #define RT5665_PM_HP_SFT 8
1558 #define RT5665_PM_HP_LV (0x0 << 8)
1559 #define RT5665_PM_HP_MV (0x1 << 8)
1560 #define RT5665_PM_HP_HV (0x2 << 8)
1569 #define RT5665_PVDD_DET_MASK (0x1 << 15)
1570 #define RT5665_PVDD_DET_SFT 15
1571 #define RT5665_PVDD_DET_DIS (0x0 << 15)
1572 #define RT5665_PVDD_DET_EN (0x1 << 15)
1579 #define RT5665_MIC1_BS_MASK (0x1 << 15)
1580 #define RT5665_MIC1_BS_SFT 15
1581 #define RT5665_MIC1_BS_9AV (0x0 << 15)
1582 #define RT5665_MIC1_BS_75AV (0x1 << 15)
1604 #define RT5665_MIC2_OVCD_MASK (0x1 << 8)
1605 #define RT5665_MIC2_OVCD_SFT 8
1606 #define RT5665_MIC2_OVCD_DIS (0x0 << 8)
1607 #define RT5665_MIC2_OVCD_EN (0x1 << 8)
1623 #define RT5665_PWR_CLK1M_MASK (0x1 << 8)
1624 #define RT5665_PWR_CLK1M_SFT 8
1625 #define RT5665_PWR_CLK1M_PD (0x0 << 8)
1626 #define RT5665_PWR_CLK1M_PU (0x1 << 8)
1642 #define RT5665_I2S2_M_PD_MASK (0x7 << 8)
1643 #define RT5665_I2S2_M_PD_SFT 8
1651 #define RT5665_EQ_SRC_DAC (0x0 << 15)
1652 #define RT5665_EQ_SRC_ADC (0x1 << 15)
1659 #define RT5665_EQ_DITH_MASK (0x3 << 8)
1660 #define RT5665_EQ_DITH_SFT 8
1661 #define RT5665_EQ_DITH_NOR (0x0 << 8)
1662 #define RT5665_EQ_DITH_LSB (0x1 << 8)
1663 #define RT5665_EQ_DITH_LSB_1 (0x2 << 8)
1664 #define RT5665_EQ_DITH_LSB_2 (0x3 << 8)
1667 #define RT5665_JD1_1_EN_MASK (0x1 << 15)
1668 #define RT5665_JD1_1_EN_SFT 15
1669 #define RT5665_JD1_1_DIS (0x0 << 15)
1670 #define RT5665_JD1_1_EN (0x1 << 15)
1686 #define RT5665_GP1_PIN_MASK (0x1 << 15)
1687 #define RT5665_GP1_PIN_SFT 15
1688 #define RT5665_GP1_PIN_GPIO1 (0x0 << 15)
1689 #define RT5665_GP1_PIN_IRQ (0x1 << 15)
1749 #define RT5665_GP2_OUT_MASK (0x1 << 8)
1750 #define RT5665_GP2_OUT_H (0x0 << 8)
1751 #define RT5665_GP2_OUT_L (0x1 << 8)
1779 #define RT5665_GP7_PF_MASK (0x1 << 15)
1780 #define RT5665_GP7_PF_IN (0x0 << 15)
1781 #define RT5665_GP7_PF_OUT (0x1 << 15)
1800 #define RT5665_GP10_OUT_MASK (0x1 << 8)
1801 #define RT5665_GP10_OUT_H (0x0 << 8)
1802 #define RT5665_GP10_OUT_L (0x1 << 8)
1811 #define RT5665_SV_MASK (0x1 << 15)
1812 #define RT5665_SV_SFT 15
1813 #define RT5665_SV_DIS (0x0 << 15)
1814 #define RT5665_SV_EN (0x1 << 15)
1835 #define RT5665_ZCD_HP_MASK (0x1 << 15)
1836 #define RT5665_ZCD_HP_SFT 15
1837 #define RT5665_ZCD_HP_DIS (0x0 << 15)
1838 #define RT5665_ZCD_HP_EN (0x1 << 15)
1841 #define RT5665_4BTN_IL_MASK (0x1 << 15)
1842 #define RT5665_4BTN_IL_EN (0x1 << 15)
1843 #define RT5665_4BTN_IL_DIS (0x0 << 15)
1898 #define RT5665_SEL_CLK_VOL_MASK (0x1 << 15)
1899 #define RT5665_SEL_CLK_VOL_EN (0x1 << 15)
1900 #define RT5665_SEL_CLK_VOL_DIS (0x0 << 15)
1907 #define RT5665_NG2_EN_MASK (0x1 << 15)
1908 #define RT5665_NG2_EN (0x1 << 15)
1909 #define RT5665_NG2_DIS (0x0 << 15)
1916 #define RT5665_SAR_BUTT_DET_MASK (0x1 << 15)
1917 #define RT5665_SAR_BUTT_DET_EN (0x1 << 15)
1918 #define RT5665_SAR_BUTT_DET_DIS (0x0 << 15)
1937 #define RT5665_SAR_SEL_MB2_MASK (0x1 << 8)
1938 #define RT5665_SAR_SEL_MB2_SEL (0x1 << 8)
1939 #define RT5665_SAR_SEL_MB2_NOSEL (0x0 << 8)