Lines Matching +full:15 +full:- +full:9
1 /* SPDX-License-Identifier: GPL-2.0-only */
3 * rt5665.h -- RT5665/RT5658 ALSA SoC audio driver
21 /* I/O - Output */
30 /* I/O - Input */
36 /* I/O - Speaker */
44 /* I/O - ADC/DAC/DMIC */
58 /* Mixer - D-D */
70 /* Mixer - PDM */
76 /* Mixer - ADC */
88 /* Mixer - DAC */
112 /* Format - ADC/DAC */
120 /* Format - TDM Control */
129 /* Function - Analog */
158 /* Function - Digital */
431 #define RT5665_L_MUTE (0x1 << 15)
432 #define RT5665_L_MUTE_SFT 15
455 #define RT5665_IN1_DF_MASK (0x1 << 15)
456 #define RT5665_IN1_DF 15
465 #define RT5665_IN3_DF_MASK (0x1 << 15)
466 #define RT5665_IN3_DF 15
481 #define RT5665_EMB_JD_EN (0x1 << 15)
482 #define RT5665_EMB_JD_EN_SFT 15
488 #define RT5665_EXT_JD_DIG (0x1 << 9)
525 #define RT5665_SIL_DET_MASK (0x1 << 15)
526 #define RT5665_SIL_DET_DIS (0x0 << 15)
527 #define RT5665_SIL_DET_EN (0x1 << 15)
540 #define RT5665_ST_SEL_MASK (0x7 << 9)
541 #define RT5665_ST_SEL_SFT 9
598 #define RT5665_M_STO1_ADC_L1 (0x1 << 15)
599 #define RT5665_M_STO1_ADC_L1_SFT 15
610 #define RT5665_STO1_DD_L_SRC_MASK (0x1 << 9)
611 #define RT5665_STO1_DD_L_SRC_SFT 9
631 #define RT5665_M_MONO_ADC_L1 (0x1 << 15)
632 #define RT5665_M_MONO_ADC_L1_SFT 15
641 #define RT5665_MONO_DD_L_SRC_MASK (0x1 << 9)
642 #define RT5665_MONO_DD_L_SRC_SFT 9
661 #define RT5665_M_STO2_ADC_L1 (0x1 << 15)
662 #define RT5665_M_STO2_ADC_L1_UN (0x0 << 15)
663 #define RT5665_M_STO2_ADC_L1_SFT 15
674 #define RT5665_STO2_DD_L_SRC_MASK (0x1 << 9)
675 #define RT5665_STO2_DD_L_SRC_SFT 9
695 #define RT5665_M_ADCMIX_L (0x1 << 15)
696 #define RT5665_M_ADCMIX_L_SFT 15
709 #define RT5665_M_DAC_L1_STO_L (0x1 << 15)
710 #define RT5665_M_DAC_L1_STO_L_SFT 15
721 #define RT5665_M_DAC_R2_STO_L (0x1 << 9)
722 #define RT5665_M_DAC_R2_STO_L_SFT 9
743 #define RT5665_M_DAC_L1_MONO_L (0x1 << 15)
744 #define RT5665_M_DAC_L1_MONO_L_SFT 15
755 #define RT5665_M_DAC_R2_MONO_L (0x1 << 9)
756 #define RT5665_M_DAC_R2_MONO_L_SFT 9
777 #define RT5665_M_DAC_L1_STO2_L (0x1 << 15)
778 #define RT5665_M_DAC_L1_STO2_L_SFT 15
789 #define RT5665_M_ST_DAC_L1 (0x1 << 9)
790 #define RT5665_M_ST_DAC_L1_SFT 9
956 #define RT5665_M_DAC_R2_SPKOMIX (0x1 << 9)
957 #define RT5665_M_DAC_R2_SPKOMIX_SFT 9
964 #define RT5665_M_MONOVOL_MA (0x1 << 9)
965 #define RT5665_M_MONOVOL_MA_SFT 9
982 #define RT5665_G_BST2_OM_L_MASK (0x7 << 9)
983 #define RT5665_G_BST2_OM_L_SFT 9
1016 #define RT5665_M_DAC_L2_LM (0x1 << 15)
1017 #define RT5665_M_DAC_L2_LM_SFT 15
1029 #define RT5665_PWR_I2S1_1 (0x1 << 15)
1030 #define RT5665_PWR_I2S1_1_BIT 15
1041 #define RT5665_PWR_I2S3 (0x1 << 9)
1042 #define RT5665_PWR_I2S3_BIT 9
1059 #define RT5665_PWR_ADC_S1F (0x1 << 15)
1060 #define RT5665_PWR_ADC_S1F_BIT 15
1071 #define RT5665_PWR_DAC_MF_L (0x1 << 9)
1072 #define RT5665_PWR_DAC_MF_L_BIT 9
1079 #define RT5665_PWR_VREF1 (0x1 << 15)
1080 #define RT5665_PWR_VREF1_BIT 15
1091 #define RT5665_PWR_MB (0x1 << 9)
1092 #define RT5665_PWR_MB_BIT 9
1114 #define RT5665_PWR_BST1 (0x1 << 15)
1115 #define RT5665_PWR_BST1_BIT 15
1128 #define RT5665_PWR_MB3 (0x1 << 9)
1129 #define RT5665_PWR_MB3_BIT 9
1148 #define RT5665_PWR_CBJ (0x1 << 9)
1149 #define RT5665_PWR_CBJ_BIT 9
1162 #define RT5665_PWR_RM2_L (0x1 << 15)
1163 #define RT5665_PWR_RM2_L_BIT 15
1192 #define RT5665_PWR_IN_L (0x1 << 9)
1193 #define RT5665_PWR_IN_L_BIT 9
1202 #define RT5665_SYS_CLK_DET 15
1209 #define RT5665_DMIC_1_EN_MASK (0x1 << 15)
1210 #define RT5665_DMIC_1_EN_SFT 15
1211 #define RT5665_DMIC_1_DIS (0x0 << 15)
1212 #define RT5665_DMIC_1_EN (0x1 << 15)
1217 #define RT5665_DMIC_2_DP_MASK (0x1 << 9)
1218 #define RT5665_DMIC_2_DP_SFT 9
1219 #define RT5665_DMIC_2_DP_GPIO5 (0x0 << 9)
1220 #define RT5665_DMIC_2_DP_IN2P (0x1 << 9)
1248 #define RT5665_I2S_MS_MASK (0x1 << 15)
1249 #define RT5665_I2S_MS_SFT 15
1250 #define RT5665_I2S_MS_M (0x0 << 15)
1251 #define RT5665_I2S_MS_S (0x1 << 15)
1313 #define RT5665_I2S_BCLK_MS2_MASK (0x1 << 15)
1314 #define RT5665_I2S_BCLK_MS2_SFT 15
1315 #define RT5665_I2S_BCLK_MS2_32 (0x0 << 15)
1316 #define RT5665_I2S_BCLK_MS2_64 (0x1 << 15)
1353 #define RT5665_I2S1_MODE_MASK (0x1 << 15)
1354 #define RT5665_I2S1_MODE_I2S (0x0 << 15)
1355 #define RT5665_I2S1_MODE_TDM (0x1 << 15)
1390 #define RT5665_IF1_ADC2_SEL_SFT 9
1433 #define RT5665_I2S3_ASRC_MASK (0x1 << 15)
1434 #define RT5665_I2S3_ASRC_SFT 15
1445 #define RT5665_DAC_MONO_R_ASRC_MASK (0x1 << 9)
1446 #define RT5665_DAC_MONO_R_ASRC_SFT 9
1569 #define RT5665_PVDD_DET_MASK (0x1 << 15)
1570 #define RT5665_PVDD_DET_SFT 15
1571 #define RT5665_PVDD_DET_DIS (0x0 << 15)
1572 #define RT5665_PVDD_DET_EN (0x1 << 15)
1579 #define RT5665_MIC1_BS_MASK (0x1 << 15)
1580 #define RT5665_MIC1_BS_SFT 15
1581 #define RT5665_MIC1_BS_9AV (0x0 << 15)
1582 #define RT5665_MIC1_BS_75AV (0x1 << 15)
1599 #define RT5665_MIC1_OVTH_MASK (0x3 << 9)
1600 #define RT5665_MIC1_OVTH_SFT 9
1601 #define RT5665_MIC1_OVTH_600UA (0x0 << 9)
1602 #define RT5665_MIC1_OVTH_1500UA (0x1 << 9)
1603 #define RT5665_MIC1_OVTH_2000UA (0x2 << 9)
1619 #define RT5665_PWR_CLK25M_MASK (0x1 << 9)
1620 #define RT5665_PWR_CLK25M_SFT 9
1621 #define RT5665_PWR_CLK25M_PD (0x0 << 9)
1622 #define RT5665_PWR_CLK25M_PU (0x1 << 9)
1651 #define RT5665_EQ_SRC_DAC (0x0 << 15)
1652 #define RT5665_EQ_SRC_ADC (0x1 << 15)
1667 #define RT5665_JD1_1_EN_MASK (0x1 << 15)
1668 #define RT5665_JD1_1_EN_SFT 15
1669 #define RT5665_JD1_1_DIS (0x0 << 15)
1670 #define RT5665_JD1_1_EN (0x1 << 15)
1686 #define RT5665_GP1_PIN_MASK (0x1 << 15)
1687 #define RT5665_GP1_PIN_SFT 15
1688 #define RT5665_GP1_PIN_GPIO1 (0x0 << 15)
1689 #define RT5665_GP1_PIN_IRQ (0x1 << 15)
1700 #define RT5665_GP4_PIN_MASK (0x3 << 9)
1701 #define RT5665_GP4_PIN_SFT 9
1702 #define RT5665_GP4_PIN_GPIO4 (0x0 << 9)
1703 #define RT5665_GP4_PIN_DACDAT2_1 (0x1 << 9)
1704 #define RT5665_GP4_PIN_DMIC1_SDA (0x2 << 9)
1746 #define RT5665_GP2_PF_MASK (0x1 << 9)
1747 #define RT5665_GP2_PF_IN (0x0 << 9)
1748 #define RT5665_GP2_PF_OUT (0x1 << 9)
1779 #define RT5665_GP7_PF_MASK (0x1 << 15)
1780 #define RT5665_GP7_PF_IN (0x0 << 15)
1781 #define RT5665_GP7_PF_OUT (0x1 << 15)
1797 #define RT5665_GP10_PF_MASK (0x1 << 9)
1798 #define RT5665_GP10_PF_IN (0x0 << 9)
1799 #define RT5665_GP10_PF_OUT (0x1 << 9)
1811 #define RT5665_SV_MASK (0x1 << 15)
1812 #define RT5665_SV_SFT 15
1813 #define RT5665_SV_DIS (0x0 << 15)
1814 #define RT5665_SV_EN (0x1 << 15)
1835 #define RT5665_ZCD_HP_MASK (0x1 << 15)
1836 #define RT5665_ZCD_HP_SFT 15
1837 #define RT5665_ZCD_HP_DIS (0x0 << 15)
1838 #define RT5665_ZCD_HP_EN (0x1 << 15)
1841 #define RT5665_4BTN_IL_MASK (0x1 << 15)
1842 #define RT5665_4BTN_IL_EN (0x1 << 15)
1843 #define RT5665_4BTN_IL_DIS (0x0 << 15)
1898 #define RT5665_SEL_CLK_VOL_MASK (0x1 << 15)
1899 #define RT5665_SEL_CLK_VOL_EN (0x1 << 15)
1900 #define RT5665_SEL_CLK_VOL_DIS (0x0 << 15)
1903 #define RT5665_AD2DA_LB_MASK (0x1 << 9)
1904 #define RT5665_AD2DA_LB_SFT 9
1907 #define RT5665_NG2_EN_MASK (0x1 << 15)
1908 #define RT5665_NG2_EN (0x1 << 15)
1909 #define RT5665_NG2_DIS (0x0 << 15)
1916 #define RT5665_SAR_BUTT_DET_MASK (0x1 << 15)
1917 #define RT5665_SAR_BUTT_DET_EN (0x1 << 15)
1918 #define RT5665_SAR_BUTT_DET_DIS (0x0 << 15)
1934 #define RT5665_SAR_SEL_MB1_MASK (0x1 << 9)
1935 #define RT5665_SAR_SEL_MB1_SEL (0x1 << 9)
1936 #define RT5665_SAR_SEL_MB1_NOSEL (0x0 << 9)