Lines Matching +full:asrc +full:- +full:clk +full:- +full:map
1 // SPDX-License-Identifier: GPL-2.0-only
3 * rt5665.c -- RT5665/RT5658 ALSA SoC audio codec driver
26 #include <sound/soc-dapm.h>
887 static const DECLARE_TLV_DB_SCALE(hp_vol_tlv, -2250, 150, 0);
888 static const DECLARE_TLV_DB_SCALE(mono_vol_tlv, -1400, 150, 0);
889 static const DECLARE_TLV_DB_SCALE(out_vol_tlv, -4650, 150, 0);
890 static const DECLARE_TLV_DB_SCALE(dac_vol_tlv, -65625, 375, 0);
891 static const DECLARE_TLV_DB_SCALE(in_vol_tlv, -3450, 150, 0);
892 static const DECLARE_TLV_DB_SCALE(adc_vol_tlv, -17625, 375, 0);
894 static const DECLARE_TLV_DB_SCALE(in_bst_tlv, -1200, 75, 0);
1029 * rt5665_sel_asrc_clk_src - select ASRC clock source for a set of filters
1034 * The ASRC function is for asynchronous MCLK and LRCK. Also, since RT5665 can
1035 * only support standard 32fs or 64fs i2s format, ASRC should be enabled to
1037 * ASRC function will track i2s clock and generate a corresponding system clock
1039 * set of filters specified by the mask. And the codec driver will turn on ASRC
1040 * for these filters if ASRC is selected as their clock source.
1061 return -EINVAL;
1158 * rt5665_headset_detect - Detect headset.
1176 regmap_update_bits(rt5665->regmap, RT5665_MICBIAS_2, 0x100,
1179 regmap_read(rt5665->regmap, RT5665_GPIO_STA, &val);
1181 regmap_update_bits(rt5665->regmap, RT5665_EJD_CTRL_1,
1184 regmap_read(rt5665->regmap, RT5665_GPIO_STA, &val);
1187 regmap_read(rt5665->regmap, RT5665_GPIO_STA,
1192 regmap_update_bits(rt5665->regmap, RT5665_EJD_CTRL_1,
1194 regmap_write(rt5665->regmap, RT5665_EJD_CTRL_3, 0x3424);
1195 regmap_write(rt5665->regmap, RT5665_IL_CMD_1, 0x0048);
1196 regmap_write(rt5665->regmap, RT5665_SAR_IL_CMD_1, 0xa291);
1200 rt5665->sar_adc_value = snd_soc_component_read(rt5665->component,
1203 sar_hs_type = rt5665->pdata.sar_hs_type ?
1204 rt5665->pdata.sar_hs_type : 729;
1206 if (rt5665->sar_adc_value > sar_hs_type) {
1207 rt5665->jack_type = SND_JACK_HEADSET;
1210 rt5665->jack_type = SND_JACK_HEADPHONE;
1211 regmap_write(rt5665->regmap, RT5665_SAR_IL_CMD_1,
1213 regmap_update_bits(rt5665->regmap, RT5665_MICBIAS_2,
1219 regmap_write(rt5665->regmap, RT5665_SAR_IL_CMD_1, 0x2291);
1220 regmap_update_bits(rt5665->regmap, RT5665_MICBIAS_2, 0x100, 0);
1223 if (rt5665->jack_type == SND_JACK_HEADSET)
1225 rt5665->jack_type = 0;
1228 dev_dbg(component->dev, "jack_type = %d\n", rt5665->jack_type);
1229 return rt5665->jack_type;
1237 &rt5665->jack_detect_work, msecs_to_jiffies(250));
1247 if (snd_soc_component_read(rt5665->component, RT5665_AJD1_CTRL) & 0x0010) {
1249 rt5665->jack_type = rt5665_headset_detect(rt5665->component, 0);
1251 snd_soc_jack_report(rt5665->hs_jack, rt5665->jack_type,
1256 schedule_delayed_work(&rt5665->jd_check_work, 500);
1265 switch (rt5665->pdata.jd_src) {
1267 regmap_update_bits(rt5665->regmap, RT5665_GPIO_CTRL_1,
1269 regmap_update_bits(rt5665->regmap, RT5665_RC_CLK_CTRL,
1271 regmap_update_bits(rt5665->regmap, RT5665_PWR_ANLG_2,
1273 regmap_update_bits(rt5665->regmap, RT5665_IRQ_CTRL_1, 0x8, 0x8);
1280 dev_warn(component->dev, "Wrong JD source\n");
1284 rt5665->hs_jack = hs_jack;
1295 while (!rt5665->component) {
1300 while (!snd_soc_card_is_instantiated(rt5665->component->card)) {
1305 while (!rt5665->calibration_done) {
1310 mutex_lock(&rt5665->calibrate_mutex);
1312 val = snd_soc_component_read(rt5665->component, RT5665_AJD1_CTRL) & 0x0010;
1315 if (rt5665->jack_type == 0) {
1317 rt5665->jack_type =
1318 rt5665_headset_detect(rt5665->component, 1);
1321 rt5665->jack_type = SND_JACK_HEADSET;
1322 btn_type = rt5665_button_detect(rt5665->component);
1334 rt5665->jack_type |= SND_JACK_BTN_0;
1339 rt5665->jack_type |= SND_JACK_BTN_1;
1344 rt5665->jack_type |= SND_JACK_BTN_2;
1349 rt5665->jack_type |= SND_JACK_BTN_3;
1355 dev_err(rt5665->component->dev,
1363 rt5665->jack_type = rt5665_headset_detect(rt5665->component, 0);
1366 snd_soc_jack_report(rt5665->hs_jack, rt5665->jack_type,
1371 if (rt5665->jack_type & (SND_JACK_BTN_0 | SND_JACK_BTN_1 |
1373 schedule_delayed_work(&rt5665->jd_check_work, 0);
1375 cancel_delayed_work_sync(&rt5665->jd_check_work);
1377 mutex_unlock(&rt5665->calibrate_mutex);
1459 /* I2S3 CLK Source */
1460 SOC_ENUM("I2S1 Master Clk Sel", rt5665_enum[0]),
1461 SOC_ENUM("I2S2 Master Clk Sel", rt5665_enum[1]),
1462 SOC_ENUM("I2S3 Master Clk Sel", rt5665_enum[2]),
1466 * set_dmic_clk - Set parameter of dmic.
1478 struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm);
1482 pd = rl6231_get_pre_div(rt5665->regmap,
1484 idx = rl6231_calc_dmic_clk(rt5665->sysclk / pd);
1487 dev_err(component->dev, "Failed to set DMIC clock\n");
1498 struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm);
1522 struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm);
1536 struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm);
1538 switch (w->shift) {
1580 /* I2S_Pre_Div1 should be 1 in asrc mode */
1837 /*MX-17 [6:4], MX-17 [2:0]*/
1857 /*MX-1B [6:4], MX-1B [2:0]*/
1877 /* MX-26 [13] [5] */
1897 /* MX-26 [11:10] [3:2] */
1917 /* MX-26 [12] [4] */
1937 /* MX-26 [8] */
1949 /* MX-26 [9] */
1961 /* MX-26 [1:0] */
1974 /* MX-27 [12] */
1988 /* MX-27 [13] */
2000 /* MX-27 [9][1]*/
2020 /* MX-27 [11:10], MX-27 [3:2] */
2040 /* MX-27 [8] */
2053 /* MX-27 [4] */
2066 /* MX-27 [5] */
2079 /* MX-27 [0] */
2093 /* MX-28 [13] [5] */
2113 /* MX-28 [11:10] [3:2] */
2133 /* MX-28 [12] [4] */
2153 /* MX-28 [8] */
2165 /* MX-28 [9] */
2177 /* MX-28 [1] */
2190 /* MX-29 [11:10], MX-29 [9:8]*/
2210 /* MX-2D [13:12], MX-2D [9:8]*/
2230 /* MX-2D [5:4], MX-2D [1:0]*/
2250 /* MX-2E [5:4], MX-2E [0]*/
2270 /* MX-2F [14:12] */
2283 /* MX-2F [6:4] */
2297 /* MX-30 [6:4] */
2311 /* MX-31 [11:10] [9:8] */
2332 /* MX-7a[10] */
2344 /* MX-7a[9] */
2356 /* MX-7a[8] */
2368 /* MX-7b[10] */
2380 /* MX-7b[9] */
2392 /* MX-7b[8] */
2404 /* MX-7b[7] */
2416 /* MX-7a[4:0] MX-7b[4:0] */
2473 struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm);
2505 struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm);
2531 struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm);
2571 struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm);
2575 switch (w->shift) {
2598 switch (w->shift) {
2629 struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm);
2632 switch (w->shift) {
2694 /* ASRC */
2695 SND_SOC_DAPM_SUPPLY_S("I2S1 ASRC", 1, RT5665_ASRC_1,
2697 SND_SOC_DAPM_SUPPLY_S("I2S2 ASRC", 1, RT5665_ASRC_1,
2699 SND_SOC_DAPM_SUPPLY_S("I2S3 ASRC", 1, RT5665_ASRC_1,
2701 SND_SOC_DAPM_SUPPLY_S("DAC STO1 ASRC", 1, RT5665_ASRC_1,
2703 SND_SOC_DAPM_SUPPLY_S("DAC STO2 ASRC", 1, RT5665_ASRC_1,
2705 SND_SOC_DAPM_SUPPLY_S("DAC Mono L ASRC", 1, RT5665_ASRC_1,
2707 SND_SOC_DAPM_SUPPLY_S("DAC Mono R ASRC", 1, RT5665_ASRC_1,
2709 SND_SOC_DAPM_SUPPLY_S("ADC STO1 ASRC", 1, RT5665_ASRC_1,
2711 SND_SOC_DAPM_SUPPLY_S("ADC STO2 ASRC", 1, RT5665_ASRC_1,
2713 SND_SOC_DAPM_SUPPLY_S("ADC Mono L ASRC", 1, RT5665_ASRC_1,
2715 SND_SOC_DAPM_SUPPLY_S("ADC Mono R ASRC", 1, RT5665_ASRC_1,
2717 SND_SOC_DAPM_SUPPLY_S("DMIC STO1 ASRC", 1, RT5665_ASRC_1,
2719 SND_SOC_DAPM_SUPPLY_S("DMIC STO2 ASRC", 1, RT5665_ASRC_1,
2721 SND_SOC_DAPM_SUPPLY_S("DMIC MONO L ASRC", 1, RT5665_ASRC_1,
2723 SND_SOC_DAPM_SUPPLY_S("DMIC MONO R ASRC", 1, RT5665_ASRC_1,
2752 SND_SOC_DAPM_SUPPLY("DMIC CLK", SND_SOC_NOPM, 0, 0,
3221 /* CLK DET */
3254 /*ASRC*/
3255 {"ADC Stereo1 Filter", NULL, "ADC STO1 ASRC", is_using_asrc},
3256 {"ADC Stereo2 Filter", NULL, "ADC STO2 ASRC", is_using_asrc},
3257 {"ADC Mono Left Filter", NULL, "ADC Mono L ASRC", is_using_asrc},
3258 {"ADC Mono Right Filter", NULL, "ADC Mono R ASRC", is_using_asrc},
3259 {"DAC Mono Left Filter", NULL, "DAC Mono L ASRC", is_using_asrc},
3260 {"DAC Mono Right Filter", NULL, "DAC Mono R ASRC", is_using_asrc},
3261 {"DAC Stereo1 Filter", NULL, "DAC STO1 ASRC", is_using_asrc},
3262 {"DAC Stereo2 Filter", NULL, "DAC STO2 ASRC", is_using_asrc},
3263 {"I2S1 ASRC", NULL, "CLKDET"},
3264 {"I2S2 ASRC", NULL, "CLKDET"},
3265 {"I2S3 ASRC", NULL, "CLKDET"},
3276 {"Stereo1 DMIC L Mux", NULL, "DMIC STO1 ASRC"},
3277 {"Stereo1 DMIC R Mux", NULL, "DMIC STO1 ASRC"},
3278 {"Stereo2 DMIC L Mux", NULL, "DMIC STO2 ASRC"},
3279 {"Stereo2 DMIC R Mux", NULL, "DMIC STO2 ASRC"},
3280 {"Mono DMIC L Mux", NULL, "DMIC MONO L ASRC"},
3281 {"Mono DMIC R Mux", NULL, "DMIC MONO R ASRC"},
3283 {"I2S1_1", NULL, "I2S1 ASRC"},
3284 {"I2S1_2", NULL, "I2S1 ASRC"},
3285 {"I2S2_1", NULL, "I2S2 ASRC"},
3286 {"I2S2_2", NULL, "I2S2 ASRC"},
3287 {"I2S3", NULL, "I2S3 ASRC"},
3377 {"DMIC L1", NULL, "DMIC CLK"},
3379 {"DMIC R1", NULL, "DMIC CLK"},
3381 {"DMIC L2", NULL, "DMIC CLK"},
3383 {"DMIC R2", NULL, "DMIC CLK"},
4051 struct snd_soc_component *component = dai->component;
4073 return -EINVAL;
4092 return -EINVAL;
4107 struct snd_soc_component *component = dai->component;
4112 rt5665->lrck[dai->id] = params_rate(params);
4113 pre_div = rl6231_get_clk_info(rt5665->sysclk, rt5665->lrck[dai->id]);
4115 dev_warn(component->dev, "Force using PLL");
4117 rt5665->sysclk, rt5665->lrck[dai->id] * 512);
4119 rt5665->lrck[dai->id] * 512, 0);
4124 dev_err(component->dev, "Unsupported frame size: %d\n", frame_size);
4125 return -EINVAL;
4128 dev_dbg(dai->dev, "lrck is %dHz and pre_div is %d for iis %d\n",
4129 rt5665->lrck[dai->id], pre_div, dai->id);
4147 return -EINVAL;
4150 switch (dai->id) {
4178 dev_err(component->dev, "Invalid dai->id: %d\n", dai->id);
4179 return -EINVAL;
4185 switch (rt5665->lrck[dai->id]) {
4203 if (rt5665->master[RT5665_AIF2_1] || rt5665->master[RT5665_AIF2_2]) {
4207 if (rt5665->master[RT5665_AIF3]) {
4217 struct snd_soc_component *component = dai->component;
4223 rt5665->master[dai->id] = 1;
4227 rt5665->master[dai->id] = 0;
4230 return -EINVAL;
4240 return -EINVAL;
4256 return -EINVAL;
4259 switch (dai->id) {
4278 dev_err(component->dev, "Invalid dai->id: %d\n", dai->id);
4279 return -EINVAL;
4290 if (freq == rt5665->sysclk && clk_id == rt5665->sysclk_src)
4307 dev_err(component->dev, "Invalid clock id (%d)\n", clk_id);
4308 return -EINVAL;
4313 if (rt5665->master[RT5665_AIF2_1] || rt5665->master[RT5665_AIF2_2]) {
4317 if (rt5665->master[RT5665_AIF3]) {
4322 rt5665->sysclk = freq;
4323 rt5665->sysclk_src = clk_id;
4325 dev_dbg(component->dev, "Sysclk is %dHz and clock id is %d\n", freq, clk_id);
4338 if (source == rt5665->pll_src && freq_in == rt5665->pll_in &&
4339 freq_out == rt5665->pll_out)
4343 dev_dbg(component->dev, "PLL disabled\n");
4345 rt5665->pll_in = 0;
4346 rt5665->pll_out = 0;
4370 dev_err(component->dev, "Unknown PLL Source %d\n", source);
4371 return -EINVAL;
4376 dev_err(component->dev, "Unsupported input clock %d\n", freq_in);
4380 dev_dbg(component->dev, "bypass=%d m=%d n=%d k=%d\n",
4390 rt5665->pll_in = freq_in;
4391 rt5665->pll_out = freq_out;
4392 rt5665->pll_src = source;
4399 struct snd_soc_component *component = dai->component;
4402 dev_dbg(component->dev, "%s ratio=%d\n", __func__, ratio);
4404 rt5665->bclk[dai->id] = ratio;
4407 switch (dai->id) {
4432 regmap_update_bits(rt5665->regmap, RT5665_DIG_MISC,
4437 regmap_update_bits(rt5665->regmap, RT5665_PWR_DIG_1,
4439 regmap_update_bits(rt5665->regmap, RT5665_PWR_ANLG_1,
4441 regmap_update_bits(rt5665->regmap, RT5665_DIG_MISC,
4445 regmap_update_bits(rt5665->regmap, RT5665_PWR_DIG_1,
4447 regmap_update_bits(rt5665->regmap, RT5665_PWR_ANLG_1,
4462 rt5665->component = component;
4464 schedule_delayed_work(&rt5665->calibrate_work, msecs_to_jiffies(100));
4473 regmap_write(rt5665->regmap, RT5665_RESET, 0);
4475 regulator_bulk_disable(ARRAY_SIZE(rt5665->supplies), rt5665->supplies);
4483 regcache_cache_only(rt5665->regmap, true);
4484 regcache_mark_dirty(rt5665->regmap);
4492 regcache_cache_only(rt5665->regmap, false);
4493 regcache_sync(rt5665->regmap);
4515 .name = "rt5665-aif1_1",
4534 .name = "rt5665-aif1_2",
4546 .name = "rt5665-aif2_1",
4565 .name = "rt5665-aif2_2",
4584 .name = "rt5665-aif3",
4645 rt5665->pdata.in1_diff = of_property_read_bool(dev->of_node,
4646 "realtek,in1-differential");
4647 rt5665->pdata.in2_diff = of_property_read_bool(dev->of_node,
4648 "realtek,in2-differential");
4649 rt5665->pdata.in3_diff = of_property_read_bool(dev->of_node,
4650 "realtek,in3-differential");
4651 rt5665->pdata.in4_diff = of_property_read_bool(dev->of_node,
4652 "realtek,in4-differential");
4654 of_property_read_u32(dev->of_node, "realtek,dmic1-data-pin",
4655 &rt5665->pdata.dmic1_data_pin);
4656 of_property_read_u32(dev->of_node, "realtek,dmic2-data-pin",
4657 &rt5665->pdata.dmic2_data_pin);
4658 of_property_read_u32(dev->of_node, "realtek,jd-src",
4659 &rt5665->pdata.jd_src);
4668 mutex_lock(&rt5665->calibrate_mutex);
4670 regcache_cache_bypass(rt5665->regmap, true);
4672 regmap_write(rt5665->regmap, RT5665_RESET, 0);
4673 regmap_write(rt5665->regmap, RT5665_BIAS_CUR_CTRL_8, 0xa602);
4674 regmap_write(rt5665->regmap, RT5665_HP_CHARGE_PUMP_1, 0x0c26);
4675 regmap_write(rt5665->regmap, RT5665_MONOMIX_IN_GAIN, 0x021f);
4676 regmap_write(rt5665->regmap, RT5665_MONO_OUT, 0x480a);
4677 regmap_write(rt5665->regmap, RT5665_PWR_MIXER, 0x083f);
4678 regmap_write(rt5665->regmap, RT5665_PWR_DIG_1, 0x0180);
4679 regmap_write(rt5665->regmap, RT5665_EJD_CTRL_1, 0x4040);
4680 regmap_write(rt5665->regmap, RT5665_HP_LOGIC_CTRL_2, 0x0000);
4681 regmap_write(rt5665->regmap, RT5665_DIG_MISC, 0x0001);
4682 regmap_write(rt5665->regmap, RT5665_MICBIAS_2, 0x0380);
4683 regmap_write(rt5665->regmap, RT5665_GLB_CLK, 0x8000);
4684 regmap_write(rt5665->regmap, RT5665_ADDA_CLK_1, 0x1000);
4685 regmap_write(rt5665->regmap, RT5665_CHOP_DAC, 0x3030);
4686 regmap_write(rt5665->regmap, RT5665_CALIB_ADC_CTRL, 0x3c05);
4687 regmap_write(rt5665->regmap, RT5665_PWR_ANLG_1, 0xaa3e);
4689 regmap_write(rt5665->regmap, RT5665_PWR_ANLG_1, 0xfe7e);
4690 regmap_write(rt5665->regmap, RT5665_HP_CALIB_CTRL_2, 0x0321);
4692 regmap_write(rt5665->regmap, RT5665_HP_CALIB_CTRL_1, 0xfc00);
4695 regmap_read(rt5665->regmap, RT5665_HP_CALIB_STA_1, &value);
4703 regmap_write(rt5665->regmap, RT5665_RESET, 0);
4704 regcache_cache_bypass(rt5665->regmap, false);
4711 regmap_write(rt5665->regmap, RT5665_MONO_AMP_CALIB_CTRL_1, 0x9e24);
4714 regmap_read(rt5665->regmap, RT5665_MONO_AMP_CALIB_STA1, &value);
4722 regmap_write(rt5665->regmap, RT5665_RESET, 0);
4723 regcache_cache_bypass(rt5665->regmap, false);
4730 regmap_write(rt5665->regmap, RT5665_RESET, 0);
4731 regcache_cache_bypass(rt5665->regmap, false);
4733 regcache_mark_dirty(rt5665->regmap);
4734 regcache_sync(rt5665->regmap);
4736 regmap_write(rt5665->regmap, RT5665_BIAS_CUR_CTRL_8, 0xa602);
4737 regmap_write(rt5665->regmap, RT5665_ASRC_8, 0x0120);
4740 rt5665->calibration_done = true;
4741 mutex_unlock(&rt5665->calibrate_mutex);
4749 while (!snd_soc_card_is_instantiated(rt5665->component->card)) {
4759 struct rt5665_platform_data *pdata = dev_get_platdata(&i2c->dev);
4764 rt5665 = devm_kzalloc(&i2c->dev, sizeof(struct rt5665_priv),
4768 return -ENOMEM;
4773 rt5665->pdata = *pdata;
4775 rt5665_parse_dt(rt5665, &i2c->dev);
4777 for (i = 0; i < ARRAY_SIZE(rt5665->supplies); i++)
4778 rt5665->supplies[i].supply = rt5665_supply_names[i];
4780 ret = devm_regulator_bulk_get(&i2c->dev, ARRAY_SIZE(rt5665->supplies),
4781 rt5665->supplies);
4783 dev_err(&i2c->dev, "Failed to request supplies: %d\n", ret);
4787 ret = regulator_bulk_enable(ARRAY_SIZE(rt5665->supplies),
4788 rt5665->supplies);
4790 dev_err(&i2c->dev, "Failed to enable supplies: %d\n", ret);
4795 rt5665->gpiod_ldo1_en = devm_gpiod_get_optional(&i2c->dev,
4796 "realtek,ldo1-en",
4798 if (IS_ERR(rt5665->gpiod_ldo1_en)) {
4799 dev_err(&i2c->dev, "Failed gpio request ldo1_en\n");
4800 return PTR_ERR(rt5665->gpiod_ldo1_en);
4806 rt5665->regmap = devm_regmap_init_i2c(i2c, &rt5665_regmap);
4807 if (IS_ERR(rt5665->regmap)) {
4808 ret = PTR_ERR(rt5665->regmap);
4809 dev_err(&i2c->dev, "Failed to allocate register map: %d\n",
4814 regmap_read(rt5665->regmap, RT5665_DEVICE_ID, &val);
4816 dev_err(&i2c->dev,
4818 return -ENODEV;
4821 regmap_read(rt5665->regmap, RT5665_RESET, &val);
4824 rt5665->id = CODEC_5666;
4828 rt5665->id = CODEC_5665;
4832 regmap_write(rt5665->regmap, RT5665_RESET, 0);
4835 if (rt5665->pdata.in1_diff)
4836 regmap_update_bits(rt5665->regmap, RT5665_IN1_IN2,
4838 if (rt5665->pdata.in2_diff)
4839 regmap_update_bits(rt5665->regmap, RT5665_IN1_IN2,
4841 if (rt5665->pdata.in3_diff)
4842 regmap_update_bits(rt5665->regmap, RT5665_IN3_IN4,
4844 if (rt5665->pdata.in4_diff)
4845 regmap_update_bits(rt5665->regmap, RT5665_IN3_IN4,
4849 if (rt5665->pdata.dmic1_data_pin != RT5665_DMIC1_NULL ||
4850 rt5665->pdata.dmic2_data_pin != RT5665_DMIC2_NULL) {
4851 regmap_update_bits(rt5665->regmap, RT5665_GPIO_CTRL_2,
4853 regmap_update_bits(rt5665->regmap, RT5665_GPIO_CTRL_1,
4855 switch (rt5665->pdata.dmic1_data_pin) {
4857 regmap_update_bits(rt5665->regmap, RT5665_DMIC_CTRL_1,
4862 regmap_update_bits(rt5665->regmap, RT5665_DMIC_CTRL_1,
4864 regmap_update_bits(rt5665->regmap, RT5665_GPIO_CTRL_1,
4869 dev_dbg(&i2c->dev, "no DMIC1\n");
4873 switch (rt5665->pdata.dmic2_data_pin) {
4875 regmap_update_bits(rt5665->regmap, RT5665_DMIC_CTRL_1,
4880 regmap_update_bits(rt5665->regmap,
4884 regmap_update_bits(rt5665->regmap, RT5665_GPIO_CTRL_1,
4889 dev_dbg(&i2c->dev, "no DMIC2\n");
4895 regmap_write(rt5665->regmap, RT5665_HP_LOGIC_CTRL_2, 0x0002);
4896 regmap_update_bits(rt5665->regmap, RT5665_EJD_CTRL_1,
4899 regmap_update_bits(rt5665->regmap, RT5665_STO1_DAC_SIL_DET,
4902 regmap_update_bits(rt5665->regmap, RT5665_HP_CHARGE_PUMP_1,
4906 if (rt5665->id == CODEC_5666) {
4907 regmap_update_bits(rt5665->regmap, RT5665_GPIO_CTRL_2,
4909 regmap_update_bits(rt5665->regmap, RT5665_GPIO_CTRL_3,
4914 regmap_update_bits(rt5665->regmap, RT5665_PWR_ANLG_1,
4918 INIT_DELAYED_WORK(&rt5665->jack_detect_work,
4920 INIT_DELAYED_WORK(&rt5665->calibrate_work,
4922 INIT_DELAYED_WORK(&rt5665->jd_check_work,
4925 mutex_init(&rt5665->calibrate_mutex);
4927 if (i2c->irq) {
4928 ret = devm_request_threaded_irq(&i2c->dev, i2c->irq, NULL,
4932 dev_err(&i2c->dev, "Failed to request IRQ: %d\n", ret);
4936 return devm_snd_soc_register_component(&i2c->dev,
4945 regmap_write(rt5665->regmap, RT5665_RESET, 0);