Lines Matching +full:mux +full:-
1 // SPDX-License-Identifier: GPL-2.0-only
3 * rt5665.c -- RT5665/RT5658 ALSA SoC audio codec driver
26 #include <sound/soc-dapm.h>
884 static const DECLARE_TLV_DB_SCALE(hp_vol_tlv, -2250, 150, 0);
885 static const DECLARE_TLV_DB_SCALE(mono_vol_tlv, -1400, 150, 0);
886 static const DECLARE_TLV_DB_SCALE(out_vol_tlv, -4650, 150, 0);
887 static const DECLARE_TLV_DB_SCALE(dac_vol_tlv, -65625, 375, 0);
888 static const DECLARE_TLV_DB_SCALE(in_vol_tlv, -3450, 150, 0);
889 static const DECLARE_TLV_DB_SCALE(adc_vol_tlv, -17625, 375, 0);
891 static const DECLARE_TLV_DB_SCALE(in_bst_tlv, -1200, 75, 0);
952 SOC_DAPM_ENUM("IF1_1 01 ADC Swap Mux", rt5665_if1_1_01_adc_enum);
955 SOC_DAPM_ENUM("IF1_1 23 ADC Swap Mux", rt5665_if1_1_23_adc_enum);
958 SOC_DAPM_ENUM("IF1_1 45 ADC Swap Mux", rt5665_if1_1_45_adc_enum);
961 SOC_DAPM_ENUM("IF1_1 67 ADC Swap Mux", rt5665_if1_1_67_adc_enum);
964 SOC_DAPM_ENUM("IF1_2 01 ADC Swap Mux", rt5665_if1_2_01_adc_enum);
967 SOC_DAPM_ENUM("IF1_2 23 ADC1 Swap Mux", rt5665_if1_2_23_adc_enum);
970 SOC_DAPM_ENUM("IF1_2 45 ADC1 Swap Mux", rt5665_if1_2_45_adc_enum);
973 SOC_DAPM_ENUM("IF1_2 67 ADC1 Swap Mux", rt5665_if1_2_67_adc_enum);
1059 * rt5665_headset_detect - Detect headset.
1077 regmap_update_bits(rt5665->regmap, RT5665_MICBIAS_2, 0x100, in rt5665_headset_detect()
1080 regmap_read(rt5665->regmap, RT5665_GPIO_STA, &val); in rt5665_headset_detect()
1082 regmap_update_bits(rt5665->regmap, RT5665_EJD_CTRL_1, in rt5665_headset_detect()
1085 regmap_read(rt5665->regmap, RT5665_GPIO_STA, &val); in rt5665_headset_detect()
1088 regmap_read(rt5665->regmap, RT5665_GPIO_STA, in rt5665_headset_detect()
1093 regmap_update_bits(rt5665->regmap, RT5665_EJD_CTRL_1, in rt5665_headset_detect()
1095 regmap_write(rt5665->regmap, RT5665_EJD_CTRL_3, 0x3424); in rt5665_headset_detect()
1096 regmap_write(rt5665->regmap, RT5665_IL_CMD_1, 0x0048); in rt5665_headset_detect()
1097 regmap_write(rt5665->regmap, RT5665_SAR_IL_CMD_1, 0xa291); in rt5665_headset_detect()
1101 rt5665->sar_adc_value = snd_soc_component_read(rt5665->component, in rt5665_headset_detect()
1104 sar_hs_type = rt5665->pdata.sar_hs_type ? in rt5665_headset_detect()
1105 rt5665->pdata.sar_hs_type : 729; in rt5665_headset_detect()
1107 if (rt5665->sar_adc_value > sar_hs_type) { in rt5665_headset_detect()
1108 rt5665->jack_type = SND_JACK_HEADSET; in rt5665_headset_detect()
1111 rt5665->jack_type = SND_JACK_HEADPHONE; in rt5665_headset_detect()
1112 regmap_write(rt5665->regmap, RT5665_SAR_IL_CMD_1, in rt5665_headset_detect()
1114 regmap_update_bits(rt5665->regmap, RT5665_MICBIAS_2, in rt5665_headset_detect()
1120 regmap_write(rt5665->regmap, RT5665_SAR_IL_CMD_1, 0x2291); in rt5665_headset_detect()
1121 regmap_update_bits(rt5665->regmap, RT5665_MICBIAS_2, 0x100, 0); in rt5665_headset_detect()
1124 if (rt5665->jack_type == SND_JACK_HEADSET) in rt5665_headset_detect()
1126 rt5665->jack_type = 0; in rt5665_headset_detect()
1129 dev_dbg(component->dev, "jack_type = %d\n", rt5665->jack_type); in rt5665_headset_detect()
1130 return rt5665->jack_type; in rt5665_headset_detect()
1138 &rt5665->jack_detect_work, msecs_to_jiffies(250)); in rt5665_irq()
1148 if (snd_soc_component_read(rt5665->component, RT5665_AJD1_CTRL) & 0x0010) { in rt5665_jd_check_handler()
1150 rt5665->jack_type = rt5665_headset_detect(rt5665->component, 0); in rt5665_jd_check_handler()
1152 snd_soc_jack_report(rt5665->hs_jack, rt5665->jack_type, in rt5665_jd_check_handler()
1157 schedule_delayed_work(&rt5665->jd_check_work, 500); in rt5665_jd_check_handler()
1166 switch (rt5665->pdata.jd_src) { in rt5665_set_jack_detect()
1168 regmap_update_bits(rt5665->regmap, RT5665_GPIO_CTRL_1, in rt5665_set_jack_detect()
1170 regmap_update_bits(rt5665->regmap, RT5665_RC_CLK_CTRL, in rt5665_set_jack_detect()
1172 regmap_update_bits(rt5665->regmap, RT5665_PWR_ANLG_2, in rt5665_set_jack_detect()
1174 regmap_update_bits(rt5665->regmap, RT5665_IRQ_CTRL_1, 0x8, 0x8); in rt5665_set_jack_detect()
1181 dev_warn(component->dev, "Wrong JD source\n"); in rt5665_set_jack_detect()
1185 rt5665->hs_jack = hs_jack; in rt5665_set_jack_detect()
1196 while (!rt5665->component) { in rt5665_jack_detect_handler()
1201 while (!snd_soc_card_is_instantiated(rt5665->component->card)) { in rt5665_jack_detect_handler()
1206 while (!rt5665->calibration_done) { in rt5665_jack_detect_handler()
1211 mutex_lock(&rt5665->calibrate_mutex); in rt5665_jack_detect_handler()
1213 val = snd_soc_component_read(rt5665->component, RT5665_AJD1_CTRL) & 0x0010; in rt5665_jack_detect_handler()
1216 if (rt5665->jack_type == 0) { in rt5665_jack_detect_handler()
1218 rt5665->jack_type = in rt5665_jack_detect_handler()
1219 rt5665_headset_detect(rt5665->component, 1); in rt5665_jack_detect_handler()
1222 rt5665->jack_type = SND_JACK_HEADSET; in rt5665_jack_detect_handler()
1223 btn_type = rt5665_button_detect(rt5665->component); in rt5665_jack_detect_handler()
1235 rt5665->jack_type |= SND_JACK_BTN_0; in rt5665_jack_detect_handler()
1240 rt5665->jack_type |= SND_JACK_BTN_1; in rt5665_jack_detect_handler()
1245 rt5665->jack_type |= SND_JACK_BTN_2; in rt5665_jack_detect_handler()
1250 rt5665->jack_type |= SND_JACK_BTN_3; in rt5665_jack_detect_handler()
1256 dev_err(rt5665->component->dev, in rt5665_jack_detect_handler()
1264 rt5665->jack_type = rt5665_headset_detect(rt5665->component, 0); in rt5665_jack_detect_handler()
1267 snd_soc_jack_report(rt5665->hs_jack, rt5665->jack_type, in rt5665_jack_detect_handler()
1272 if (rt5665->jack_type & (SND_JACK_BTN_0 | SND_JACK_BTN_1 | in rt5665_jack_detect_handler()
1274 schedule_delayed_work(&rt5665->jd_check_work, 0); in rt5665_jack_detect_handler()
1276 cancel_delayed_work_sync(&rt5665->jd_check_work); in rt5665_jack_detect_handler()
1278 mutex_unlock(&rt5665->calibrate_mutex); in rt5665_jack_detect_handler()
1367 * set_dmic_clk - Set parameter of dmic.
1379 struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm); in set_dmic_clk()
1383 pd = rl6231_get_pre_div(rt5665->regmap, in set_dmic_clk()
1385 idx = rl6231_calc_dmic_clk(rt5665->sysclk / pd); in set_dmic_clk()
1388 dev_err(component->dev, "Failed to set DMIC clock\n"); in set_dmic_clk()
1399 struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm); in rt5665_charge_pump_event()
1423 struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm); in is_sys_clk_from_pll()
1437 struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm); in is_using_asrc()
1439 switch (w->shift) { in is_using_asrc()
1738 /*MX-17 [6:4], MX-17 [2:0]*/
1758 /*MX-1B [6:4], MX-1B [2:0]*/
1778 /* MX-26 [13] [5] */
1780 "DD Mux", "ADC"
1798 /* MX-26 [11:10] [3:2] */
1818 /* MX-26 [12] [4] */
1838 /* MX-26 [8] */
1848 SOC_DAPM_ENUM("Stereo1 DMIC Mux", rt5665_sto1_dmic_enum);
1850 /* MX-26 [9] */
1862 /* MX-26 [1:0] */
1875 /* MX-27 [12] */
1889 /* MX-27 [13] */
1891 "DD Mux", "ADC"
1901 /* MX-27 [9][1]*/
1921 /* MX-27 [11:10], MX-27 [3:2] */
1941 /* MX-27 [8] */
1954 /* MX-27 [4] */
1967 /* MX-27 [5] */
1969 "DD Mux", "ADC"
1980 /* MX-27 [0] */
1994 /* MX-28 [13] [5] */
1996 "DD Mux", "ADC"
2014 /* MX-28 [11:10] [3:2] */
2034 /* MX-28 [12] [4] */
2054 /* MX-28 [8] */
2066 /* MX-28 [9] */
2078 /* MX-28 [1] */
2091 /* MX-29 [11:10], MX-29 [9:8]*/
2111 /* MX-2D [13:12], MX-2D [9:8]*/
2131 /* MX-2D [5:4], MX-2D [1:0]*/
2151 /* MX-2E [5:4], MX-2E [0]*/
2171 /* MX-2F [14:12] */
2184 /* MX-2F [6:4] */
2198 /* MX-30 [6:4] */
2212 /* MX-31 [11:10] [9:8] */
2233 /* MX-7a[10] */
2245 /* MX-7a[9] */
2257 /* MX-7a[8] */
2269 /* MX-7b[10] */
2281 /* MX-7b[9] */
2293 /* MX-7b[8] */
2305 /* MX-7b[7] */
2317 /* MX-7a[4:0] MX-7b[4:0] */
2330 SOC_DAPM_ENUM("TDM1 ADC Mux", rt5665_tdm1_adc_data_enum);
2374 struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm); in rt5665_mono_event()
2406 struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm); in rt5665_hp_event()
2432 struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm); in rt5665_lout_event()
2472 struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm); in rt5665_set_verf()
2476 switch (w->shift) { in rt5665_set_verf()
2499 switch (w->shift) { in rt5665_set_verf()
2530 struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm); in rt5665_i2s_pin_event()
2533 switch (w->shift) { in rt5665_i2s_pin_event()
2734 /* ADC Mux */
2735 SND_SOC_DAPM_MUX("Stereo1 DMIC L Mux", SND_SOC_NOPM, 0, 0,
2737 SND_SOC_DAPM_MUX("Stereo1 DMIC R Mux", SND_SOC_NOPM, 0, 0,
2739 SND_SOC_DAPM_MUX("Stereo1 ADC L1 Mux", SND_SOC_NOPM, 0, 0,
2741 SND_SOC_DAPM_MUX("Stereo1 ADC R1 Mux", SND_SOC_NOPM, 0, 0,
2743 SND_SOC_DAPM_MUX("Stereo1 ADC L2 Mux", SND_SOC_NOPM, 0, 0,
2745 SND_SOC_DAPM_MUX("Stereo1 ADC R2 Mux", SND_SOC_NOPM, 0, 0,
2747 SND_SOC_DAPM_MUX("Stereo1 ADC L Mux", SND_SOC_NOPM, 0, 0,
2749 SND_SOC_DAPM_MUX("Stereo1 ADC R Mux", SND_SOC_NOPM, 0, 0,
2751 SND_SOC_DAPM_MUX("Stereo1 DD L Mux", SND_SOC_NOPM, 0, 0,
2753 SND_SOC_DAPM_MUX("Stereo1 DD R Mux", SND_SOC_NOPM, 0, 0,
2755 SND_SOC_DAPM_MUX("Mono ADC L2 Mux", SND_SOC_NOPM, 0, 0,
2757 SND_SOC_DAPM_MUX("Mono ADC R2 Mux", SND_SOC_NOPM, 0, 0,
2759 SND_SOC_DAPM_MUX("Mono ADC L1 Mux", SND_SOC_NOPM, 0, 0,
2761 SND_SOC_DAPM_MUX("Mono ADC R1 Mux", SND_SOC_NOPM, 0, 0,
2763 SND_SOC_DAPM_MUX("Mono DMIC L Mux", SND_SOC_NOPM, 0, 0,
2765 SND_SOC_DAPM_MUX("Mono DMIC R Mux", SND_SOC_NOPM, 0, 0,
2767 SND_SOC_DAPM_MUX("Mono ADC L Mux", SND_SOC_NOPM, 0, 0,
2769 SND_SOC_DAPM_MUX("Mono ADC R Mux", SND_SOC_NOPM, 0, 0,
2771 SND_SOC_DAPM_MUX("Mono DD L Mux", SND_SOC_NOPM, 0, 0,
2773 SND_SOC_DAPM_MUX("Mono DD R Mux", SND_SOC_NOPM, 0, 0,
2775 SND_SOC_DAPM_MUX("Stereo2 DMIC L Mux", SND_SOC_NOPM, 0, 0,
2777 SND_SOC_DAPM_MUX("Stereo2 DMIC R Mux", SND_SOC_NOPM, 0, 0,
2779 SND_SOC_DAPM_MUX("Stereo2 ADC L1 Mux", SND_SOC_NOPM, 0, 0,
2781 SND_SOC_DAPM_MUX("Stereo2 ADC R1 Mux", SND_SOC_NOPM, 0, 0,
2783 SND_SOC_DAPM_MUX("Stereo2 ADC L2 Mux", SND_SOC_NOPM, 0, 0,
2785 SND_SOC_DAPM_MUX("Stereo2 ADC R2 Mux", SND_SOC_NOPM, 0, 0,
2787 SND_SOC_DAPM_MUX("Stereo2 ADC L Mux", SND_SOC_NOPM, 0, 0,
2789 SND_SOC_DAPM_MUX("Stereo2 ADC R Mux", SND_SOC_NOPM, 0, 0,
2791 SND_SOC_DAPM_MUX("Stereo2 DD L Mux", SND_SOC_NOPM, 0, 0,
2793 SND_SOC_DAPM_MUX("Stereo2 DD R Mux", SND_SOC_NOPM, 0, 0,
2867 SND_SOC_DAPM_MUX("IF1_1_ADC1 Mux", SND_SOC_NOPM, 0, 0,
2869 SND_SOC_DAPM_MUX("IF1_1_ADC2 Mux", SND_SOC_NOPM, 0, 0,
2871 SND_SOC_DAPM_MUX("IF1_1_ADC3 Mux", SND_SOC_NOPM, 0, 0,
2874 SND_SOC_DAPM_MUX("IF1_2_ADC1 Mux", SND_SOC_NOPM, 0, 0,
2876 SND_SOC_DAPM_MUX("IF1_2_ADC2 Mux", SND_SOC_NOPM, 0, 0,
2878 SND_SOC_DAPM_MUX("IF1_2_ADC3 Mux", SND_SOC_NOPM, 0, 0,
2880 SND_SOC_DAPM_MUX("IF1_2_ADC4 Mux", SND_SOC_NOPM, 0, 0,
2882 SND_SOC_DAPM_MUX("TDM1 slot 01 Data Mux", SND_SOC_NOPM, 0, 0,
2884 SND_SOC_DAPM_MUX("TDM1 slot 23 Data Mux", SND_SOC_NOPM, 0, 0,
2886 SND_SOC_DAPM_MUX("TDM1 slot 45 Data Mux", SND_SOC_NOPM, 0, 0,
2888 SND_SOC_DAPM_MUX("TDM1 slot 67 Data Mux", SND_SOC_NOPM, 0, 0,
2890 SND_SOC_DAPM_MUX("TDM2 slot 01 Data Mux", SND_SOC_NOPM, 0, 0,
2892 SND_SOC_DAPM_MUX("TDM2 slot 23 Data Mux", SND_SOC_NOPM, 0, 0,
2894 SND_SOC_DAPM_MUX("TDM2 slot 45 Data Mux", SND_SOC_NOPM, 0, 0,
2896 SND_SOC_DAPM_MUX("TDM2 slot 67 Data Mux", SND_SOC_NOPM, 0, 0,
2898 SND_SOC_DAPM_MUX("IF2_1 ADC Mux", SND_SOC_NOPM, 0, 0,
2900 SND_SOC_DAPM_MUX("IF2_2 ADC Mux", SND_SOC_NOPM, 0, 0,
2902 SND_SOC_DAPM_MUX("IF3 ADC Mux", SND_SOC_NOPM, 0, 0,
2904 SND_SOC_DAPM_MUX("IF1_1 0 ADC Swap Mux", SND_SOC_NOPM, 0, 0,
2906 SND_SOC_DAPM_MUX("IF1_1 1 ADC Swap Mux", SND_SOC_NOPM, 0, 0,
2908 SND_SOC_DAPM_MUX("IF1_1 2 ADC Swap Mux", SND_SOC_NOPM, 0, 0,
2910 SND_SOC_DAPM_MUX("IF1_1 3 ADC Swap Mux", SND_SOC_NOPM, 0, 0,
2912 SND_SOC_DAPM_MUX("IF1_1 4 ADC Swap Mux", SND_SOC_NOPM, 0, 0,
2914 SND_SOC_DAPM_MUX("IF1_1 5 ADC Swap Mux", SND_SOC_NOPM, 0, 0,
2916 SND_SOC_DAPM_MUX("IF1_1 6 ADC Swap Mux", SND_SOC_NOPM, 0, 0,
2918 SND_SOC_DAPM_MUX("IF1_1 7 ADC Swap Mux", SND_SOC_NOPM, 0, 0,
2920 SND_SOC_DAPM_MUX("IF1_2 0 ADC Swap Mux", SND_SOC_NOPM, 0, 0,
2922 SND_SOC_DAPM_MUX("IF1_2 1 ADC Swap Mux", SND_SOC_NOPM, 0, 0,
2924 SND_SOC_DAPM_MUX("IF1_2 2 ADC Swap Mux", SND_SOC_NOPM, 0, 0,
2926 SND_SOC_DAPM_MUX("IF1_2 3 ADC Swap Mux", SND_SOC_NOPM, 0, 0,
2928 SND_SOC_DAPM_MUX("IF1_2 4 ADC Swap Mux", SND_SOC_NOPM, 0, 0,
2930 SND_SOC_DAPM_MUX("IF1_2 5 ADC Swap Mux", SND_SOC_NOPM, 0, 0,
2932 SND_SOC_DAPM_MUX("IF1_2 6 ADC Swap Mux", SND_SOC_NOPM, 0, 0,
2934 SND_SOC_DAPM_MUX("IF1_2 7 ADC Swap Mux", SND_SOC_NOPM, 0, 0,
2936 SND_SOC_DAPM_MUX("IF2_1 DAC Swap Mux", SND_SOC_NOPM, 0, 0,
2938 SND_SOC_DAPM_MUX("IF2_1 ADC Swap Mux", SND_SOC_NOPM, 0, 0,
2940 SND_SOC_DAPM_MUX("IF2_2 DAC Swap Mux", SND_SOC_NOPM, 0, 0,
2942 SND_SOC_DAPM_MUX("IF2_2 ADC Swap Mux", SND_SOC_NOPM, 0, 0,
2944 SND_SOC_DAPM_MUX("IF3 DAC Swap Mux", SND_SOC_NOPM, 0, 0,
2946 SND_SOC_DAPM_MUX("IF3 ADC Swap Mux", SND_SOC_NOPM, 0, 0,
3004 /* DAC channel Mux */
3005 SND_SOC_DAPM_MUX("DAC L1 Mux", SND_SOC_NOPM, 0, 0, &rt5665_dac_l1_mux),
3006 SND_SOC_DAPM_MUX("DAC R1 Mux", SND_SOC_NOPM, 0, 0, &rt5665_dac_r1_mux),
3007 SND_SOC_DAPM_MUX("DAC L2 Mux", SND_SOC_NOPM, 0, 0, &rt5665_dac_l2_mux),
3008 SND_SOC_DAPM_MUX("DAC R2 Mux", SND_SOC_NOPM, 0, 0, &rt5665_dac_r2_mux),
3009 SND_SOC_DAPM_MUX("DAC L3 Mux", SND_SOC_NOPM, 0, 0, &rt5665_dac_l3_mux),
3010 SND_SOC_DAPM_MUX("DAC R3 Mux", SND_SOC_NOPM, 0, 0, &rt5665_dac_r3_mux),
3117 SND_SOC_DAPM_MUX("PDM L Mux", SND_SOC_NOPM,
3119 SND_SOC_DAPM_MUX("PDM R Mux", SND_SOC_NOPM,
3177 {"Stereo1 DMIC L Mux", NULL, "DMIC STO1 ASRC"},
3178 {"Stereo1 DMIC R Mux", NULL, "DMIC STO1 ASRC"},
3179 {"Stereo2 DMIC L Mux", NULL, "DMIC STO2 ASRC"},
3180 {"Stereo2 DMIC R Mux", NULL, "DMIC STO2 ASRC"},
3181 {"Mono DMIC L Mux", NULL, "DMIC MONO L ASRC"},
3182 {"Mono DMIC R Mux", NULL, "DMIC MONO R ASRC"},
3287 {"Stereo1 DMIC L Mux", "DMIC1", "DMIC L1"},
3288 {"Stereo1 DMIC L Mux", "DMIC2", "DMIC L2"},
3290 {"Stereo1 DMIC R Mux", "DMIC1", "DMIC R1"},
3291 {"Stereo1 DMIC R Mux", "DMIC2", "DMIC R2"},
3293 {"Mono DMIC L Mux", "DMIC1 L", "DMIC L1"},
3294 {"Mono DMIC L Mux", "DMIC2 L", "DMIC L2"},
3296 {"Mono DMIC R Mux", "DMIC1 R", "DMIC R1"},
3297 {"Mono DMIC R Mux", "DMIC2 R", "DMIC R2"},
3299 {"Stereo2 DMIC L Mux", "DMIC1", "DMIC L1"},
3300 {"Stereo2 DMIC L Mux", "DMIC2", "DMIC L2"},
3302 {"Stereo2 DMIC R Mux", "DMIC1", "DMIC R1"},
3303 {"Stereo2 DMIC R Mux", "DMIC2", "DMIC R2"},
3305 {"Stereo1 ADC L Mux", "ADC1 L", "ADC1 L"},
3306 {"Stereo1 ADC L Mux", "ADC1 R", "ADC1 R"},
3307 {"Stereo1 ADC L Mux", "ADC2 L", "ADC2 L"},
3308 {"Stereo1 ADC L Mux", "ADC2 R", "ADC2 R"},
3309 {"Stereo1 ADC R Mux", "ADC1 L", "ADC1 L"},
3310 {"Stereo1 ADC R Mux", "ADC1 R", "ADC1 R"},
3311 {"Stereo1 ADC R Mux", "ADC2 L", "ADC2 L"},
3312 {"Stereo1 ADC R Mux", "ADC2 R", "ADC2 R"},
3314 {"Stereo1 DD L Mux", "STO2 DAC", "Stereo2 DAC MIXL"},
3315 {"Stereo1 DD L Mux", "MONO DAC", "Mono DAC MIXL"},
3317 {"Stereo1 DD R Mux", "STO2 DAC", "Stereo2 DAC MIXR"},
3318 {"Stereo1 DD R Mux", "MONO DAC", "Mono DAC MIXR"},
3320 {"Stereo1 ADC L1 Mux", "ADC", "Stereo1 ADC L Mux"},
3321 {"Stereo1 ADC L1 Mux", "DD Mux", "Stereo1 DD L Mux"},
3322 {"Stereo1 ADC L2 Mux", "DMIC", "Stereo1 DMIC L Mux"},
3323 {"Stereo1 ADC L2 Mux", "DAC MIX", "DAC MIXL"},
3325 {"Stereo1 ADC R1 Mux", "ADC", "Stereo1 ADC R Mux"},
3326 {"Stereo1 ADC R1 Mux", "DD Mux", "Stereo1 DD R Mux"},
3327 {"Stereo1 ADC R2 Mux", "DMIC", "Stereo1 DMIC R Mux"},
3328 {"Stereo1 ADC R2 Mux", "DAC MIX", "DAC MIXR"},
3330 {"Mono ADC L Mux", "ADC1 L", "ADC1 L"},
3331 {"Mono ADC L Mux", "ADC1 R", "ADC1 R"},
3332 {"Mono ADC L Mux", "ADC2 L", "ADC2 L"},
3333 {"Mono ADC L Mux", "ADC2 R", "ADC2 R"},
3335 {"Mono ADC R Mux", "ADC1 L", "ADC1 L"},
3336 {"Mono ADC R Mux", "ADC1 R", "ADC1 R"},
3337 {"Mono ADC R Mux", "ADC2 L", "ADC2 L"},
3338 {"Mono ADC R Mux", "ADC2 R", "ADC2 R"},
3340 {"Mono DD L Mux", "STO2 DAC", "Stereo2 DAC MIXL"},
3341 {"Mono DD L Mux", "MONO DAC", "Mono DAC MIXL"},
3343 {"Mono DD R Mux", "STO2 DAC", "Stereo2 DAC MIXR"},
3344 {"Mono DD R Mux", "MONO DAC", "Mono DAC MIXR"},
3346 {"Mono ADC L2 Mux", "DMIC", "Mono DMIC L Mux"},
3347 {"Mono ADC L2 Mux", "DAC MIXL", "DAC MIXL"},
3348 {"Mono ADC L1 Mux", "DD Mux", "Mono DD L Mux"},
3349 {"Mono ADC L1 Mux", "ADC", "Mono ADC L Mux"},
3351 {"Mono ADC R1 Mux", "DD Mux", "Mono DD R Mux"},
3352 {"Mono ADC R1 Mux", "ADC", "Mono ADC R Mux"},
3353 {"Mono ADC R2 Mux", "DMIC", "Mono DMIC R Mux"},
3354 {"Mono ADC R2 Mux", "DAC MIXR", "DAC MIXR"},
3356 {"Stereo2 ADC L Mux", "ADC1 L", "ADC1 L"},
3357 {"Stereo2 ADC L Mux", "ADC2 L", "ADC2 L"},
3358 {"Stereo2 ADC L Mux", "ADC1 R", "ADC1 R"},
3359 {"Stereo2 ADC R Mux", "ADC1 L", "ADC1 L"},
3360 {"Stereo2 ADC R Mux", "ADC2 L", "ADC2 L"},
3361 {"Stereo2 ADC R Mux", "ADC1 R", "ADC1 R"},
3363 {"Stereo2 DD L Mux", "STO2 DAC", "Stereo2 DAC MIXL"},
3364 {"Stereo2 DD L Mux", "MONO DAC", "Mono DAC MIXL"},
3366 {"Stereo2 DD R Mux", "STO2 DAC", "Stereo2 DAC MIXR"},
3367 {"Stereo2 DD R Mux", "MONO DAC", "Mono DAC MIXR"},
3369 {"Stereo2 ADC L1 Mux", "ADC", "Stereo2 ADC L Mux"},
3370 {"Stereo2 ADC L1 Mux", "DD Mux", "Stereo2 DD L Mux"},
3371 {"Stereo2 ADC L2 Mux", "DMIC", "Stereo2 DMIC L Mux"},
3372 {"Stereo2 ADC L2 Mux", "DAC MIX", "DAC MIXL"},
3374 {"Stereo2 ADC R1 Mux", "ADC", "Stereo2 ADC R Mux"},
3375 {"Stereo2 ADC R1 Mux", "DD Mux", "Stereo2 DD R Mux"},
3376 {"Stereo2 ADC R2 Mux", "DMIC", "Stereo2 DMIC R Mux"},
3377 {"Stereo2 ADC R2 Mux", "DAC MIX", "DAC MIXR"},
3379 {"Stereo1 ADC MIXL", "ADC1 Switch", "Stereo1 ADC L1 Mux"},
3380 {"Stereo1 ADC MIXL", "ADC2 Switch", "Stereo1 ADC L2 Mux"},
3383 {"Stereo1 ADC MIXR", "ADC1 Switch", "Stereo1 ADC R1 Mux"},
3384 {"Stereo1 ADC MIXR", "ADC2 Switch", "Stereo1 ADC R2 Mux"},
3387 {"Mono ADC MIXL", "ADC1 Switch", "Mono ADC L1 Mux"},
3388 {"Mono ADC MIXL", "ADC2 Switch", "Mono ADC L2 Mux"},
3391 {"Mono ADC MIXR", "ADC1 Switch", "Mono ADC R1 Mux"},
3392 {"Mono ADC MIXR", "ADC2 Switch", "Mono ADC R2 Mux"},
3395 {"Stereo2 ADC MIXL", "ADC1 Switch", "Stereo2 ADC L1 Mux"},
3396 {"Stereo2 ADC MIXL", "ADC2 Switch", "Stereo2 ADC L2 Mux"},
3399 {"Stereo2 ADC MIXR", "ADC1 Switch", "Stereo2 ADC R1 Mux"},
3400 {"Stereo2 ADC MIXR", "ADC2 Switch", "Stereo2 ADC R2 Mux"},
3410 {"IF1_1_ADC1 Mux", "STO1 ADC", "Stereo1 ADC MIX"},
3411 {"IF1_1_ADC1 Mux", "IF2_1 DAC", "IF2_1 DAC"},
3412 {"IF1_1_ADC2 Mux", "STO2 ADC", "Stereo2 ADC MIX"},
3413 {"IF1_1_ADC2 Mux", "IF2_2 DAC", "IF2_2 DAC"},
3414 {"IF1_1_ADC3 Mux", "MONO ADC", "Mono ADC MIX"},
3415 {"IF1_1_ADC3 Mux", "IF3 DAC", "IF3 DAC"},
3418 {"IF1_2_ADC1 Mux", "STO1 ADC", "Stereo1 ADC MIX"},
3419 {"IF1_2_ADC1 Mux", "IF1 DAC", "IF1 DAC1"},
3420 {"IF1_2_ADC2 Mux", "STO2 ADC", "Stereo2 ADC MIX"},
3421 {"IF1_2_ADC2 Mux", "IF2_1 DAC", "IF2_1 DAC"},
3422 {"IF1_2_ADC3 Mux", "MONO ADC", "Mono ADC MIX"},
3423 {"IF1_2_ADC3 Mux", "IF2_2 DAC", "IF2_2 DAC"},
3424 {"IF1_2_ADC4 Mux", "DAC1", "DAC1 MIX"},
3425 {"IF1_2_ADC4 Mux", "IF3 DAC", "IF3 DAC"},
3427 {"TDM1 slot 01 Data Mux", "1234", "IF1_1_ADC1 Mux"},
3428 {"TDM1 slot 01 Data Mux", "1243", "IF1_1_ADC1 Mux"},
3429 {"TDM1 slot 01 Data Mux", "1324", "IF1_1_ADC1 Mux"},
3430 {"TDM1 slot 01 Data Mux", "1342", "IF1_1_ADC1 Mux"},
3431 {"TDM1 slot 01 Data Mux", "1432", "IF1_1_ADC1 Mux"},
3432 {"TDM1 slot 01 Data Mux", "1423", "IF1_1_ADC1 Mux"},
3433 {"TDM1 slot 01 Data Mux", "2134", "IF1_1_ADC2 Mux"},
3434 {"TDM1 slot 01 Data Mux", "2143", "IF1_1_ADC2 Mux"},
3435 {"TDM1 slot 01 Data Mux", "2314", "IF1_1_ADC2 Mux"},
3436 {"TDM1 slot 01 Data Mux", "2341", "IF1_1_ADC2 Mux"},
3437 {"TDM1 slot 01 Data Mux", "2431", "IF1_1_ADC2 Mux"},
3438 {"TDM1 slot 01 Data Mux", "2413", "IF1_1_ADC2 Mux"},
3439 {"TDM1 slot 01 Data Mux", "3124", "IF1_1_ADC3 Mux"},
3440 {"TDM1 slot 01 Data Mux", "3142", "IF1_1_ADC3 Mux"},
3441 {"TDM1 slot 01 Data Mux", "3214", "IF1_1_ADC3 Mux"},
3442 {"TDM1 slot 01 Data Mux", "3241", "IF1_1_ADC3 Mux"},
3443 {"TDM1 slot 01 Data Mux", "3412", "IF1_1_ADC3 Mux"},
3444 {"TDM1 slot 01 Data Mux", "3421", "IF1_1_ADC3 Mux"},
3445 {"TDM1 slot 01 Data Mux", "4123", "IF1_1_ADC4"},
3446 {"TDM1 slot 01 Data Mux", "4132", "IF1_1_ADC4"},
3447 {"TDM1 slot 01 Data Mux", "4213", "IF1_1_ADC4"},
3448 {"TDM1 slot 01 Data Mux", "4231", "IF1_1_ADC4"},
3449 {"TDM1 slot 01 Data Mux", "4312", "IF1_1_ADC4"},
3450 {"TDM1 slot 01 Data Mux", "4321", "IF1_1_ADC4"},
3451 {"TDM1 slot 01 Data Mux", NULL, "I2S1_1"},
3453 {"TDM1 slot 23 Data Mux", "1234", "IF1_1_ADC2 Mux"},
3454 {"TDM1 slot 23 Data Mux", "1243", "IF1_1_ADC2 Mux"},
3455 {"TDM1 slot 23 Data Mux", "1324", "IF1_1_ADC3 Mux"},
3456 {"TDM1 slot 23 Data Mux", "1342", "IF1_1_ADC3 Mux"},
3457 {"TDM1 slot 23 Data Mux", "1432", "IF1_1_ADC4"},
3458 {"TDM1 slot 23 Data Mux", "1423", "IF1_1_ADC4"},
3459 {"TDM1 slot 23 Data Mux", "2134", "IF1_1_ADC1 Mux"},
3460 {"TDM1 slot 23 Data Mux", "2143", "IF1_1_ADC1 Mux"},
3461 {"TDM1 slot 23 Data Mux", "2314", "IF1_1_ADC3 Mux"},
3462 {"TDM1 slot 23 Data Mux", "2341", "IF1_1_ADC3 Mux"},
3463 {"TDM1 slot 23 Data Mux", "2431", "IF1_1_ADC4"},
3464 {"TDM1 slot 23 Data Mux", "2413", "IF1_1_ADC4"},
3465 {"TDM1 slot 23 Data Mux", "3124", "IF1_1_ADC1 Mux"},
3466 {"TDM1 slot 23 Data Mux", "3142", "IF1_1_ADC1 Mux"},
3467 {"TDM1 slot 23 Data Mux", "3214", "IF1_1_ADC2 Mux"},
3468 {"TDM1 slot 23 Data Mux", "3241", "IF1_1_ADC2 Mux"},
3469 {"TDM1 slot 23 Data Mux", "3412", "IF1_1_ADC4"},
3470 {"TDM1 slot 23 Data Mux", "3421", "IF1_1_ADC4"},
3471 {"TDM1 slot 23 Data Mux", "4123", "IF1_1_ADC1 Mux"},
3472 {"TDM1 slot 23 Data Mux", "4132", "IF1_1_ADC1 Mux"},
3473 {"TDM1 slot 23 Data Mux", "4213", "IF1_1_ADC2 Mux"},
3474 {"TDM1 slot 23 Data Mux", "4231", "IF1_1_ADC2 Mux"},
3475 {"TDM1 slot 23 Data Mux", "4312", "IF1_1_ADC3 Mux"},
3476 {"TDM1 slot 23 Data Mux", "4321", "IF1_1_ADC3 Mux"},
3477 {"TDM1 slot 23 Data Mux", NULL, "I2S1_1"},
3479 {"TDM1 slot 45 Data Mux", "1234", "IF1_1_ADC3 Mux"},
3480 {"TDM1 slot 45 Data Mux", "1243", "IF1_1_ADC4"},
3481 {"TDM1 slot 45 Data Mux", "1324", "IF1_1_ADC2 Mux"},
3482 {"TDM1 slot 45 Data Mux", "1342", "IF1_1_ADC4"},
3483 {"TDM1 slot 45 Data Mux", "1432", "IF1_1_ADC3 Mux"},
3484 {"TDM1 slot 45 Data Mux", "1423", "IF1_1_ADC2 Mux"},
3485 {"TDM1 slot 45 Data Mux", "2134", "IF1_1_ADC3 Mux"},
3486 {"TDM1 slot 45 Data Mux", "2143", "IF1_1_ADC4"},
3487 {"TDM1 slot 45 Data Mux", "2314", "IF1_1_ADC1 Mux"},
3488 {"TDM1 slot 45 Data Mux", "2341", "IF1_1_ADC4"},
3489 {"TDM1 slot 45 Data Mux", "2431", "IF1_1_ADC3 Mux"},
3490 {"TDM1 slot 45 Data Mux", "2413", "IF1_1_ADC1 Mux"},
3491 {"TDM1 slot 45 Data Mux", "3124", "IF1_1_ADC2 Mux"},
3492 {"TDM1 slot 45 Data Mux", "3142", "IF1_1_ADC4"},
3493 {"TDM1 slot 45 Data Mux", "3214", "IF1_1_ADC1 Mux"},
3494 {"TDM1 slot 45 Data Mux", "3241", "IF1_1_ADC4"},
3495 {"TDM1 slot 45 Data Mux", "3412", "IF1_1_ADC1 Mux"},
3496 {"TDM1 slot 45 Data Mux", "3421", "IF1_1_ADC2 Mux"},
3497 {"TDM1 slot 45 Data Mux", "4123", "IF1_1_ADC2 Mux"},
3498 {"TDM1 slot 45 Data Mux", "4132", "IF1_1_ADC3 Mux"},
3499 {"TDM1 slot 45 Data Mux", "4213", "IF1_1_ADC1 Mux"},
3500 {"TDM1 slot 45 Data Mux", "4231", "IF1_1_ADC3 Mux"},
3501 {"TDM1 slot 45 Data Mux", "4312", "IF1_1_ADC1 Mux"},
3502 {"TDM1 slot 45 Data Mux", "4321", "IF1_1_ADC2 Mux"},
3503 {"TDM1 slot 45 Data Mux", NULL, "I2S1_1"},
3505 {"TDM1 slot 67 Data Mux", "1234", "IF1_1_ADC4"},
3506 {"TDM1 slot 67 Data Mux", "1243", "IF1_1_ADC3 Mux"},
3507 {"TDM1 slot 67 Data Mux", "1324", "IF1_1_ADC4"},
3508 {"TDM1 slot 67 Data Mux", "1342", "IF1_1_ADC2 Mux"},
3509 {"TDM1 slot 67 Data Mux", "1432", "IF1_1_ADC2 Mux"},
3510 {"TDM1 slot 67 Data Mux", "1423", "IF1_1_ADC3 Mux"},
3511 {"TDM1 slot 67 Data Mux", "2134", "IF1_1_ADC4"},
3512 {"TDM1 slot 67 Data Mux", "2143", "IF1_1_ADC3 Mux"},
3513 {"TDM1 slot 67 Data Mux", "2314", "IF1_1_ADC4"},
3514 {"TDM1 slot 67 Data Mux", "2341", "IF1_1_ADC1 Mux"},
3515 {"TDM1 slot 67 Data Mux", "2431", "IF1_1_ADC1 Mux"},
3516 {"TDM1 slot 67 Data Mux", "2413", "IF1_1_ADC3 Mux"},
3517 {"TDM1 slot 67 Data Mux", "3124", "IF1_1_ADC4"},
3518 {"TDM1 slot 67 Data Mux", "3142", "IF1_1_ADC2 Mux"},
3519 {"TDM1 slot 67 Data Mux", "3214", "IF1_1_ADC4"},
3520 {"TDM1 slot 67 Data Mux", "3241", "IF1_1_ADC1 Mux"},
3521 {"TDM1 slot 67 Data Mux", "3412", "IF1_1_ADC2 Mux"},
3522 {"TDM1 slot 67 Data Mux", "3421", "IF1_1_ADC1 Mux"},
3523 {"TDM1 slot 67 Data Mux", "4123", "IF1_1_ADC3 Mux"},
3524 {"TDM1 slot 67 Data Mux", "4132", "IF1_1_ADC2 Mux"},
3525 {"TDM1 slot 67 Data Mux", "4213", "IF1_1_ADC3 Mux"},
3526 {"TDM1 slot 67 Data Mux", "4231", "IF1_1_ADC1 Mux"},
3527 {"TDM1 slot 67 Data Mux", "4312", "IF1_1_ADC2 Mux"},
3528 {"TDM1 slot 67 Data Mux", "4321", "IF1_1_ADC1 Mux"},
3529 {"TDM1 slot 67 Data Mux", NULL, "I2S1_1"},
3532 {"TDM2 slot 01 Data Mux", "1234", "IF1_2_ADC1 Mux"},
3533 {"TDM2 slot 01 Data Mux", "1243", "IF1_2_ADC1 Mux"},
3534 {"TDM2 slot 01 Data Mux", "1324", "IF1_2_ADC1 Mux"},
3535 {"TDM2 slot 01 Data Mux", "1342", "IF1_2_ADC1 Mux"},
3536 {"TDM2 slot 01 Data Mux", "1432", "IF1_2_ADC1 Mux"},
3537 {"TDM2 slot 01 Data Mux", "1423", "IF1_2_ADC1 Mux"},
3538 {"TDM2 slot 01 Data Mux", "2134", "IF1_2_ADC2 Mux"},
3539 {"TDM2 slot 01 Data Mux", "2143", "IF1_2_ADC2 Mux"},
3540 {"TDM2 slot 01 Data Mux", "2314", "IF1_2_ADC2 Mux"},
3541 {"TDM2 slot 01 Data Mux", "2341", "IF1_2_ADC2 Mux"},
3542 {"TDM2 slot 01 Data Mux", "2431", "IF1_2_ADC2 Mux"},
3543 {"TDM2 slot 01 Data Mux", "2413", "IF1_2_ADC2 Mux"},
3544 {"TDM2 slot 01 Data Mux", "3124", "IF1_2_ADC3 Mux"},
3545 {"TDM2 slot 01 Data Mux", "3142", "IF1_2_ADC3 Mux"},
3546 {"TDM2 slot 01 Data Mux", "3214", "IF1_2_ADC3 Mux"},
3547 {"TDM2 slot 01 Data Mux", "3241", "IF1_2_ADC3 Mux"},
3548 {"TDM2 slot 01 Data Mux", "3412", "IF1_2_ADC3 Mux"},
3549 {"TDM2 slot 01 Data Mux", "3421", "IF1_2_ADC3 Mux"},
3550 {"TDM2 slot 01 Data Mux", "4123", "IF1_2_ADC4 Mux"},
3551 {"TDM2 slot 01 Data Mux", "4132", "IF1_2_ADC4 Mux"},
3552 {"TDM2 slot 01 Data Mux", "4213", "IF1_2_ADC4 Mux"},
3553 {"TDM2 slot 01 Data Mux", "4231", "IF1_2_ADC4 Mux"},
3554 {"TDM2 slot 01 Data Mux", "4312", "IF1_2_ADC4 Mux"},
3555 {"TDM2 slot 01 Data Mux", "4321", "IF1_2_ADC4 Mux"},
3556 {"TDM2 slot 01 Data Mux", NULL, "I2S1_2"},
3558 {"TDM2 slot 23 Data Mux", "1234", "IF1_2_ADC2 Mux"},
3559 {"TDM2 slot 23 Data Mux", "1243", "IF1_2_ADC2 Mux"},
3560 {"TDM2 slot 23 Data Mux", "1324", "IF1_2_ADC3 Mux"},
3561 {"TDM2 slot 23 Data Mux", "1342", "IF1_2_ADC3 Mux"},
3562 {"TDM2 slot 23 Data Mux", "1432", "IF1_2_ADC4 Mux"},
3563 {"TDM2 slot 23 Data Mux", "1423", "IF1_2_ADC4 Mux"},
3564 {"TDM2 slot 23 Data Mux", "2134", "IF1_2_ADC1 Mux"},
3565 {"TDM2 slot 23 Data Mux", "2143", "IF1_2_ADC1 Mux"},
3566 {"TDM2 slot 23 Data Mux", "2314", "IF1_2_ADC3 Mux"},
3567 {"TDM2 slot 23 Data Mux", "2341", "IF1_2_ADC3 Mux"},
3568 {"TDM2 slot 23 Data Mux", "2431", "IF1_2_ADC4 Mux"},
3569 {"TDM2 slot 23 Data Mux", "2413", "IF1_2_ADC4 Mux"},
3570 {"TDM2 slot 23 Data Mux", "3124", "IF1_2_ADC1 Mux"},
3571 {"TDM2 slot 23 Data Mux", "3142", "IF1_2_ADC1 Mux"},
3572 {"TDM2 slot 23 Data Mux", "3214", "IF1_2_ADC2 Mux"},
3573 {"TDM2 slot 23 Data Mux", "3241", "IF1_2_ADC2 Mux"},
3574 {"TDM2 slot 23 Data Mux", "3412", "IF1_2_ADC4 Mux"},
3575 {"TDM2 slot 23 Data Mux", "3421", "IF1_2_ADC4 Mux"},
3576 {"TDM2 slot 23 Data Mux", "4123", "IF1_2_ADC1 Mux"},
3577 {"TDM2 slot 23 Data Mux", "4132", "IF1_2_ADC1 Mux"},
3578 {"TDM2 slot 23 Data Mux", "4213", "IF1_2_ADC2 Mux"},
3579 {"TDM2 slot 23 Data Mux", "4231", "IF1_2_ADC2 Mux"},
3580 {"TDM2 slot 23 Data Mux", "4312", "IF1_2_ADC3 Mux"},
3581 {"TDM2 slot 23 Data Mux", "4321", "IF1_2_ADC3 Mux"},
3582 {"TDM2 slot 23 Data Mux", NULL, "I2S1_2"},
3584 {"TDM2 slot 45 Data Mux", "1234", "IF1_2_ADC3 Mux"},
3585 {"TDM2 slot 45 Data Mux", "1243", "IF1_2_ADC4 Mux"},
3586 {"TDM2 slot 45 Data Mux", "1324", "IF1_2_ADC2 Mux"},
3587 {"TDM2 slot 45 Data Mux", "1342", "IF1_2_ADC4 Mux"},
3588 {"TDM2 slot 45 Data Mux", "1432", "IF1_2_ADC3 Mux"},
3589 {"TDM2 slot 45 Data Mux", "1423", "IF1_2_ADC2 Mux"},
3590 {"TDM2 slot 45 Data Mux", "2134", "IF1_2_ADC3 Mux"},
3591 {"TDM2 slot 45 Data Mux", "2143", "IF1_2_ADC4 Mux"},
3592 {"TDM2 slot 45 Data Mux", "2314", "IF1_2_ADC1 Mux"},
3593 {"TDM2 slot 45 Data Mux", "2341", "IF1_2_ADC4 Mux"},
3594 {"TDM2 slot 45 Data Mux", "2431", "IF1_2_ADC3 Mux"},
3595 {"TDM2 slot 45 Data Mux", "2413", "IF1_2_ADC1 Mux"},
3596 {"TDM2 slot 45 Data Mux", "3124", "IF1_2_ADC2 Mux"},
3597 {"TDM2 slot 45 Data Mux", "3142", "IF1_2_ADC4 Mux"},
3598 {"TDM2 slot 45 Data Mux", "3214", "IF1_2_ADC1 Mux"},
3599 {"TDM2 slot 45 Data Mux", "3241", "IF1_2_ADC4 Mux"},
3600 {"TDM2 slot 45 Data Mux", "3412", "IF1_2_ADC1 Mux"},
3601 {"TDM2 slot 45 Data Mux", "3421", "IF1_2_ADC2 Mux"},
3602 {"TDM2 slot 45 Data Mux", "4123", "IF1_2_ADC2 Mux"},
3603 {"TDM2 slot 45 Data Mux", "4132", "IF1_2_ADC3 Mux"},
3604 {"TDM2 slot 45 Data Mux", "4213", "IF1_2_ADC1 Mux"},
3605 {"TDM2 slot 45 Data Mux", "4231", "IF1_2_ADC3 Mux"},
3606 {"TDM2 slot 45 Data Mux", "4312", "IF1_2_ADC1 Mux"},
3607 {"TDM2 slot 45 Data Mux", "4321", "IF1_2_ADC2 Mux"},
3608 {"TDM2 slot 45 Data Mux", NULL, "I2S1_2"},
3610 {"TDM2 slot 67 Data Mux", "1234", "IF1_2_ADC4 Mux"},
3611 {"TDM2 slot 67 Data Mux", "1243", "IF1_2_ADC3 Mux"},
3612 {"TDM2 slot 67 Data Mux", "1324", "IF1_2_ADC4 Mux"},
3613 {"TDM2 slot 67 Data Mux", "1342", "IF1_2_ADC2 Mux"},
3614 {"TDM2 slot 67 Data Mux", "1432", "IF1_2_ADC2 Mux"},
3615 {"TDM2 slot 67 Data Mux", "1423", "IF1_2_ADC3 Mux"},
3616 {"TDM2 slot 67 Data Mux", "2134", "IF1_2_ADC4 Mux"},
3617 {"TDM2 slot 67 Data Mux", "2143", "IF1_2_ADC3 Mux"},
3618 {"TDM2 slot 67 Data Mux", "2314", "IF1_2_ADC4 Mux"},
3619 {"TDM2 slot 67 Data Mux", "2341", "IF1_2_ADC1 Mux"},
3620 {"TDM2 slot 67 Data Mux", "2431", "IF1_2_ADC1 Mux"},
3621 {"TDM2 slot 67 Data Mux", "2413", "IF1_2_ADC3 Mux"},
3622 {"TDM2 slot 67 Data Mux", "3124", "IF1_2_ADC4 Mux"},
3623 {"TDM2 slot 67 Data Mux", "3142", "IF1_2_ADC2 Mux"},
3624 {"TDM2 slot 67 Data Mux", "3214", "IF1_2_ADC4 Mux"},
3625 {"TDM2 slot 67 Data Mux", "3241", "IF1_2_ADC1 Mux"},
3626 {"TDM2 slot 67 Data Mux", "3412", "IF1_2_ADC2 Mux"},
3627 {"TDM2 slot 67 Data Mux", "3421", "IF1_2_ADC1 Mux"},
3628 {"TDM2 slot 67 Data Mux", "4123", "IF1_2_ADC3 Mux"},
3629 {"TDM2 slot 67 Data Mux", "4132", "IF1_2_ADC2 Mux"},
3630 {"TDM2 slot 67 Data Mux", "4213", "IF1_2_ADC3 Mux"},
3631 {"TDM2 slot 67 Data Mux", "4231", "IF1_2_ADC1 Mux"},
3632 {"TDM2 slot 67 Data Mux", "4312", "IF1_2_ADC2 Mux"},
3633 {"TDM2 slot 67 Data Mux", "4321", "IF1_2_ADC1 Mux"},
3634 {"TDM2 slot 67 Data Mux", NULL, "I2S1_2"},
3636 {"IF1_1 0 ADC Swap Mux", "L/R", "TDM1 slot 01 Data Mux"},
3637 {"IF1_1 0 ADC Swap Mux", "L/L", "TDM1 slot 01 Data Mux"},
3638 {"IF1_1 1 ADC Swap Mux", "R/L", "TDM1 slot 01 Data Mux"},
3639 {"IF1_1 1 ADC Swap Mux", "R/R", "TDM1 slot 01 Data Mux"},
3640 {"IF1_1 2 ADC Swap Mux", "L/R", "TDM1 slot 23 Data Mux"},
3641 {"IF1_1 2 ADC Swap Mux", "R/L", "TDM1 slot 23 Data Mux"},
3642 {"IF1_1 3 ADC Swap Mux", "L/L", "TDM1 slot 23 Data Mux"},
3643 {"IF1_1 3 ADC Swap Mux", "R/R", "TDM1 slot 23 Data Mux"},
3644 {"IF1_1 4 ADC Swap Mux", "L/R", "TDM1 slot 45 Data Mux"},
3645 {"IF1_1 4 ADC Swap Mux", "R/L", "TDM1 slot 45 Data Mux"},
3646 {"IF1_1 5 ADC Swap Mux", "L/L", "TDM1 slot 45 Data Mux"},
3647 {"IF1_1 5 ADC Swap Mux", "R/R", "TDM1 slot 45 Data Mux"},
3648 {"IF1_1 6 ADC Swap Mux", "L/R", "TDM1 slot 67 Data Mux"},
3649 {"IF1_1 6 ADC Swap Mux", "R/L", "TDM1 slot 67 Data Mux"},
3650 {"IF1_1 7 ADC Swap Mux", "L/L", "TDM1 slot 67 Data Mux"},
3651 {"IF1_1 7 ADC Swap Mux", "R/R", "TDM1 slot 67 Data Mux"},
3652 {"IF1_2 0 ADC Swap Mux", "L/R", "TDM2 slot 01 Data Mux"},
3653 {"IF1_2 0 ADC Swap Mux", "R/L", "TDM2 slot 01 Data Mux"},
3654 {"IF1_2 1 ADC Swap Mux", "L/L", "TDM2 slot 01 Data Mux"},
3655 {"IF1_2 1 ADC Swap Mux", "R/R", "TDM2 slot 01 Data Mux"},
3656 {"IF1_2 2 ADC Swap Mux", "L/R", "TDM2 slot 23 Data Mux"},
3657 {"IF1_2 2 ADC Swap Mux", "R/L", "TDM2 slot 23 Data Mux"},
3658 {"IF1_2 3 ADC Swap Mux", "L/L", "TDM2 slot 23 Data Mux"},
3659 {"IF1_2 3 ADC Swap Mux", "R/R", "TDM2 slot 23 Data Mux"},
3660 {"IF1_2 4 ADC Swap Mux", "L/R", "TDM2 slot 45 Data Mux"},
3661 {"IF1_2 4 ADC Swap Mux", "R/L", "TDM2 slot 45 Data Mux"},
3662 {"IF1_2 5 ADC Swap Mux", "L/L", "TDM2 slot 45 Data Mux"},
3663 {"IF1_2 5 ADC Swap Mux", "R/R", "TDM2 slot 45 Data Mux"},
3664 {"IF1_2 6 ADC Swap Mux", "L/R", "TDM2 slot 67 Data Mux"},
3665 {"IF1_2 6 ADC Swap Mux", "R/L", "TDM2 slot 67 Data Mux"},
3666 {"IF1_2 7 ADC Swap Mux", "L/L", "TDM2 slot 67 Data Mux"},
3667 {"IF1_2 7 ADC Swap Mux", "R/R", "TDM2 slot 67 Data Mux"},
3669 {"IF2_1 ADC Mux", "STO1 ADC", "Stereo1 ADC MIX"},
3670 {"IF2_1 ADC Mux", "STO2 ADC", "Stereo2 ADC MIX"},
3671 {"IF2_1 ADC Mux", "MONO ADC", "Mono ADC MIX"},
3672 {"IF2_1 ADC Mux", "IF1 DAC1", "IF1 DAC1"},
3673 {"IF2_1 ADC Mux", "IF1 DAC2", "IF1 DAC2"},
3674 {"IF2_1 ADC Mux", "IF2_2 DAC", "IF2_2 DAC"},
3675 {"IF2_1 ADC Mux", "IF3 DAC", "IF3 DAC"},
3676 {"IF2_1 ADC Mux", "DAC1 MIX", "DAC1 MIX"},
3677 {"IF2_1 ADC", NULL, "IF2_1 ADC Mux"},
3680 {"IF2_2 ADC Mux", "STO1 ADC", "Stereo1 ADC MIX"},
3681 {"IF2_2 ADC Mux", "STO2 ADC", "Stereo2 ADC MIX"},
3682 {"IF2_2 ADC Mux", "MONO ADC", "Mono ADC MIX"},
3683 {"IF2_2 ADC Mux", "IF1 DAC1", "IF1 DAC1"},
3684 {"IF2_2 ADC Mux", "IF1 DAC2", "IF1 DAC2"},
3685 {"IF2_2 ADC Mux", "IF2_1 DAC", "IF2_1 DAC"},
3686 {"IF2_2 ADC Mux", "IF3 DAC", "IF3 DAC"},
3687 {"IF2_2 ADC Mux", "DAC1 MIX", "DAC1 MIX"},
3688 {"IF2_2 ADC", NULL, "IF2_2 ADC Mux"},
3691 {"IF3 ADC Mux", "STO1 ADC", "Stereo1 ADC MIX"},
3692 {"IF3 ADC Mux", "STO2 ADC", "Stereo2 ADC MIX"},
3693 {"IF3 ADC Mux", "MONO ADC", "Mono ADC MIX"},
3694 {"IF3 ADC Mux", "IF1 DAC1", "IF1 DAC1"},
3695 {"IF3 ADC Mux", "IF1 DAC2", "IF1 DAC2"},
3696 {"IF3 ADC Mux", "IF2_1 DAC", "IF2_1 DAC"},
3697 {"IF3 ADC Mux", "IF2_2 DAC", "IF2_2 DAC"},
3698 {"IF3 ADC Mux", "DAC1 MIX", "DAC1 MIX"},
3699 {"IF3 ADC", NULL, "IF3 ADC Mux"},
3702 {"AIF1_1TX slot 0", NULL, "IF1_1 0 ADC Swap Mux"},
3703 {"AIF1_1TX slot 1", NULL, "IF1_1 1 ADC Swap Mux"},
3704 {"AIF1_1TX slot 2", NULL, "IF1_1 2 ADC Swap Mux"},
3705 {"AIF1_1TX slot 3", NULL, "IF1_1 3 ADC Swap Mux"},
3706 {"AIF1_1TX slot 4", NULL, "IF1_1 4 ADC Swap Mux"},
3707 {"AIF1_1TX slot 5", NULL, "IF1_1 5 ADC Swap Mux"},
3708 {"AIF1_1TX slot 6", NULL, "IF1_1 6 ADC Swap Mux"},
3709 {"AIF1_1TX slot 7", NULL, "IF1_1 7 ADC Swap Mux"},
3710 {"AIF1_2TX slot 0", NULL, "IF1_2 0 ADC Swap Mux"},
3711 {"AIF1_2TX slot 1", NULL, "IF1_2 1 ADC Swap Mux"},
3712 {"AIF1_2TX slot 2", NULL, "IF1_2 2 ADC Swap Mux"},
3713 {"AIF1_2TX slot 3", NULL, "IF1_2 3 ADC Swap Mux"},
3714 {"AIF1_2TX slot 4", NULL, "IF1_2 4 ADC Swap Mux"},
3715 {"AIF1_2TX slot 5", NULL, "IF1_2 5 ADC Swap Mux"},
3716 {"AIF1_2TX slot 6", NULL, "IF1_2 6 ADC Swap Mux"},
3717 {"AIF1_2TX slot 7", NULL, "IF1_2 7 ADC Swap Mux"},
3718 {"IF2_1 ADC Swap Mux", "L/R", "IF2_1 ADC"},
3719 {"IF2_1 ADC Swap Mux", "R/L", "IF2_1 ADC"},
3720 {"IF2_1 ADC Swap Mux", "L/L", "IF2_1 ADC"},
3721 {"IF2_1 ADC Swap Mux", "R/R", "IF2_1 ADC"},
3722 {"AIF2_1TX", NULL, "IF2_1 ADC Swap Mux"},
3723 {"IF2_2 ADC Swap Mux", "L/R", "IF2_2 ADC"},
3724 {"IF2_2 ADC Swap Mux", "R/L", "IF2_2 ADC"},
3725 {"IF2_2 ADC Swap Mux", "L/L", "IF2_2 ADC"},
3726 {"IF2_2 ADC Swap Mux", "R/R", "IF2_2 ADC"},
3727 {"AIF2_2TX", NULL, "IF2_2 ADC Swap Mux"},
3728 {"IF3 ADC Swap Mux", "L/R", "IF3 ADC"},
3729 {"IF3 ADC Swap Mux", "R/L", "IF3 ADC"},
3730 {"IF3 ADC Swap Mux", "L/L", "IF3 ADC"},
3731 {"IF3 ADC Swap Mux", "R/R", "IF3 ADC"},
3732 {"AIF3TX", NULL, "IF3 ADC Swap Mux"},
3737 {"IF2_1 DAC Swap Mux", "L/R", "AIF2_1RX"},
3738 {"IF2_1 DAC Swap Mux", "R/L", "AIF2_1RX"},
3739 {"IF2_1 DAC Swap Mux", "L/L", "AIF2_1RX"},
3740 {"IF2_1 DAC Swap Mux", "R/R", "AIF2_1RX"},
3741 {"IF2_2 DAC Swap Mux", "L/R", "AIF2_2RX"},
3742 {"IF2_2 DAC Swap Mux", "R/L", "AIF2_2RX"},
3743 {"IF2_2 DAC Swap Mux", "L/L", "AIF2_2RX"},
3744 {"IF2_2 DAC Swap Mux", "R/R", "AIF2_2RX"},
3745 {"IF2_1 DAC", NULL, "IF2_1 DAC Swap Mux"},
3746 {"IF2_2 DAC", NULL, "IF2_2 DAC Swap Mux"},
3747 {"IF3 DAC Swap Mux", "L/R", "AIF3RX"},
3748 {"IF3 DAC Swap Mux", "R/L", "AIF3RX"},
3749 {"IF3 DAC Swap Mux", "L/L", "AIF3RX"},
3750 {"IF3 DAC Swap Mux", "R/R", "AIF3RX"},
3751 {"IF3 DAC", NULL, "IF3 DAC Swap Mux"},
3773 {"DAC L1 Mux", "IF1 DAC1", "IF1 DAC1 L"},
3774 {"DAC L1 Mux", "IF2_1 DAC", "IF2_1 DAC L"},
3775 {"DAC L1 Mux", "IF2_2 DAC", "IF2_2 DAC L"},
3776 {"DAC L1 Mux", "IF3 DAC", "IF3 DAC L"},
3777 {"DAC L1 Mux", NULL, "DAC Stereo1 Filter"},
3779 {"DAC R1 Mux", "IF1 DAC1", "IF1 DAC1 R"},
3780 {"DAC R1 Mux", "IF2_1 DAC", "IF2_1 DAC R"},
3781 {"DAC R1 Mux", "IF2_2 DAC", "IF2_2 DAC R"},
3782 {"DAC R1 Mux", "IF3 DAC", "IF3 DAC R"},
3783 {"DAC R1 Mux", NULL, "DAC Stereo1 Filter"},
3786 {"DAC1 MIXL", "DAC1 Switch", "DAC L1 Mux"},
3788 {"DAC1 MIXR", "DAC1 Switch", "DAC R1 Mux"},
3793 {"DAC L2 Mux", "IF1 DAC2", "IF1 DAC2 L"},
3794 {"DAC L2 Mux", "IF2_1 DAC", "IF2_1 DAC L"},
3795 {"DAC L2 Mux", "IF2_2 DAC", "IF2_2 DAC L"},
3796 {"DAC L2 Mux", "IF3 DAC", "IF3 DAC L"},
3797 {"DAC L2 Mux", "Mono ADC MIX", "Mono ADC MIXL"},
3798 {"DAC L2 Mux", NULL, "DAC Mono Left Filter"},
3800 {"DAC R2 Mux", "IF1 DAC2", "IF1 DAC2 R"},
3801 {"DAC R2 Mux", "IF2_1 DAC", "IF2_1 DAC R"},
3802 {"DAC R2 Mux", "IF2_2 DAC", "IF2_2 DAC R"},
3803 {"DAC R2 Mux", "IF3 DAC", "IF3 DAC R"},
3804 {"DAC R2 Mux", "Mono ADC MIX", "Mono ADC MIXR"},
3805 {"DAC R2 Mux", NULL, "DAC Mono Right Filter"},
3807 {"DAC L3 Mux", "IF1 DAC2", "IF1 DAC2 L"},
3808 {"DAC L3 Mux", "IF2_1 DAC", "IF2_1 DAC L"},
3809 {"DAC L3 Mux", "IF2_2 DAC", "IF2_2 DAC L"},
3810 {"DAC L3 Mux", "IF3 DAC", "IF3 DAC L"},
3811 {"DAC L3 Mux", "STO2 ADC MIX", "Stereo2 ADC MIXL"},
3812 {"DAC L3 Mux", NULL, "DAC Stereo2 Filter"},
3814 {"DAC R3 Mux", "IF1 DAC2", "IF1 DAC2 R"},
3815 {"DAC R3 Mux", "IF2_1 DAC", "IF2_1 DAC R"},
3816 {"DAC R3 Mux", "IF2_2 DAC", "IF2_2 DAC R"},
3817 {"DAC R3 Mux", "IF3 DAC", "IF3 DAC R"},
3818 {"DAC R3 Mux", "STO2 ADC MIX", "Stereo2 ADC MIXR"},
3819 {"DAC R3 Mux", NULL, "DAC Stereo2 Filter"},
3823 {"Stereo1 DAC MIXL", "DAC L2 Switch", "DAC L2 Mux"},
3824 {"Stereo1 DAC MIXL", "DAC R2 Switch", "DAC R2 Mux"},
3828 {"Stereo1 DAC MIXR", "DAC L2 Switch", "DAC L2 Mux"},
3829 {"Stereo1 DAC MIXR", "DAC R2 Switch", "DAC R2 Mux"},
3832 {"Stereo2 DAC MIXL", "DAC L2 Switch", "DAC L2 Mux"},
3833 {"Stereo2 DAC MIXL", "DAC L3 Switch", "DAC L3 Mux"},
3836 {"Stereo2 DAC MIXR", "DAC R2 Switch", "DAC R2 Mux"},
3837 {"Stereo2 DAC MIXR", "DAC R3 Switch", "DAC R3 Mux"},
3841 {"Mono DAC MIXL", "DAC L2 Switch", "DAC L2 Mux"},
3842 {"Mono DAC MIXL", "DAC R2 Switch", "DAC R2 Mux"},
3845 {"Mono DAC MIXR", "DAC L2 Switch", "DAC L2 Mux"},
3846 {"Mono DAC MIXR", "DAC R2 Switch", "DAC R2 Mux"},
3862 {"DAC L2 Source", "DAC2", "DAC L2 Mux"},
3865 {"DAC R2 Source", "DAC2", "DAC R2 Mux"},
3935 {"PDM L Mux", "Mono DAC", "Mono DAC MIXL"},
3936 {"PDM L Mux", "Stereo1 DAC", "Stereo1 DAC MIXL"},
3937 {"PDM L Mux", "Stereo2 DAC", "Stereo2 DAC MIXL"},
3938 {"PDM L Mux", NULL, "PDM Power"},
3939 {"PDM R Mux", "Mono DAC", "Mono DAC MIXR"},
3940 {"PDM R Mux", "Stereo1 DAC", "Stereo1 DAC MIXR"},
3941 {"PDM R Mux", "Stereo2 DAC", "Stereo2 DAC MIXR"},
3942 {"PDM R Mux", NULL, "PDM Power"},
3943 {"PDM L Playback", "Switch", "PDM L Mux"},
3944 {"PDM R Playback", "Switch", "PDM R Mux"},
3952 struct snd_soc_component *component = dai->component; in rt5665_set_tdm_slot()
3974 return -EINVAL; in rt5665_set_tdm_slot()
3993 return -EINVAL; in rt5665_set_tdm_slot()
4008 struct snd_soc_component *component = dai->component; in rt5665_hw_params()
4013 rt5665->lrck[dai->id] = params_rate(params); in rt5665_hw_params()
4014 pre_div = rl6231_get_clk_info(rt5665->sysclk, rt5665->lrck[dai->id]); in rt5665_hw_params()
4016 dev_warn(component->dev, "Force using PLL"); in rt5665_hw_params()
4018 rt5665->sysclk, rt5665->lrck[dai->id] * 512); in rt5665_hw_params()
4020 rt5665->lrck[dai->id] * 512, 0); in rt5665_hw_params()
4025 dev_err(component->dev, "Unsupported frame size: %d\n", frame_size); in rt5665_hw_params()
4026 return -EINVAL; in rt5665_hw_params()
4029 dev_dbg(dai->dev, "lrck is %dHz and pre_div is %d for iis %d\n", in rt5665_hw_params()
4030 rt5665->lrck[dai->id], pre_div, dai->id); in rt5665_hw_params()
4048 return -EINVAL; in rt5665_hw_params()
4051 switch (dai->id) { in rt5665_hw_params()
4079 dev_err(component->dev, "Invalid dai->id: %d\n", dai->id); in rt5665_hw_params()
4080 return -EINVAL; in rt5665_hw_params()
4086 switch (rt5665->lrck[dai->id]) { in rt5665_hw_params()
4104 if (rt5665->master[RT5665_AIF2_1] || rt5665->master[RT5665_AIF2_2]) { in rt5665_hw_params()
4108 if (rt5665->master[RT5665_AIF3]) { in rt5665_hw_params()
4118 struct snd_soc_component *component = dai->component; in rt5665_set_dai_fmt()
4124 rt5665->master[dai->id] = 1; in rt5665_set_dai_fmt()
4128 rt5665->master[dai->id] = 0; in rt5665_set_dai_fmt()
4131 return -EINVAL; in rt5665_set_dai_fmt()
4141 return -EINVAL; in rt5665_set_dai_fmt()
4157 return -EINVAL; in rt5665_set_dai_fmt()
4160 switch (dai->id) { in rt5665_set_dai_fmt()
4179 dev_err(component->dev, "Invalid dai->id: %d\n", dai->id); in rt5665_set_dai_fmt()
4180 return -EINVAL; in rt5665_set_dai_fmt()
4191 if (freq == rt5665->sysclk && clk_id == rt5665->sysclk_src) in rt5665_set_component_sysclk()
4208 dev_err(component->dev, "Invalid clock id (%d)\n", clk_id); in rt5665_set_component_sysclk()
4209 return -EINVAL; in rt5665_set_component_sysclk()
4214 if (rt5665->master[RT5665_AIF2_1] || rt5665->master[RT5665_AIF2_2]) { in rt5665_set_component_sysclk()
4218 if (rt5665->master[RT5665_AIF3]) { in rt5665_set_component_sysclk()
4223 rt5665->sysclk = freq; in rt5665_set_component_sysclk()
4224 rt5665->sysclk_src = clk_id; in rt5665_set_component_sysclk()
4226 dev_dbg(component->dev, "Sysclk is %dHz and clock id is %d\n", freq, clk_id); in rt5665_set_component_sysclk()
4239 if (source == rt5665->pll_src && freq_in == rt5665->pll_in && in rt5665_set_component_pll()
4240 freq_out == rt5665->pll_out) in rt5665_set_component_pll()
4244 dev_dbg(component->dev, "PLL disabled\n"); in rt5665_set_component_pll()
4246 rt5665->pll_in = 0; in rt5665_set_component_pll()
4247 rt5665->pll_out = 0; in rt5665_set_component_pll()
4271 dev_err(component->dev, "Unknown PLL Source %d\n", source); in rt5665_set_component_pll()
4272 return -EINVAL; in rt5665_set_component_pll()
4277 dev_err(component->dev, "Unsupported input clock %d\n", freq_in); in rt5665_set_component_pll()
4281 dev_dbg(component->dev, "bypass=%d m=%d n=%d k=%d\n", in rt5665_set_component_pll()
4291 rt5665->pll_in = freq_in; in rt5665_set_component_pll()
4292 rt5665->pll_out = freq_out; in rt5665_set_component_pll()
4293 rt5665->pll_src = source; in rt5665_set_component_pll()
4300 struct snd_soc_component *component = dai->component; in rt5665_set_bclk_ratio()
4303 dev_dbg(component->dev, "%s ratio=%d\n", __func__, ratio); in rt5665_set_bclk_ratio()
4305 rt5665->bclk[dai->id] = ratio; in rt5665_set_bclk_ratio()
4308 switch (dai->id) { in rt5665_set_bclk_ratio()
4333 regmap_update_bits(rt5665->regmap, RT5665_DIG_MISC, in rt5665_set_bias_level()
4338 regmap_update_bits(rt5665->regmap, RT5665_PWR_DIG_1, in rt5665_set_bias_level()
4340 regmap_update_bits(rt5665->regmap, RT5665_PWR_ANLG_1, in rt5665_set_bias_level()
4342 regmap_update_bits(rt5665->regmap, RT5665_DIG_MISC, in rt5665_set_bias_level()
4346 regmap_update_bits(rt5665->regmap, RT5665_PWR_DIG_1, in rt5665_set_bias_level()
4348 regmap_update_bits(rt5665->regmap, RT5665_PWR_ANLG_1, in rt5665_set_bias_level()
4363 rt5665->component = component; in rt5665_probe()
4365 schedule_delayed_work(&rt5665->calibrate_work, msecs_to_jiffies(100)); in rt5665_probe()
4374 regmap_write(rt5665->regmap, RT5665_RESET, 0); in rt5665_remove()
4382 regcache_cache_only(rt5665->regmap, true); in rt5665_suspend()
4383 regcache_mark_dirty(rt5665->regmap); in rt5665_suspend()
4391 regcache_cache_only(rt5665->regmap, false); in rt5665_resume()
4392 regcache_sync(rt5665->regmap); in rt5665_resume()
4414 .name = "rt5665-aif1_1",
4433 .name = "rt5665-aif1_2",
4445 .name = "rt5665-aif2_1",
4464 .name = "rt5665-aif2_2",
4483 .name = "rt5665-aif3",
4544 rt5665->pdata.in1_diff = of_property_read_bool(dev->of_node, in rt5665_parse_dt()
4545 "realtek,in1-differential"); in rt5665_parse_dt()
4546 rt5665->pdata.in2_diff = of_property_read_bool(dev->of_node, in rt5665_parse_dt()
4547 "realtek,in2-differential"); in rt5665_parse_dt()
4548 rt5665->pdata.in3_diff = of_property_read_bool(dev->of_node, in rt5665_parse_dt()
4549 "realtek,in3-differential"); in rt5665_parse_dt()
4550 rt5665->pdata.in4_diff = of_property_read_bool(dev->of_node, in rt5665_parse_dt()
4551 "realtek,in4-differential"); in rt5665_parse_dt()
4553 of_property_read_u32(dev->of_node, "realtek,dmic1-data-pin", in rt5665_parse_dt()
4554 &rt5665->pdata.dmic1_data_pin); in rt5665_parse_dt()
4555 of_property_read_u32(dev->of_node, "realtek,dmic2-data-pin", in rt5665_parse_dt()
4556 &rt5665->pdata.dmic2_data_pin); in rt5665_parse_dt()
4557 of_property_read_u32(dev->of_node, "realtek,jd-src", in rt5665_parse_dt()
4558 &rt5665->pdata.jd_src); in rt5665_parse_dt()
4567 mutex_lock(&rt5665->calibrate_mutex); in rt5665_calibrate()
4569 regcache_cache_bypass(rt5665->regmap, true); in rt5665_calibrate()
4571 regmap_write(rt5665->regmap, RT5665_RESET, 0); in rt5665_calibrate()
4572 regmap_write(rt5665->regmap, RT5665_BIAS_CUR_CTRL_8, 0xa602); in rt5665_calibrate()
4573 regmap_write(rt5665->regmap, RT5665_HP_CHARGE_PUMP_1, 0x0c26); in rt5665_calibrate()
4574 regmap_write(rt5665->regmap, RT5665_MONOMIX_IN_GAIN, 0x021f); in rt5665_calibrate()
4575 regmap_write(rt5665->regmap, RT5665_MONO_OUT, 0x480a); in rt5665_calibrate()
4576 regmap_write(rt5665->regmap, RT5665_PWR_MIXER, 0x083f); in rt5665_calibrate()
4577 regmap_write(rt5665->regmap, RT5665_PWR_DIG_1, 0x0180); in rt5665_calibrate()
4578 regmap_write(rt5665->regmap, RT5665_EJD_CTRL_1, 0x4040); in rt5665_calibrate()
4579 regmap_write(rt5665->regmap, RT5665_HP_LOGIC_CTRL_2, 0x0000); in rt5665_calibrate()
4580 regmap_write(rt5665->regmap, RT5665_DIG_MISC, 0x0001); in rt5665_calibrate()
4581 regmap_write(rt5665->regmap, RT5665_MICBIAS_2, 0x0380); in rt5665_calibrate()
4582 regmap_write(rt5665->regmap, RT5665_GLB_CLK, 0x8000); in rt5665_calibrate()
4583 regmap_write(rt5665->regmap, RT5665_ADDA_CLK_1, 0x1000); in rt5665_calibrate()
4584 regmap_write(rt5665->regmap, RT5665_CHOP_DAC, 0x3030); in rt5665_calibrate()
4585 regmap_write(rt5665->regmap, RT5665_CALIB_ADC_CTRL, 0x3c05); in rt5665_calibrate()
4586 regmap_write(rt5665->regmap, RT5665_PWR_ANLG_1, 0xaa3e); in rt5665_calibrate()
4588 regmap_write(rt5665->regmap, RT5665_PWR_ANLG_1, 0xfe7e); in rt5665_calibrate()
4589 regmap_write(rt5665->regmap, RT5665_HP_CALIB_CTRL_2, 0x0321); in rt5665_calibrate()
4591 regmap_write(rt5665->regmap, RT5665_HP_CALIB_CTRL_1, 0xfc00); in rt5665_calibrate()
4594 regmap_read(rt5665->regmap, RT5665_HP_CALIB_STA_1, &value); in rt5665_calibrate()
4602 regmap_write(rt5665->regmap, RT5665_RESET, 0); in rt5665_calibrate()
4603 regcache_cache_bypass(rt5665->regmap, false); in rt5665_calibrate()
4610 regmap_write(rt5665->regmap, RT5665_MONO_AMP_CALIB_CTRL_1, 0x9e24); in rt5665_calibrate()
4613 regmap_read(rt5665->regmap, RT5665_MONO_AMP_CALIB_STA1, &value); in rt5665_calibrate()
4621 regmap_write(rt5665->regmap, RT5665_RESET, 0); in rt5665_calibrate()
4622 regcache_cache_bypass(rt5665->regmap, false); in rt5665_calibrate()
4629 regmap_write(rt5665->regmap, RT5665_RESET, 0); in rt5665_calibrate()
4630 regcache_cache_bypass(rt5665->regmap, false); in rt5665_calibrate()
4632 regcache_mark_dirty(rt5665->regmap); in rt5665_calibrate()
4633 regcache_sync(rt5665->regmap); in rt5665_calibrate()
4635 regmap_write(rt5665->regmap, RT5665_BIAS_CUR_CTRL_8, 0xa602); in rt5665_calibrate()
4636 regmap_write(rt5665->regmap, RT5665_ASRC_8, 0x0120); in rt5665_calibrate()
4639 rt5665->calibration_done = true; in rt5665_calibrate()
4640 mutex_unlock(&rt5665->calibrate_mutex); in rt5665_calibrate()
4648 while (!snd_soc_card_is_instantiated(rt5665->component->card)) { in rt5665_calibrate_handler()
4658 struct rt5665_platform_data *pdata = dev_get_platdata(&i2c->dev); in rt5665_i2c_probe()
4663 rt5665 = devm_kzalloc(&i2c->dev, sizeof(struct rt5665_priv), in rt5665_i2c_probe()
4667 return -ENOMEM; in rt5665_i2c_probe()
4672 rt5665->pdata = *pdata; in rt5665_i2c_probe()
4674 rt5665_parse_dt(rt5665, &i2c->dev); in rt5665_i2c_probe()
4676 ret = devm_regulator_bulk_get_enable(&i2c->dev, ARRAY_SIZE(rt5665_supply_names), in rt5665_i2c_probe()
4679 dev_err(&i2c->dev, "Failed to request supplies: %d\n", ret); in rt5665_i2c_probe()
4683 rt5665->gpiod_ldo1_en = devm_gpiod_get_optional(&i2c->dev, in rt5665_i2c_probe()
4684 "realtek,ldo1-en", in rt5665_i2c_probe()
4686 if (IS_ERR(rt5665->gpiod_ldo1_en)) { in rt5665_i2c_probe()
4687 dev_err(&i2c->dev, "Failed gpio request ldo1_en\n"); in rt5665_i2c_probe()
4688 return PTR_ERR(rt5665->gpiod_ldo1_en); in rt5665_i2c_probe()
4694 rt5665->regmap = devm_regmap_init_i2c(i2c, &rt5665_regmap); in rt5665_i2c_probe()
4695 if (IS_ERR(rt5665->regmap)) { in rt5665_i2c_probe()
4696 ret = PTR_ERR(rt5665->regmap); in rt5665_i2c_probe()
4697 dev_err(&i2c->dev, "Failed to allocate register map: %d\n", in rt5665_i2c_probe()
4702 regmap_read(rt5665->regmap, RT5665_DEVICE_ID, &val); in rt5665_i2c_probe()
4704 dev_err(&i2c->dev, in rt5665_i2c_probe()
4706 return -ENODEV; in rt5665_i2c_probe()
4709 regmap_read(rt5665->regmap, RT5665_RESET, &val); in rt5665_i2c_probe()
4712 rt5665->id = CODEC_5666; in rt5665_i2c_probe()
4716 rt5665->id = CODEC_5665; in rt5665_i2c_probe()
4720 regmap_write(rt5665->regmap, RT5665_RESET, 0); in rt5665_i2c_probe()
4723 if (rt5665->pdata.in1_diff) in rt5665_i2c_probe()
4724 regmap_update_bits(rt5665->regmap, RT5665_IN1_IN2, in rt5665_i2c_probe()
4726 if (rt5665->pdata.in2_diff) in rt5665_i2c_probe()
4727 regmap_update_bits(rt5665->regmap, RT5665_IN1_IN2, in rt5665_i2c_probe()
4729 if (rt5665->pdata.in3_diff) in rt5665_i2c_probe()
4730 regmap_update_bits(rt5665->regmap, RT5665_IN3_IN4, in rt5665_i2c_probe()
4732 if (rt5665->pdata.in4_diff) in rt5665_i2c_probe()
4733 regmap_update_bits(rt5665->regmap, RT5665_IN3_IN4, in rt5665_i2c_probe()
4737 if (rt5665->pdata.dmic1_data_pin != RT5665_DMIC1_NULL || in rt5665_i2c_probe()
4738 rt5665->pdata.dmic2_data_pin != RT5665_DMIC2_NULL) { in rt5665_i2c_probe()
4739 regmap_update_bits(rt5665->regmap, RT5665_GPIO_CTRL_2, in rt5665_i2c_probe()
4741 regmap_update_bits(rt5665->regmap, RT5665_GPIO_CTRL_1, in rt5665_i2c_probe()
4743 switch (rt5665->pdata.dmic1_data_pin) { in rt5665_i2c_probe()
4745 regmap_update_bits(rt5665->regmap, RT5665_DMIC_CTRL_1, in rt5665_i2c_probe()
4750 regmap_update_bits(rt5665->regmap, RT5665_DMIC_CTRL_1, in rt5665_i2c_probe()
4752 regmap_update_bits(rt5665->regmap, RT5665_GPIO_CTRL_1, in rt5665_i2c_probe()
4757 dev_dbg(&i2c->dev, "no DMIC1\n"); in rt5665_i2c_probe()
4761 switch (rt5665->pdata.dmic2_data_pin) { in rt5665_i2c_probe()
4763 regmap_update_bits(rt5665->regmap, RT5665_DMIC_CTRL_1, in rt5665_i2c_probe()
4768 regmap_update_bits(rt5665->regmap, in rt5665_i2c_probe()
4772 regmap_update_bits(rt5665->regmap, RT5665_GPIO_CTRL_1, in rt5665_i2c_probe()
4777 dev_dbg(&i2c->dev, "no DMIC2\n"); in rt5665_i2c_probe()
4783 regmap_write(rt5665->regmap, RT5665_HP_LOGIC_CTRL_2, 0x0002); in rt5665_i2c_probe()
4784 regmap_update_bits(rt5665->regmap, RT5665_EJD_CTRL_1, in rt5665_i2c_probe()
4787 regmap_update_bits(rt5665->regmap, RT5665_STO1_DAC_SIL_DET, in rt5665_i2c_probe()
4790 regmap_update_bits(rt5665->regmap, RT5665_HP_CHARGE_PUMP_1, in rt5665_i2c_probe()
4794 if (rt5665->id == CODEC_5666) { in rt5665_i2c_probe()
4795 regmap_update_bits(rt5665->regmap, RT5665_GPIO_CTRL_2, in rt5665_i2c_probe()
4797 regmap_update_bits(rt5665->regmap, RT5665_GPIO_CTRL_3, in rt5665_i2c_probe()
4802 regmap_update_bits(rt5665->regmap, RT5665_PWR_ANLG_1, in rt5665_i2c_probe()
4806 INIT_DELAYED_WORK(&rt5665->jack_detect_work, in rt5665_i2c_probe()
4808 INIT_DELAYED_WORK(&rt5665->calibrate_work, in rt5665_i2c_probe()
4810 INIT_DELAYED_WORK(&rt5665->jd_check_work, in rt5665_i2c_probe()
4813 mutex_init(&rt5665->calibrate_mutex); in rt5665_i2c_probe()
4815 if (i2c->irq) { in rt5665_i2c_probe()
4816 ret = devm_request_threaded_irq(&i2c->dev, i2c->irq, NULL, in rt5665_i2c_probe()
4820 dev_err(&i2c->dev, "Failed to request IRQ: %d\n", ret); in rt5665_i2c_probe()
4824 return devm_snd_soc_register_component(&i2c->dev, in rt5665_i2c_probe()
4833 regmap_write(rt5665->regmap, RT5665_RESET, 0); in rt5665_i2c_shutdown()