Lines Matching +full:8 +full:- +full:15
1 /* SPDX-License-Identifier: GPL-2.0-only */
3 * rt5651.h -- RT5651 ALSA SoC audio driver
12 #include <dt-bindings/sound/rt5651.h>
19 /* I/O - Output */
23 /* I/O - Input */
28 /* I/O - ADC/DAC/DMIC */
35 /* Mixer - D-D */
48 /* Mixer - ADC */
53 /* Mixer - DAC */
72 /* Format - ADC/DAC */
82 /* Function - Analog */
99 /* Function - Digital */
176 #define RT5651_L_MUTE (0x1 << 15)
177 #define RT5651_L_MUTE_SFT 15
184 #define RT5651_L_VOL_MASK (0x3f << 8)
185 #define RT5651_L_VOL_SFT 8
190 #define RT5651_EN_DFO (0x1 << 15)
196 #define RT5651_BST_MASK2 (0xf<<8)
197 #define RT5651_BST_SFT2 8
205 #define RT5651_INL_SEL_MASK (0x1 << 15)
206 #define RT5651_INL_SEL_SFT 15
207 #define RT5651_INL_SEL_IN4P (0x0 << 15)
208 #define RT5651_INL_SEL_MONOP (0x1 << 15)
209 #define RT5651_INL_VOL_MASK (0x1f << 8)
210 #define RT5651_INL_VOL_SFT 8
219 #define RT5651_DAC_L1_VOL_MASK (0xff << 8)
220 #define RT5651_DAC_L1_VOL_SFT 8
225 #define RT5651_DAC_L2_VOL_MASK (0xff << 8)
226 #define RT5651_DAC_L2_VOL_SFT 8
245 #define RT5651_ADC_L_VOL_MASK (0x7f << 8)
246 #define RT5651_ADC_L_VOL_SFT 8
251 #define RT5651_M_MONO_ADC_L (0x1 << 15)
252 #define RT5651_M_MONO_ADC_L_SFT 15
253 #define RT5651_MONO_ADC_L_VOL_MASK (0x7f << 8)
254 #define RT5651_MONO_ADC_L_VOL_SFT 8
313 #define RT5651_M_ADCMIX_L (0x1 << 15)
314 #define RT5651_M_ADCMIX_L_SFT 15
333 #define RT5651_DAC_R1_STO_L_VOL_MASK (0x1 << 8)
334 #define RT5651_DAC_R1_STO_L_VOL_SFT 8
375 #define RT5651_M_STO_L_DAC_L (0x1 << 15)
376 #define RT5651_M_STO_L_DAC_L_SFT 15
389 #define RT5651_DAC_R2_DAC_R_VOL_MASK (0x1 << 8)
390 #define RT5651_DAC_R2_DAC_R_VOL_SFT 8
393 #define RT5651_RXDP_SRC_MASK (0x1 << 15)
394 #define RT5651_RXDP_SRC_SFT 15
395 #define RT5651_RXDP_SRC_NOR (0x0 << 15)
396 #define RT5651_RXDP_SRC_DIV3 (0x1 << 15)
422 #define RT5651_RXDC_SEL_MASK (0x3 << 8)
423 #define RT5651_RXDC_SEL_SFT 8
424 #define RT5651_RXDC_SEL_NOR (0x0 << 8)
425 #define RT5651_RXDC_SEL_L2R (0x1 << 8)
426 #define RT5651_RXDC_SEL_R2L (0x2 << 8)
427 #define RT5651_RXDC_SEL_SWAP (0x3 << 8)
454 #define RT5651_IF2_ADC_SEL_MASK (0x3 << 8)
455 #define RT5651_IF2_ADC_SEL_SFT 8
456 #define RT5651_IF2_ADC_SEL_NOR (0x0 << 8)
457 #define RT5651_IF2_ADC_SEL_SWAP (0x1 << 8)
458 #define RT5651_IF2_ADC_SEL_L2R (0x2 << 8)
459 #define RT5651_IF2_ADC_SEL_R2L (0x3 << 8)
466 #define RT5651_PDM_L_SEL_MASK (0x1 << 15)
467 #define RT5651_PDM_L_SEL_SFT 15
468 #define RT5651_PDM_L_SEL_DD_L (0x0 << 15)
469 #define RT5651_PDM_L_SEL_STO_L (0x1 << 15)
499 #define RT5651_PDM_I2C_NORMAL (0x0 << 8)
500 #define RT5651_PDM_I2C_BUSY (0x1 << 8)
503 #define RT5651_PDM_I2C_ADDR (0xff << 8)
578 #define RT5651_G_DAC_L2_SM_L_MASK (0x3 << 8)
579 #define RT5651_G_DAC_L2_SM_L_SFT 8
600 #define RT5651_G_DAC_R2_SM_R_MASK (0x3 << 8)
601 #define RT5651_G_DAC_R2_SM_R_SFT 8
616 #define RT5651_M_DAC_R1_SPM_L (0x1 << 15)
617 #define RT5651_M_DAC_R1_SPM_L_SFT 15
640 #define RT5651_M_DAC_R2_MM (0x1 << 15)
641 #define RT5651_M_DAC_R2_MM_SFT 15
714 #define RT5651_M_DAC_L1_LM (0x1 << 15)
715 #define RT5651_M_DAC_L1_LM_SFT 15
726 #define RT5651_PWR_I2S1 (0x1 << 15)
727 #define RT5651_PWR_I2S1_BIT 15
740 #define RT5651_PWR_ADC_STO1_F (0x1 << 15)
741 #define RT5651_PWR_ADC_STO1_F_BIT 15
752 #define RT5651_PWR_VREF1 (0x1 << 15)
753 #define RT5651_PWR_VREF1_BIT 15
781 #define RT5651_PWR_BST1 (0x1 << 15)
782 #define RT5651_PWR_BST1_BIT 15
805 #define RT5651_PWR_OM_L (0x1 << 15)
806 #define RT5651_PWR_OM_L_BIT 15
825 #define RT5651_PWR_IN1_R (0x1 << 8)
826 #define RT5651_PWR_IN1_R_BIT 8
833 #define RT5651_I2S_MS_MASK (0x1 << 15)
834 #define RT5651_I2S_MS_SFT 15
835 #define RT5651_I2S_MS_M (0x0 << 15)
836 #define RT5651_I2S_MS_S (0x1 << 15)
842 #define RT5651_I2S_I_CP_MASK (0x3 << 8)
843 #define RT5651_I2S_I_CP_SFT 8
844 #define RT5651_I2S_I_CP_OFF (0x0 << 8)
845 #define RT5651_I2S_I_CP_U_LAW (0x1 << 8)
846 #define RT5651_I2S_I_CP_A_LAW (0x2 << 8)
879 #define RT5651_I2S_PD2_MASK (0x7 << 8)
880 #define RT5651_I2S_PD2_SFT 8
881 #define RT5651_I2S_PD2_1 (0x0 << 8)
882 #define RT5651_I2S_PD2_2 (0x1 << 8)
883 #define RT5651_I2S_PD2_3 (0x2 << 8)
884 #define RT5651_I2S_PD2_4 (0x3 << 8)
885 #define RT5651_I2S_PD2_6 (0x4 << 8)
886 #define RT5651_I2S_PD2_8 (0x5 << 8)
887 #define RT5651_I2S_PD2_12 (0x6 << 8)
888 #define RT5651_I2S_PD2_16 (0x7 << 8)
909 #define RT5651_DMIC_1_EN_MASK (0x1 << 15)
910 #define RT5651_DMIC_1_EN_SFT 15
911 #define RT5651_DMIC_1_DIS (0x0 << 15)
912 #define RT5651_DMIC_1_EN (0x1 << 15)
930 #define RT5651_TDM_INTEL_SEL_MASK (0x1 << 15)
931 #define RT5651_TDM_INTEL_SEL_SFT 15
932 #define RT5651_TDM_INTEL_SEL_64 (0x0 << 15)
933 #define RT5651_TDM_INTEL_SEL_50 (0x1 << 15)
954 #define RT5651_TDM_ADC_START_SEL_MASK (0x1 << 8)
955 #define RT5651_TDM_ADC_START_SEL_SFT 8
956 #define RT5651_TDM_ADC_START_SEL_SL0 (0x0 << 8)
957 #define RT5651_TDM_ADC_START_SEL_SL4 (0x1 << 8)
984 #define RT5651_TDM_LRCK_POL_SEL_MASK (0x1 << 15)
985 #define RT5651_TDM_LRCK_POL_SEL_SFT 15
986 #define RT5651_TDM_LRCK_POL_SEL_NOR (0x0 << 15)
987 #define RT5651_TDM_LRCK_POL_SEL_INV (0x1 << 15)
1006 #define RT5651_TDM_TRAN_EDGE_SEL_MASK (0x1 << 8)
1007 #define RT5651_TDM_TRAN_EDGE_SEL_SFT 8
1008 #define RT5651_TDM_TRAN_EDGE_SEL_POS (0x0 << 8)
1009 #define RT5651_TDM_TRAN_EDGE_SEL_NEG (0x1 << 8)
1030 #define RT5651_CH2_R_SEL_MASK (0x7 << 8)
1031 #define RT5651_CH2_R_SEL_SFT 8
1032 #define RT5651_CH2_R_SEL_SL0 (0x0 << 8)
1033 #define RT5651_CH2_R_SEL_SL1 (0x1 << 8)
1034 #define RT5651_CH2_R_SEL_SL2 (0x2 << 8)
1035 #define RT5651_CH2_R_SEL_SL3 (0x3 << 8)
1036 #define RT5651_CH2_R_SEL_SL4 (0x4 << 8)
1037 #define RT5651_CH2_R_SEL_SL5 (0x5 << 8)
1038 #define RT5651_CH2_R_SEL_SL6 (0x6 << 8)
1039 #define RT5651_CH2_R_SEL_SL7 (0x7 << 8)
1095 #define RT5651_STO1_T_MASK (0x1 << 15)
1096 #define RT5651_STO1_T_SFT 15
1097 #define RT5651_STO1_T_SCLK (0x0 << 15)
1098 #define RT5651_STO1_T_LRCK1 (0x1 << 15)
1113 #define RT5651_STO1_ASRC_EN (0x1 << 15)
1114 #define RT5651_STO1_ASRC_EN_SFT 15
1146 #define RT5651_I2S2_RATE_MASK (0xf << 8)
1147 #define RT5651_I2S2_RATE_SFT 8
1164 #define RT5651_I2S2_PD_MASK (0x7 << 8)
1165 #define RT5651_I2S2_PD_SFT 8
1170 #define RT5651_FSI2_RATE_MASK (0xf << 8)
1171 #define RT5651_FSI2_RATE_SFT 8
1178 #define RT5651_HP_OC_TH_MASK (0x3 << 8)
1179 #define RT5651_HP_OC_TH_SFT 8
1180 #define RT5651_HP_OC_TH_90 (0x0 << 8)
1181 #define RT5651_HP_OC_TH_105 (0x1 << 8)
1182 #define RT5651_HP_OC_TH_120 (0x2 << 8)
1183 #define RT5651_HP_OC_TH_135 (0x3 << 8)
1186 #define RT5651_SMT_TRIG_MASK (0x1 << 15)
1187 #define RT5651_SMT_TRIG_SFT 15
1188 #define RT5651_SMT_TRIG_DIS (0x0 << 15)
1189 #define RT5651_SMT_TRIG_EN (0x1 << 15)
1194 #define RT5651_HP_R_SMT_MASK (0x1 << 8)
1195 #define RT5651_HP_R_SMT_SFT 8
1196 #define RT5651_HP_R_SMT_DIS (0x0 << 8)
1197 #define RT5651_HP_R_SMT_EN (0x1 << 8)
1248 #define RT5651_MRES_MASK (0x3 << 8)
1249 #define RT5651_MRES_SFT 8
1250 #define RT5651_MRES_15MO (0x0 << 8)
1251 #define RT5651_MRES_25MO (0x1 << 8)
1252 #define RT5651_MRES_35MO (0x2 << 8)
1253 #define RT5651_MRES_45MO (0x3 << 8)
1268 #define RT5651_CP_FQ1_MASK (0x7 << 8)
1269 #define RT5651_CP_FQ1_SFT 8
1292 #define RT5651_PM_HP_MASK (0x3 << 8)
1293 #define RT5651_PM_HP_SFT 8
1294 #define RT5651_PM_HP_LV (0x0 << 8)
1295 #define RT5651_PM_HP_MV (0x1 << 8)
1296 #define RT5651_PM_HP_HV (0x2 << 8)
1305 #define RT5651_MIC1_BS_MASK (0x1 << 15)
1306 #define RT5651_MIC1_BS_SFT 15
1307 #define RT5651_MIC1_BS_9AV (0x0 << 15)
1308 #define RT5651_MIC1_BS_75AV (0x1 << 15)
1338 #define RT5651_JD_MODE_SEL_MASK (0x3 << 8)
1339 #define RT5651_JD_MODE_SEL_SFT 8
1340 #define RT5651_JD_MODE_SEL_M0 (0x0 << 8)
1341 #define RT5651_JD_MODE_SEL_M1 (0x1 << 8)
1342 #define RT5651_JD_MODE_SEL_M2 (0x2 << 8)
1360 #define RT5651_EQ_SRC_MASK (0x1 << 15)
1361 #define RT5651_EQ_SRC_SFT 15
1362 #define RT5651_EQ_SRC_DAC (0x0 << 15)
1363 #define RT5651_EQ_SRC_ADC (0x1 << 15)
1370 #define RT5651_EQ_DITH_MASK (0x3 << 8)
1371 #define RT5651_EQ_DITH_SFT 8
1372 #define RT5651_EQ_DITH_NOR (0x0 << 8)
1373 #define RT5651_EQ_DITH_LSB (0x1 << 8)
1374 #define RT5651_EQ_DITH_LSB_1 (0x2 << 8)
1375 #define RT5651_EQ_DITH_LSB_2 (0x3 << 8)
1394 #define RT5651_EQ_HPF1_M_MASK (0x1 << 8)
1395 #define RT5651_EQ_HPF1_M_SFT 8
1396 #define RT5651_EQ_HPF1_M_HI (0x0 << 8)
1397 #define RT5651_EQ_HPF1_M_1ST (0x1 << 8)
1433 #define RT5651_MT_MASK (0x1 << 15)
1434 #define RT5651_MT_SFT 15
1435 #define RT5651_MT_DIS (0x0 << 15)
1436 #define RT5651_MT_EN (0x1 << 15)
1439 #define RT5651_ALC_P_MASK (0x1 << 15)
1440 #define RT5651_ALC_P_SFT 15
1441 #define RT5651_ALC_P_DAC (0x0 << 15)
1442 #define RT5651_ALC_P_ADC (0x1 << 15)
1449 #define RT5651_ALC_AR_MASK (0x1f << 8)
1450 #define RT5651_ALC_AR_SFT 8
1463 #define RT5651_ALC_POB_MASK (0x3f << 8)
1464 #define RT5651_ALC_POB_SFT 8
1516 #define RT5651_JD_SPL_TRG_MASK (0x1 << 8)
1517 #define RT5651_JD_SPL_TRG_SFT 8
1518 #define RT5651_JD_SPL_TRG_LO (0x0 << 8)
1519 #define RT5651_JD_SPL_TRG_HI (0x1 << 8)
1545 #define RT5651_JD3_IRQ_EN (0x1 << 8)
1546 #define RT5651_JD3_IRQ_EN_SFT 8
1553 #define RT5651_IRQ_JD_MASK (0x1 << 15)
1554 #define RT5651_IRQ_JD_SFT 15
1555 #define RT5651_IRQ_JD_BP (0x0 << 15)
1556 #define RT5651_IRQ_JD_NOR (0x1 << 15)
1567 #define RT5651_JD1_1_EN_STKY (0x1 << 8)
1568 #define RT5651_JD1_1_EN_STKY_SFT 8
1585 #define RT5651_IRQ_MB1_OC_MASK (0x1 << 15)
1586 #define RT5651_IRQ_MB1_OC_SFT 15
1587 #define RT5651_IRQ_MB1_OC_BP (0x0 << 15)
1588 #define RT5651_IRQ_MB1_OC_NOR (0x1 << 15)
1604 #define RT5651_STA_JD3 (0x1 << 15)
1605 #define RT5651_STA_JD3_BIT 15
1618 #define RT5651_STA_GP1 (0x1 << 8)
1619 #define RT5651_STA_GP1_BIT 8
1630 #define RT5651_GP1_PIN_MASK (0x1 << 15)
1631 #define RT5651_GP1_PIN_SFT 15
1632 #define RT5651_GP1_PIN_GPIO1 (0x0 << 15)
1633 #define RT5651_GP1_PIN_IRQ (0x1 << 15)
1642 #define RT5651_I2S2_SEL_MASK (0x1 << 8)
1643 #define RT5651_I2S2_SEL_SFT 8
1644 #define RT5651_I2S2_SEL_I2S (0x0 << 8)
1645 #define RT5651_I2S2_SEL_GPIO (0x1 << 8)
1692 #define RT5651_GP3_DR_MASK (0x1 << 8)
1693 #define RT5651_GP3_DR_SFT 8
1694 #define RT5651_GP3_DR_IN (0x0 << 8)
1695 #define RT5651_GP3_DR_OUT (0x1 << 8)
1730 #define RT5651_GP8_DR_MASK (0x1 << 8)
1731 #define RT5651_GP8_DR_SFT 8
1732 #define RT5651_GP8_DR_IN (0x0 << 8)
1733 #define RT5651_GP8_DR_OUT (0x1 << 8)
1768 #define RT5651_SCB_SWAP_MASK (0x1 << 15)
1769 #define RT5651_SCB_SWAP_SFT 15
1770 #define RT5651_SCB_SWAP_DIS (0x0 << 15)
1771 #define RT5651_SCB_SWAP_EN (0x1 << 15)
1778 #define RT5651_BB_MASK (0x1 << 15)
1779 #define RT5651_BB_SFT 15
1780 #define RT5651_BB_DIS (0x0 << 15)
1781 #define RT5651_BB_EN (0x1 << 15)
1790 #define RT5651_M_BB_R_MASK (0x1 << 8)
1791 #define RT5651_M_BB_R_SFT 8
1800 #define RT5651_M_MP3_L_MASK (0x1 << 15)
1801 #define RT5651_M_MP3_L_SFT 15
1808 #define RT5651_EG_MP3_MASK (0x1f << 8)
1809 #define RT5651_EG_MP3_SFT 8
1824 #define RT5651_OG_MP3_MASK (0x1f << 8)
1825 #define RT5651_OG_MP3_SFT 8
1830 #define RT5651_3D_CF_MASK (0x1 << 15)
1831 #define RT5651_3D_CF_SFT 15
1832 #define RT5651_3D_CF_DIS (0x0 << 15)
1833 #define RT5651_3D_CF_EN (0x1 << 15)
1850 #define RT5651_M_3D_D2H_MASK (0x1 << 8)
1851 #define RT5651_M_3D_D2H_SFT 8
1858 #define RT5651_2ND_HPF_MASK (0x1 << 15)
1859 #define RT5651_2ND_HPF_SFT 15
1860 #define RT5651_2ND_HPF_DIS (0x0 << 15)
1861 #define RT5651_2ND_HPF_EN (0x1 << 15)
1864 #define RT5651_HPF_CF_R_MASK (0x7 << 8)
1865 #define RT5651_HPF_CF_R_SFT 8
1876 #define RT5651_HPF_CF_L_NUM_MASK (0x3f << 8)
1877 #define RT5651_HPF_CF_L_NUM_SFT 8
1919 #define RT5651_SV_MASK (0x1 << 15)
1920 #define RT5651_SV_SFT 15
1921 #define RT5651_SV_DIS (0x0 << 15)
1922 #define RT5651_SV_EN (0x1 << 15)
1949 #define RT5651_ZCD_HP_MASK (0x1 << 15)
1950 #define RT5651_ZCD_HP_SFT 15
1951 #define RT5651_ZCD_HP_DIS (0x0 << 15)
1952 #define RT5651_ZCD_HP_EN (0x1 << 15)
1955 #define RT5651_I2S2_MS_SP_MASK (0x1 << 8)
1956 #define RT5651_I2S2_MS_SP_SEL 8
1957 #define RT5651_I2S2_MS_SP_64 (0x0 << 8)
1958 #define RT5651_I2S2_MS_SP_50 (0x1 << 8)
1969 #define RT5651_MIC_OVCD_SF_MASK (0x3 << 8)
1970 #define RT5651_MIC_OVCD_SF_SFT 8
1971 #define RT5651_MIC_OVCD_SF_0P5 (0x0 << 8)
1972 #define RT5651_MIC_OVCD_SF_0P75 (0x1 << 8)
1973 #define RT5651_MIC_OVCD_SF_1P0 (0x2 << 8)
1974 #define RT5651_MIC_OVCD_SF_1P5 (0x3 << 8)
1977 #define RT5651_3D_SPK_MASK (0x1 << 15)
1978 #define RT5651_3D_SPK_SFT 15
1979 #define RT5651_3D_SPK_DIS (0x0 << 15)
1980 #define RT5651_3D_SPK_EN (0x1 << 15)
1983 #define RT5651_3D_SPK_CG_MASK (0x1f << 8)
1984 #define RT5651_3D_SPK_CG_SFT 8
1989 #define RT5651_WND_MASK (0x1 << 15)
1990 #define RT5651_WND_SFT 15
1991 #define RT5651_WND_DIS (0x0 << 15)
1992 #define RT5651_WND_EN (0x1 << 15)
2014 /* Wind Noise Detection Control 8 (0x73) */
2015 #define RT5651_WND_WIND_MASK (0x1 << 13) /* Read-Only */
2017 #define RT5651_WND_STRONG_MASK (0x1 << 12) /* Read-Only */