Lines Matching +full:8 +full:- +full:15
1 /* SPDX-License-Identifier: GPL-2.0-only */
3 * rt5645.h -- RT5645 ALSA SoC audio driver
17 /* I/O - Output */
22 /* I/O - Input */
30 /* I/O - ADC/DAC/DMIC */
38 /* Mixer - D-D */
47 /* Mixer - PDM */
49 /* Mixer - ADC */
54 /* Mixer - DAC */
92 /* Format - ADC/DAC */
99 /* Format - TDM Control */
105 /* Function - Analog */
121 /* Function - Digital */
217 #define RT5645_L_MUTE (0x1 << 15)
218 #define RT5645_L_MUTE_SFT 15
225 #define RT5645_L_VOL_MASK (0x3f << 8)
226 #define RT5645_L_VOL_SFT 8
234 #define RT5645_CBJ_JD_MIC_EN (0x1 << 8)
247 #define RT5645_CBJ_TIE_G_L (0x1 << 15)
253 #define RT5645_BST_MASK2 (0xf<<8)
254 #define RT5645_BST_SFT2 8
259 #define RT5645_INL_SEL_MASK (0x1 << 15)
260 #define RT5645_INL_SEL_SFT 15
261 #define RT5645_INL_SEL_IN4P (0x0 << 15)
262 #define RT5645_INL_SEL_MONOP (0x1 << 15)
263 #define RT5645_INL_VOL_MASK (0x1f << 8)
264 #define RT5645_INL_VOL_SFT 8
273 #define RT5645_DAC_L1_VOL_MASK (0xff << 8)
274 #define RT5645_DAC_L1_VOL_SFT 8
279 #define RT5645_DAC_L2_VOL_MASK (0xff << 8)
280 #define RT5645_DAC_L2_VOL_SFT 8
295 #define RT5645_ADC_L_VOL_MASK (0x7f << 8)
296 #define RT5645_ADC_L_VOL_SFT 8
301 #define RT5645_MONO_ADC_L_VOL_MASK (0x7f << 8)
302 #define RT5645_MONO_ADC_L_VOL_SFT 8
323 #define RT5645_STO2_ADC_SRC_MASK (0x1 << 15)
324 #define RT5645_STO2_ADC_SRC_SFT 15
337 #define RT5645_DMIC_SRC_MASK (0x1 << 8)
338 #define RT5645_DMIC_SRC_SFT 8
357 #define RT5645_MONO_DMIC_L_SRC_MASK (0x1 << 8)
358 #define RT5645_MONO_DMIC_L_SRC_SFT 8
373 #define RT5645_M_ADCMIX_L (0x1 << 15)
374 #define RT5645_M_ADCMIX_L_SFT 15
383 #define RT5645_DAC1_L_SEL_MASK (0x3 << 8)
384 #define RT5645_DAC1_L_SEL_SFT 8
385 #define RT5645_DAC1_L_SEL_IF1 (0x0 << 8)
386 #define RT5645_DAC1_L_SEL_IF2 (0x1 << 8)
387 #define RT5645_DAC1_L_SEL_IF3 (0x2 << 8)
388 #define RT5645_DAC1_L_SEL_IF4 (0x3 << 8)
407 #define RT5645_DAC_R1_STO_L_VOL_MASK (0x1 << 8)
408 #define RT5645_DAC_R1_STO_L_VOL_SFT 8
451 #define RT5645_M_STO_L_DAC_L (0x1 << 15)
452 #define RT5645_M_STO_L_DAC_L_SFT 15
465 #define RT5645_DAC_R2_DAC_R_VOL_MASK (0x1 << 8)
466 #define RT5645_DAC_R2_DAC_R_VOL_SFT 8
483 #define RT5645_IF1_ADC2_IN_SEL (0x1 << 15)
484 #define RT5645_IF1_ADC2_IN_SFT 15
489 #define RT5645_IF2_ADC_SEL_MASK (0x3 << 8)
490 #define RT5645_IF2_ADC_SEL_SFT 8
499 #define RT5645_PDM1_L_MASK (0x1 << 15)
500 #define RT5645_PDM1_L_SFT 15
513 #define RT5645_M_PDM2_R (0x1 << 8)
514 #define RT5645_M_PDM2_R_SFT 8
613 #define RT5645_G_DAC_L2_SM_L_MASK (0x3 << 8)
614 #define RT5645_G_DAC_L2_SM_L_SFT 8
635 #define RT5645_G_DAC_R2_SM_R_MASK (0x3 << 8)
636 #define RT5645_G_DAC_R2_SM_R_SFT 8
651 #define RT5645_M_DAC_L1_SPM_L (0x1 << 15)
652 #define RT5645_M_DAC_L1_SPM_L_SFT 15
677 #define RT5645_M_DAC_L2_MA (0x1 << 8)
678 #define RT5645_M_DAC_L2_MA_SFT 8
755 #define RT5645_M_DAC_L1_LM (0x1 << 15)
756 #define RT5645_M_DAC_L1_LM_SFT 15
767 #define RT5645_PWR_I2S1 (0x1 << 15)
768 #define RT5645_PWR_I2S1_BIT 15
779 #define RT5645_PWR_CLS_D_L (0x1 << 8)
780 #define RT5645_PWR_CLS_D_L_BIT 8
793 #define RT5645_PWR_ADC_S1F (0x1 << 15)
794 #define RT5645_PWR_ADC_S1F_BIT 15
817 #define RT5645_PWR_VREF1 (0x1 << 15)
818 #define RT5645_PWR_VREF1_BIT 15
843 #define RT5645_PWR_BST1 (0x1 << 15)
844 #define RT5645_PWR_BST1_BIT 15
869 #define RT5645_PWR_OM_L (0x1 << 15)
870 #define RT5645_PWR_OM_L_BIT 15
881 #define RT5645_PWR_MM (0x1 << 8)
882 #define RT5645_PWR_MM_BIT 8
891 #define RT5645_PWR_SV_L (0x1 << 15)
892 #define RT5645_PWR_SV_L_BIT 15
901 #define RT5645_PWR_IN_R (0x1 << 8)
902 #define RT5645_PWR_IN_R_BIT 8
907 #define RT5645_I2S_MS_MASK (0x1 << 15)
908 #define RT5645_I2S_MS_SFT 15
909 #define RT5645_I2S_MS_M (0x0 << 15)
910 #define RT5645_I2S_MS_S (0x1 << 15)
916 #define RT5645_I2S_I_CP_MASK (0x3 << 8)
917 #define RT5645_I2S_I_CP_SFT 8
918 #define RT5645_I2S_I_CP_OFF (0x0 << 8)
919 #define RT5645_I2S_I_CP_U_LAW (0x1 << 8)
920 #define RT5645_I2S_I_CP_A_LAW (0x2 << 8)
959 #define RT5645_I2S_PD2_MASK (0x7 << 8)
960 #define RT5645_I2S_PD2_SFT 8
961 #define RT5645_I2S_PD2_1 (0x0 << 8)
962 #define RT5645_I2S_PD2_2 (0x1 << 8)
963 #define RT5645_I2S_PD2_3 (0x2 << 8)
964 #define RT5645_I2S_PD2_4 (0x3 << 8)
965 #define RT5645_I2S_PD2_6 (0x4 << 8)
966 #define RT5645_I2S_PD2_8 (0x5 << 8)
967 #define RT5645_I2S_PD2_12 (0x6 << 8)
968 #define RT5645_I2S_PD2_16 (0x7 << 8)
1015 #define RT5645_DMIC_1_EN_MASK (0x1 << 15)
1016 #define RT5645_DMIC_1_EN_SFT 15
1017 #define RT5645_DMIC_1_DIS (0x0 << 15)
1018 #define RT5645_DMIC_1_EN (0x1 << 15)
1041 #define RT5645_DMIC_2R_LH_MASK (0x1 << 8)
1042 #define RT5645_DMIC_2R_LH_SFT 8
1043 #define RT5645_DMIC_2R_LH_FALLING (0x0 << 8)
1044 #define RT5645_DMIC_2R_LH_RISING (0x1 << 8)
1058 #define RT5645_IF1_ADC_IN_MASK (0x3 << 8)
1059 #define RT5645_IF1_ADC_IN_SFT 8
1097 #define RT5645_STO_T_MASK (0x1 << 15)
1098 #define RT5645_STO_T_SFT 15
1099 #define RT5645_STO_T_SCLK (0x0 << 15)
1100 #define RT5645_STO_T_LRCK1 (0x1 << 15)
1113 #define RT5645_DMIC_2_M_MASK (0x1 << 8)
1114 #define RT5645_DMIC_2_M_SFT 8
1115 #define RT5645_DMIC_2_M_NOR (0x0 << 8)
1116 #define RT5645_DMIC_2_M_ASYN (0x1 << 8)
1127 #define RT5645_DA_MONOL_CLK_SEL_MASK (0xf << 8)
1128 #define RT5645_DA_MONOL_CLK_SEL_SFT 8
1143 #define RT5645_I2S2_PD_MASK (0x7 << 8)
1144 #define RT5645_I2S2_PD_SFT 8
1151 #define RT5645_HP_OC_TH_MASK (0x3 << 8)
1152 #define RT5645_HP_OC_TH_SFT 8
1153 #define RT5645_HP_OC_TH_90 (0x0 << 8)
1154 #define RT5645_HP_OC_TH_105 (0x1 << 8)
1155 #define RT5645_HP_OC_TH_120 (0x2 << 8)
1156 #define RT5645_HP_OC_TH_135 (0x3 << 8)
1163 #define RT5645_AUTO_PD_MASK (0x1 << 8)
1164 #define RT5645_AUTO_PD_SFT 8
1165 #define RT5645_AUTO_PD_DIS (0x0 << 8)
1166 #define RT5645_AUTO_PD_EN (0x1 << 8)
1183 #define RT5645_SMT_TRIG_MASK (0x1 << 15)
1184 #define RT5645_SMT_TRIG_SFT 15
1185 #define RT5645_SMT_TRIG_DIS (0x0 << 15)
1186 #define RT5645_SMT_TRIG_EN (0x1 << 15)
1191 #define RT5645_HP_R_SMT_MASK (0x1 << 8)
1192 #define RT5645_HP_R_SMT_SFT 8
1193 #define RT5645_HP_R_SMT_DIS (0x0 << 8)
1194 #define RT5645_HP_R_SMT_EN (0x1 << 8)
1245 #define RT5645_MRES_MASK (0x3 << 8)
1246 #define RT5645_MRES_SFT 8
1247 #define RT5645_MRES_15MO (0x0 << 8)
1248 #define RT5645_MRES_25MO (0x1 << 8)
1249 #define RT5645_MRES_35MO (0x2 << 8)
1250 #define RT5645_MRES_45MO (0x3 << 8)
1265 #define RT5645_CP_FQ1_MASK (0x7 << 8)
1266 #define RT5645_CP_FQ1_SFT 8
1281 #define RT5645_PVDD_DET_MASK (0x1 << 15)
1282 #define RT5645_PVDD_DET_SFT 15
1283 #define RT5645_PVDD_DET_DIS (0x0 << 15)
1284 #define RT5645_PVDD_DET_EN (0x1 << 15)
1291 #define RT5645_MIC1_BS_MASK (0x1 << 15)
1292 #define RT5645_MIC1_BS_SFT 15
1293 #define RT5645_MIC1_BS_9AV (0x0 << 15)
1294 #define RT5645_MIC1_BS_75AV (0x1 << 15)
1316 #define RT5645_MIC2_OVCD_MASK (0x1 << 8)
1317 #define RT5645_MIC2_OVCD_SFT 8
1318 #define RT5645_MIC2_OVCD_DIS (0x0 << 8)
1319 #define RT5645_MIC2_OVCD_EN (0x1 << 8)
1341 #define RT5645_VAD_SEL_MASK (0x3 << 8)
1342 #define RT5645_VAD_SEL_SFT 8
1345 #define RT5645_EQ_SRC_MASK (0x1 << 15)
1346 #define RT5645_EQ_SRC_SFT 15
1347 #define RT5645_EQ_SRC_DAC (0x0 << 15)
1348 #define RT5645_EQ_SRC_ADC (0x1 << 15)
1355 #define RT5645_EQ_DITH_MASK (0x3 << 8)
1356 #define RT5645_EQ_DITH_SFT 8
1357 #define RT5645_EQ_DITH_NOR (0x0 << 8)
1358 #define RT5645_EQ_DITH_LSB (0x1 << 8)
1359 #define RT5645_EQ_DITH_LSB_1 (0x2 << 8)
1360 #define RT5645_EQ_DITH_LSB_2 (0x3 << 8)
1363 #define RT5645_EQ_HPF1_M_MASK (0x1 << 8)
1364 #define RT5645_EQ_HPF1_M_SFT 8
1365 #define RT5645_EQ_HPF1_M_HI (0x0 << 8)
1366 #define RT5645_EQ_HPF1_M_1ST (0x1 << 8)
1402 #define RT5645_MT_MASK (0x1 << 15)
1403 #define RT5645_MT_SFT 15
1404 #define RT5645_MT_DIS (0x0 << 15)
1405 #define RT5645_MT_EN (0x1 << 15)
1408 #define RT5645_DRC_AGC_P_MASK (0x1 << 15)
1409 #define RT5645_DRC_AGC_P_SFT 15
1410 #define RT5645_DRC_AGC_P_DAC (0x0 << 15)
1411 #define RT5645_DRC_AGC_P_ADC (0x1 << 15)
1418 #define RT5645_DRC_AGC_AR_MASK (0x1f << 8)
1419 #define RT5645_DRC_AGC_AR_SFT 8
1432 #define RT5645_DRC_AGC_POB_MASK (0x3f << 8)
1433 #define RT5645_DRC_AGC_POB_SFT 8
1464 #define RT5645_ANC_M_MASK (0x1 << 15)
1465 #define RT5645_ANC_M_SFT 15
1466 #define RT5645_ANC_M_NOR (0x0 << 15)
1467 #define RT5645_ANC_M_REV (0x1 << 15)
1486 #define RT5645_ANC_ZCD_MASK (0x3 << 8)
1487 #define RT5645_ANC_ZCD_SFT 8
1488 #define RT5645_ANC_ZCD_DIS (0x0 << 8)
1489 #define RT5645_ANC_ZCD_T1 (0x1 << 8)
1490 #define RT5645_ANC_ZCD_T2 (0x2 << 8)
1491 #define RT5645_ANC_ZCD_WT (0x3 << 8)
1506 #define RT5645_ANC_FG_L_MASK (0xf << 8)
1507 #define RT5645_ANC_FG_L_SFT 8
1543 #define RT5645_JD_SPL_TRG_MASK (0x1 << 8)
1544 #define RT5645_JD_SPL_TRG_SFT 8
1545 #define RT5645_JD_SPL_TRG_LO (0x0 << 8)
1546 #define RT5645_JD_SPL_TRG_HI (0x1 << 8)
1603 #define RT5645_IRQ_JD_MASK (0x1 << 15)
1604 #define RT5645_IRQ_JD_SFT 15
1605 #define RT5645_IRQ_JD_BP (0x0 << 15)
1606 #define RT5645_IRQ_JD_NOR (0x1 << 15)
1634 #define RT5645_IRQ_MB1_OC_MASK (0x1 << 15)
1635 #define RT5645_IRQ_MB1_OC_SFT 15
1636 #define RT5645_IRQ_MB1_OC_BP (0x0 << 15)
1637 #define RT5645_IRQ_MB1_OC_NOR (0x1 << 15)
1664 #define RT5645_GP1_PIN_MASK (0x1 << 15)
1665 #define RT5645_GP1_PIN_SFT 15
1666 #define RT5645_GP1_PIN_GPIO1 (0x0 << 15)
1667 #define RT5645_GP1_PIN_IRQ (0x1 << 15)
1689 #define RT5645_I2S2_SEL (0x1 << 8)
1690 #define RT5645_I2S2_SEL_SFT 8
1733 #define RT5645_GP3_PF_MASK (0x1 << 8)
1734 #define RT5645_GP3_PF_SFT 8
1735 #define RT5645_GP3_PF_IN (0x0 << 8)
1736 #define RT5645_GP3_PF_OUT (0x1 << 8)
1785 #define RT5645_SEQ_2_PT_MASK (0x1 << 8)
1786 #define RT5645_SEQ_2_PT_BIT 8
1795 #define RT5645_SEQ_DLY_MASK (0xff << 8)
1796 #define RT5645_SEQ_DLY_SFT 8
1807 #define RT5645_SEQ1_START_MASK (0xf << 8)
1808 #define RT5645_SEQ1_START_SFT 8
1813 #define RT5645_SEQ2_START_MASK (0xf << 8)
1814 #define RT5645_SEQ2_START_SFT 8
1823 #define RT5645_SCB_SWAP_MASK (0x1 << 15)
1824 #define RT5645_SCB_SWAP_SFT 15
1825 #define RT5645_SCB_SWAP_DIS (0x0 << 15)
1826 #define RT5645_SCB_SWAP_EN (0x1 << 15)
1833 #define RT5645_BB_MASK (0x1 << 15)
1834 #define RT5645_BB_SFT 15
1835 #define RT5645_BB_DIS (0x0 << 15)
1836 #define RT5645_BB_EN (0x1 << 15)
1845 #define RT5645_M_BB_R_MASK (0x1 << 8)
1846 #define RT5645_M_BB_R_SFT 8
1856 #define RT5645_M_MP3_L_MASK (0x1 << 15)
1857 #define RT5645_M_MP3_L_SFT 15
1864 #define RT5645_EG_MP3_MASK (0x1f << 8)
1865 #define RT5645_EG_MP3_SFT 8
1880 #define RT5645_OG_MP3_MASK (0x1f << 8)
1881 #define RT5645_OG_MP3_SFT 8
1886 #define RT5645_3D_CF_MASK (0x1 << 15)
1887 #define RT5645_3D_CF_SFT 15
1888 #define RT5645_3D_CF_DIS (0x0 << 15)
1889 #define RT5645_3D_CF_EN (0x1 << 15)
1906 #define RT5645_M_3D_D2H_MASK (0x1 << 8)
1907 #define RT5645_M_3D_D2H_SFT 8
1914 #define RT5645_2ND_HPF_MASK (0x1 << 15)
1915 #define RT5645_2ND_HPF_SFT 15
1916 #define RT5645_2ND_HPF_DIS (0x0 << 15)
1917 #define RT5645_2ND_HPF_EN (0x1 << 15)
1924 #define RT5645_HPF_CF_R_MASK (0x7 << 8)
1925 #define RT5645_HPF_CF_R_SFT 8
1973 #define RT5645_SV_MASK (0x1 << 15)
1974 #define RT5645_SV_SFT 15
1975 #define RT5645_SV_DIS (0x0 << 15)
1976 #define RT5645_SV_EN (0x1 << 15)
2000 #define RT5645_M_ZCD_RM_R (0x1 << 8)
2009 #define RT5645_ZCD_HP_MASK (0x1 << 15)
2010 #define RT5645_ZCD_HP_SFT 15
2011 #define RT5645_ZCD_HP_DIS (0x0 << 15)
2012 #define RT5645_ZCD_HP_EN (0x1 << 15)
2015 #define RT5645_EN_4BTN_IL_MASK (0x1 << 15)
2016 #define RT5645_EN_4BTN_IL_EN (0x1 << 15)
2026 #define RT5645_3D_SPK_MASK (0x1 << 15)
2027 #define RT5645_3D_SPK_SFT 15
2028 #define RT5645_3D_SPK_DIS (0x0 << 15)
2029 #define RT5645_3D_SPK_EN (0x1 << 15)
2032 #define RT5645_3D_SPK_CG_MASK (0x1f << 8)
2033 #define RT5645_3D_SPK_CG_SFT 8
2038 #define RT5645_WND_MASK (0x1 << 15)
2039 #define RT5645_WND_SFT 15
2040 #define RT5645_WND_DIS (0x0 << 15)
2041 #define RT5645_WND_EN (0x1 << 15)
2063 /* Wind Noise Detection Control 8 (0x73) */
2064 #define RT5645_WND_WIND_MASK (0x1 << 13) /* Read-Only */
2066 #define RT5645_WND_STRONG_MASK (0x1 << 12) /* Read-Only */