Lines Matching +full:8 +full:- +full:15
1 /* SPDX-License-Identifier: GPL-2.0-only */
3 * rt5640.h -- RT5640 ALSA SoC audio driver
15 #include <dt-bindings/sound/rt5640.h>
22 /* I/O - Output */
27 /* I/O - Input */
31 /* I/O - ADC/DAC/DMIC */
38 /* Mixer - D-D */
48 /* Mixer - ADC */
53 /* Mixer - DAC */
78 /* Format - ADC/DAC */
84 /* Function - Analog */
102 /* Function - Digital */
183 #define RT5640_L_MUTE (0x1 << 15)
184 #define RT5640_L_MUTE_SFT 15
191 #define RT5640_L_VOL_MASK (0x3f << 8)
192 #define RT5640_L_VOL_SFT 8
206 #define RT5640_BST_SFT2 8
213 #define RT5640_INL_SEL_MASK (0x1 << 15)
214 #define RT5640_INL_SEL_SFT 15
215 #define RT5640_INL_SEL_IN4P (0x0 << 15)
216 #define RT5640_INL_SEL_MONOP (0x1 << 15)
217 #define RT5640_INL_VOL_MASK (0x1f << 8)
218 #define RT5640_INL_VOL_SFT 8
227 #define RT5640_DAC_L1_VOL_MASK (0xff << 8)
228 #define RT5640_DAC_L1_VOL_SFT 8
233 #define RT5640_DAC_L2_VOL_MASK (0xff << 8)
234 #define RT5640_DAC_L2_VOL_SFT 8
245 #define RT5640_ADC_L_VOL_MASK (0x7f << 8)
246 #define RT5640_ADC_L_VOL_SFT 8
251 #define RT5640_MONO_ADC_L_VOL_MASK (0x7f << 8)
252 #define RT5640_MONO_ADC_L_VOL_SFT 8
312 #define RT5640_M_ADCMIX_L (0x1 << 15)
313 #define RT5640_M_ADCMIX_L_SFT 15
370 #define RT5640_M_STO_L_DAC_L (0x1 << 15)
371 #define RT5640_M_STO_L_DAC_L_SFT 15
384 #define RT5640_DAC_R2_DAC_R_VOL_MASK (0x1 << 8)
385 #define RT5640_DAC_R2_DAC_R_VOL_SFT 8
388 #define RT5640_RXDP_SRC_MASK (0x1 << 15)
389 #define RT5640_RXDP_SRC_SFT 15
390 #define RT5640_RXDP_SRC_NOR (0x0 << 15)
391 #define RT5640_RXDP_SRC_DIV3 (0x1 << 15)
417 #define RT5640_RXDC_SEL_MASK (0x3 << 8)
418 #define RT5640_RXDC_SEL_SFT 8
419 #define RT5640_RXDC_SEL_NOR (0x0 << 8)
420 #define RT5640_RXDC_SEL_L2R (0x1 << 8)
421 #define RT5640_RXDC_SEL_R2L (0x2 << 8)
422 #define RT5640_RXDC_SEL_SWAP (0x3 << 8)
461 #define RT5640_IF2_ADC_SEL_MASK (0x3 << 8)
462 #define RT5640_IF2_ADC_SEL_SFT 8
463 #define RT5640_IF2_ADC_SEL_NOR (0x0 << 8)
464 #define RT5640_IF2_ADC_SEL_SWAP (0x1 << 8)
465 #define RT5640_IF2_ADC_SEL_L2R (0x2 << 8)
466 #define RT5640_IF2_ADC_SEL_R2L (0x3 << 8)
545 #define RT5640_M_DAC2_HM (0x1 << 15)
546 #define RT5640_M_DAC2_HM_SFT 15
561 #define RT5640_G_DAC_L2_SM_L_MASK (0x3 << 8)
562 #define RT5640_G_DAC_L2_SM_L_SFT 8
583 #define RT5640_G_DAC_R2_SM_R_MASK (0x3 << 8)
584 #define RT5640_G_DAC_R2_SM_R_SFT 8
599 #define RT5640_M_DAC_R1_SPM_L (0x1 << 15)
600 #define RT5640_M_DAC_R1_SPM_L_SFT 15
623 #define RT5640_M_DAC_R2_MM (0x1 << 15)
624 #define RT5640_M_DAC_R2_MM_SFT 15
657 #define RT5640_M_SM_L_OM_L (0x1 << 8)
658 #define RT5640_M_SM_L_OM_L_SFT 8
697 #define RT5640_M_SM_L_OM_R (0x1 << 8)
698 #define RT5640_M_SM_L_OM_R_SFT 8
717 #define RT5640_M_DAC_L1_LM (0x1 << 15)
718 #define RT5640_M_DAC_L1_LM_SFT 15
729 #define RT5640_PWR_I2S1 (0x1 << 15)
730 #define RT5640_PWR_I2S1_BIT 15
749 #define RT5640_PWR_ADC_SF (0x1 << 15)
750 #define RT5640_PWR_ADC_SF_BIT 15
759 #define RT5640_PWR_VREF1 (0x1 << 15)
760 #define RT5640_PWR_VREF1_BIT 15
771 #define RT5640_PWR_MA (0x1 << 8)
772 #define RT5640_PWR_MA_BIT 8
787 #define RT5640_PWR_BST1 (0x1 << 15)
788 #define RT5640_PWR_BST1_BIT 15
801 #define RT5640_PWR_OM_L (0x1 << 15)
802 #define RT5640_PWR_OM_L_BIT 15
815 #define RT5640_PWR_SV_L (0x1 << 15)
816 #define RT5640_PWR_SV_L_BIT 15
829 #define RT5640_PWR_IN_R (0x1 << 8)
830 #define RT5640_PWR_IN_R_BIT 8
833 #define RT5640_I2S_MS_MASK (0x1 << 15)
834 #define RT5640_I2S_MS_SFT 15
835 #define RT5640_I2S_MS_M (0x0 << 15)
836 #define RT5640_I2S_MS_S (0x1 << 15)
844 #define RT5640_I2S_I_CP_MASK (0x3 << 8)
845 #define RT5640_I2S_I_CP_SFT 8
846 #define RT5640_I2S_I_CP_OFF (0x0 << 8)
847 #define RT5640_I2S_I_CP_U_LAW (0x1 << 8)
848 #define RT5640_I2S_I_CP_A_LAW (0x2 << 8)
873 #define RT5640_I2S_BCLK_MS1_MASK (0x1 << 15)
874 #define RT5640_I2S_BCLK_MS1_SFT 15
875 #define RT5640_I2S_BCLK_MS1_32 (0x0 << 15)
876 #define RT5640_I2S_BCLK_MS1_64 (0x1 << 15)
891 #define RT5640_I2S_PD2_MASK (0x7 << 8)
892 #define RT5640_I2S_PD2_SFT 8
893 #define RT5640_I2S_PD2_1 (0x0 << 8)
894 #define RT5640_I2S_PD2_2 (0x1 << 8)
895 #define RT5640_I2S_PD2_3 (0x2 << 8)
896 #define RT5640_I2S_PD2_4 (0x3 << 8)
897 #define RT5640_I2S_PD2_6 (0x4 << 8)
898 #define RT5640_I2S_PD2_8 (0x5 << 8)
899 #define RT5640_I2S_PD2_12 (0x6 << 8)
900 #define RT5640_I2S_PD2_16 (0x7 << 8)
947 #define RT5640_DMIC_1_EN_MASK (0x1 << 15)
948 #define RT5640_DMIC_1_EN_SFT 15
949 #define RT5640_DMIC_1_DIS (0x0 << 15)
950 #define RT5640_DMIC_1_EN (0x1 << 15)
975 #define RT5640_DMIC_2R_LH_MASK (0x1 << 8)
976 #define RT5640_DMIC_2R_LH_SFT 8
977 #define RT5640_DMIC_2R_LH_FALLING (0x0 << 8)
978 #define RT5640_DMIC_2R_LH_RISING (0x1 << 8)
1017 #define RT5640_STO_T_MASK (0x1 << 15)
1018 #define RT5640_STO_T_SFT 15
1019 #define RT5640_STO_T_SCLK (0x0 << 15)
1020 #define RT5640_STO_T_LRCK1 (0x1 << 15)
1033 #define RT5640_DMIC_2_M_MASK (0x1 << 8)
1034 #define RT5640_DMIC_2_M_SFT 8
1035 #define RT5640_DMIC_2_M_NOR (0x0 << 8)
1036 #define RT5640_DMIC_2_M_ASYN (0x1 << 8)
1043 #define RT5640_MDA_L_M_MASK (0x1 << 15)
1044 #define RT5640_MDA_L_M_SFT 15
1045 #define RT5640_MDA_L_M_NOR (0x0 << 15)
1046 #define RT5640_MDA_L_M_ASYN (0x1 << 15)
1084 #define RT5640_I2S2_RATE_MASK (0xf << 8)
1085 #define RT5640_I2S2_RATE_SFT 8
1090 #define RT5640_I2S2_PD_MASK (0x7 << 8)
1091 #define RT5640_I2S2_PD_SFT 8
1098 #define RT5640_HP_OC_TH_MASK (0x3 << 8)
1099 #define RT5640_HP_OC_TH_SFT 8
1100 #define RT5640_HP_OC_TH_90 (0x0 << 8)
1101 #define RT5640_HP_OC_TH_105 (0x1 << 8)
1102 #define RT5640_HP_OC_TH_120 (0x2 << 8)
1103 #define RT5640_HP_OC_TH_135 (0x3 << 8)
1110 #define RT5640_AUTO_PD_MASK (0x1 << 8)
1111 #define RT5640_AUTO_PD_SFT 8
1112 #define RT5640_AUTO_PD_DIS (0x0 << 8)
1113 #define RT5640_AUTO_PD_EN (0x1 << 8)
1130 #define RT5640_SMT_TRIG_MASK (0x1 << 15)
1131 #define RT5640_SMT_TRIG_SFT 15
1132 #define RT5640_SMT_TRIG_DIS (0x0 << 15)
1133 #define RT5640_SMT_TRIG_EN (0x1 << 15)
1138 #define RT5640_HP_R_SMT_MASK (0x1 << 8)
1139 #define RT5640_HP_R_SMT_SFT 8
1140 #define RT5640_HP_R_SMT_DIS (0x0 << 8)
1141 #define RT5640_HP_R_SMT_EN (0x1 << 8)
1192 #define RT5640_MRES_MASK (0x3 << 8)
1193 #define RT5640_MRES_SFT 8
1194 #define RT5640_MRES_15MO (0x0 << 8)
1195 #define RT5640_MRES_25MO (0x1 << 8)
1196 #define RT5640_MRES_35MO (0x2 << 8)
1197 #define RT5640_MRES_45MO (0x3 << 8)
1212 #define RT5640_CP_FQ1_MASK (0x7 << 8)
1213 #define RT5640_CP_FQ1_SFT 8
1236 #define RT5640_PM_HP_MASK (0x3 << 8)
1237 #define RT5640_PM_HP_SFT 8
1238 #define RT5640_PM_HP_LV (0x0 << 8)
1239 #define RT5640_PM_HP_MV (0x1 << 8)
1240 #define RT5640_PM_HP_HV (0x2 << 8)
1249 #define RT5640_PVDD_DET_MASK (0x1 << 15)
1250 #define RT5640_PVDD_DET_SFT 15
1251 #define RT5640_PVDD_DET_DIS (0x0 << 15)
1252 #define RT5640_PVDD_DET_EN (0x1 << 15)
1259 #define RT5640_MIC1_BS_MASK (0x1 << 15)
1260 #define RT5640_MIC1_BS_SFT 15
1261 #define RT5640_MIC1_BS_9AV (0x0 << 15)
1262 #define RT5640_MIC1_BS_75AV (0x1 << 15)
1284 #define RT5640_MIC2_OVCD_MASK (0x1 << 8)
1285 #define RT5640_MIC2_OVCD_SFT 8
1286 #define RT5640_MIC2_OVCD_DIS (0x0 << 8)
1287 #define RT5640_MIC2_OVCD_EN (0x1 << 8)
1303 #define RT5640_EQ_SRC_MASK (0x1 << 15)
1304 #define RT5640_EQ_SRC_SFT 15
1305 #define RT5640_EQ_SRC_DAC (0x0 << 15)
1306 #define RT5640_EQ_SRC_ADC (0x1 << 15)
1313 #define RT5640_EQ_DITH_MASK (0x3 << 8)
1314 #define RT5640_EQ_DITH_SFT 8
1315 #define RT5640_EQ_DITH_NOR (0x0 << 8)
1316 #define RT5640_EQ_DITH_LSB (0x1 << 8)
1317 #define RT5640_EQ_DITH_LSB_1 (0x2 << 8)
1318 #define RT5640_EQ_DITH_LSB_2 (0x3 << 8)
1321 #define RT5640_EQ_HPF1_M_MASK (0x1 << 8)
1322 #define RT5640_EQ_HPF1_M_SFT 8
1323 #define RT5640_EQ_HPF1_M_HI (0x0 << 8)
1324 #define RT5640_EQ_HPF1_M_1ST (0x1 << 8)
1359 #define RT5640_MT_MASK (0x1 << 15)
1360 #define RT5640_MT_SFT 15
1361 #define RT5640_MT_DIS (0x0 << 15)
1362 #define RT5640_MT_EN (0x1 << 15)
1365 #define RT5640_DRC_AGC_P_MASK (0x1 << 15)
1366 #define RT5640_DRC_AGC_P_SFT 15
1367 #define RT5640_DRC_AGC_P_DAC (0x0 << 15)
1368 #define RT5640_DRC_AGC_P_ADC (0x1 << 15)
1375 #define RT5640_DRC_AGC_AR_MASK (0x1f << 8)
1376 #define RT5640_DRC_AGC_AR_SFT 8
1389 #define RT5640_DRC_AGC_POB_MASK (0x3f << 8)
1390 #define RT5640_DRC_AGC_POB_SFT 8
1421 #define RT5640_ANC_M_MASK (0x1 << 15)
1422 #define RT5640_ANC_M_SFT 15
1423 #define RT5640_ANC_M_NOR (0x0 << 15)
1424 #define RT5640_ANC_M_REV (0x1 << 15)
1443 #define RT5640_ANC_ZCD_MASK (0x3 << 8)
1444 #define RT5640_ANC_ZCD_SFT 8
1445 #define RT5640_ANC_ZCD_DIS (0x0 << 8)
1446 #define RT5640_ANC_ZCD_T1 (0x1 << 8)
1447 #define RT5640_ANC_ZCD_T2 (0x2 << 8)
1448 #define RT5640_ANC_ZCD_WT (0x3 << 8)
1463 #define RT5640_ANC_FG_L_MASK (0xf << 8)
1464 #define RT5640_ANC_FG_L_SFT 8
1500 #define RT5640_JD_SPL_TRG_MASK (0x1 << 8)
1501 #define RT5640_JD_SPL_TRG_SFT 8
1502 #define RT5640_JD_SPL_TRG_LO (0x0 << 8)
1503 #define RT5640_JD_SPL_TRG_HI (0x1 << 8)
1560 #define RT5640_IRQ_JD_MASK (0x1 << 15)
1561 #define RT5640_IRQ_JD_SFT 15
1562 #define RT5640_IRQ_JD_BP (0x0 << 15)
1563 #define RT5640_IRQ_JD_NOR (0x1 << 15)
1586 #define RT5640_IRQ_MB1_OC_MASK (0x1 << 15)
1587 #define RT5640_IRQ_MB1_OC_SFT 15
1588 #define RT5640_IRQ_MB1_OC_BP (0x0 << 15)
1589 #define RT5640_IRQ_MB1_OC_NOR (0x1 << 15)
1616 #define RT5640_GPIO1_STATUS (0x1 << 8)
1623 #define RT5640_GP1_PIN_MASK (0x1 << 15)
1624 #define RT5640_GP1_PIN_SFT 15
1625 #define RT5640_GP1_PIN_GPIO1 (0x0 << 15)
1626 #define RT5640_GP1_PIN_IRQ (0x1 << 15)
1662 #define RT5640_GP3_PF_MASK (0x1 << 8)
1663 #define RT5640_GP3_PF_SFT 8
1664 #define RT5640_GP3_PF_IN (0x0 << 8)
1665 #define RT5640_GP3_PF_OUT (0x1 << 8)
1699 /* FM34-500 Register Control 1 (0xc4) */
1702 /* FM34-500 Register Control 2 (0xc5) */
1705 /* FM34-500 Register Control 3 (0xc6) */
1706 #define RT5640_DSP_BUSY_MASK (0x1 << 15)
1707 #define RT5640_DSP_BUSY_BIT 15
1728 #define RT5640_DSP_W_EN (0x1 << 8)
1729 #define RT5640_DSP_W_EN_BIT 8
1752 #define RT5640_SEQ_2_PT_MASK (0x1 << 8)
1753 #define RT5640_SEQ_2_PT_BIT 8
1762 #define RT5640_SEQ_DLY_MASK (0xff << 8)
1763 #define RT5640_SEQ_DLY_SFT 8
1774 #define RT5640_SEQ1_START_MASK (0xf << 8)
1775 #define RT5640_SEQ1_START_SFT 8
1780 #define RT5640_SEQ2_START_MASK (0xf << 8)
1781 #define RT5640_SEQ2_START_SFT 8
1790 #define RT5640_SCB_SWAP_MASK (0x1 << 15)
1791 #define RT5640_SCB_SWAP_SFT 15
1792 #define RT5640_SCB_SWAP_DIS (0x0 << 15)
1793 #define RT5640_SCB_SWAP_EN (0x1 << 15)
1800 #define RT5640_BB_MASK (0x1 << 15)
1801 #define RT5640_BB_SFT 15
1802 #define RT5640_BB_DIS (0x0 << 15)
1803 #define RT5640_BB_EN (0x1 << 15)
1812 #define RT5640_M_BB_R_MASK (0x1 << 8)
1813 #define RT5640_M_BB_R_SFT 8
1822 #define RT5640_M_MP3_L_MASK (0x1 << 15)
1823 #define RT5640_M_MP3_L_SFT 15
1830 #define RT5640_EG_MP3_MASK (0x1f << 8)
1831 #define RT5640_EG_MP3_SFT 8
1846 #define RT5640_OG_MP3_MASK (0x1f << 8)
1847 #define RT5640_OG_MP3_SFT 8
1852 #define RT5640_3D_CF_MASK (0x1 << 15)
1853 #define RT5640_3D_CF_SFT 15
1854 #define RT5640_3D_CF_DIS (0x0 << 15)
1855 #define RT5640_3D_CF_EN (0x1 << 15)
1872 #define RT5640_M_3D_D2H_MASK (0x1 << 8)
1873 #define RT5640_M_3D_D2H_SFT 8
1880 #define RT5640_2ND_HPF_MASK (0x1 << 15)
1881 #define RT5640_2ND_HPF_SFT 15
1882 #define RT5640_2ND_HPF_DIS (0x0 << 15)
1883 #define RT5640_2ND_HPF_EN (0x1 << 15)
1890 #define RT5640_HPF_CF_R_MASK (0x7 << 8)
1891 #define RT5640_HPF_CF_R_SFT 8
1939 #define RT5640_SV_MASK (0x1 << 15)
1940 #define RT5640_SV_SFT 15
1941 #define RT5640_SV_DIS (0x0 << 15)
1942 #define RT5640_SV_EN (0x1 << 15)
1966 #define RT5640_M_ZCD_RM_R (0x1 << 8)
1975 #define RT5640_ZCD_HP_MASK (0x1 << 15)
1976 #define RT5640_ZCD_HP_SFT 15
1977 #define RT5640_ZCD_HP_DIS (0x0 << 15)
1978 #define RT5640_ZCD_HP_EN (0x1 << 15)
1998 #define RT5640_JD2_MASK (0x1 << 8)
1999 #define RT5640_JD2_SFT 8
2000 #define RT5640_JD2_DIS (0x0 << 8)
2001 #define RT5640_JD2_EN (0x1 << 8)
2006 #define RT5640_MIC_OVCD_SF_MASK (0x3 << 8)
2007 #define RT5640_MIC_OVCD_SF_SFT 8
2008 #define RT5640_MIC_OVCD_SF_0P5 (0x0 << 8)
2009 #define RT5640_MIC_OVCD_SF_0P75 (0x1 << 8)
2010 #define RT5640_MIC_OVCD_SF_1P0 (0x2 << 8)
2011 #define RT5640_MIC_OVCD_SF_1P5 (0x3 << 8)
2014 #define RT5640_3D_SPK_MASK (0x1 << 15)
2015 #define RT5640_3D_SPK_SFT 15
2016 #define RT5640_3D_SPK_DIS (0x0 << 15)
2017 #define RT5640_3D_SPK_EN (0x1 << 15)
2020 #define RT5640_3D_SPK_CG_MASK (0x1f << 8)
2021 #define RT5640_3D_SPK_CG_SFT 8
2026 #define RT5640_WND_MASK (0x1 << 15)
2027 #define RT5640_WND_SFT 15
2028 #define RT5640_WND_DIS (0x0 << 15)
2029 #define RT5640_WND_EN (0x1 << 15)
2051 /* Wind Noise Detection Control 8 (0x73) */
2052 #define RT5640_WND_WIND_MASK (0x1 << 13) /* Read-Only */
2054 #define RT5640_WND_STRONG_MASK (0x1 << 12) /* Read-Only */