Lines Matching +full:8 +full:- +full:15
1 /* SPDX-License-Identifier: GPL-2.0 */
83 #define RT5631_L_MUTE (0x1 << 15)
84 #define RT5631_L_MUTE_SHIFT 15
92 #define RT5631_L_VOL_SHIFT 8
122 #define RT5631_MIC1_DIFF_INPUT_CTRL (0x1 << 15)
123 #define RT5631_MIC1_DIFF_INPUT_SHIFT 15
131 #define RT5631_M_OUTMIXER_L_TO_RECMIXER_L (0x1 << 15)
132 #define RT5631_M_OUTMIXL_RECMIXL_BIT 15
149 #define RT5631_M_RECMIXER_L_TO_OUTMIXER_L (0x1 << 15)
150 #define RT5631_M_RECMIXL_OUTMIXL_BIT 15
163 #define RT5631_M_AXIR_TO_OUTMIXER_L (0x1 << 8)
164 #define RT5631_M_AXIR_OUTMIXL_BIT 8
169 #define RT5631_M_RECMIXER_L_TO_OUTMIXER_R (0x1 << 15)
170 #define RT5631_M_RECMIXL_OUTMIXR_BIT 15
183 #define RT5631_M_AXIR_TO_OUTMIXER_R (0x1 << 8)
184 #define RT5631_M_AXIR_OUTMIXR_BIT 8
189 #define RT5631_M_MIC1_TO_AXO1MIXER (0x1 << 15)
190 #define RT5631_M_MIC1_AXO1MIX_BIT 15
199 #define RT5631_M_MIC1_TO_AXO2MIXER (0x1 << 15)
200 #define RT5631_M_MIC1_AXO2MIX_BIT 15
224 #define RT5631_MIC2_BOOST_CTRL_MASK (0xf << 8)
225 #define RT5631_MIC2_BOOST_CTRL_BYPASS (0x0 << 8)
226 #define RT5631_MIC2_BOOST_CTRL_20DB (0x1 << 8)
227 #define RT5631_MIC2_BOOST_CTRL_24DB (0x2 << 8)
228 #define RT5631_MIC2_BOOST_CTRL_30DB (0x3 << 8)
229 #define RT5631_MIC2_BOOST_CTRL_35DB (0x4 << 8)
230 #define RT5631_MIC2_BOOST_CTRL_40DB (0x5 << 8)
231 #define RT5631_MIC2_BOOST_CTRL_34DB (0x6 << 8)
232 #define RT5631_MIC2_BOOST_CTRL_50DB (0x7 << 8)
233 #define RT5631_MIC2_BOOST_CTRL_52DB (0x8 << 8)
234 #define RT5631_MIC2_BOOST_SHIFT 8
264 #define RT5631_DMIC_ENA_MASK (0x1 << 15)
265 #define RT5631_DMIC_ENA_SHIFT 15
267 #define RT5631_DMIC_ENA (0x1 << 15)
269 #define RT5631_DMIC_DIS (0x0 << 15)
277 #define RT5631_DMIC_R_CH_LATCH_MASK (0x1 << 8)
278 #define RT5631_DMIC_R_CH_LATCH_RISING (0x1 << 8)
279 #define RT5631_DMIC_R_CH_LATCH_FALLING (0x0 << 8)
286 #define RT5631_MONO_DIFF_INPUT_SHIFT 15
289 #define RT5631_M_RECMIXER_L_TO_SPKMIXER_L (0x1 << 15)
290 #define RT5631_M_RECMIXL_SPKMIXL_BIT 15
308 #define RT5631_M_SPKVOL_L_TO_SPOL_MIXER (0x1 << 15)
309 #define RT5631_M_SPKVOLL_SPOLMIX_BIT 15
350 #define RT5631_SDP_MODE_SEL_MASK (0x1 << 15)
351 #define RT5631_SDP_MODE_SEL_MASTER (0x0 << 15)
352 #define RT5631_SDP_MODE_SEL_SLAVE (0x1 << 15)
359 #define RT5631_SDP_DAC_CPS_SEL_MASK (0x3 << 8)
360 #define RT5631_SDP_DAC_CPS_SEL_OFF (0x0 << 8)
361 #define RT5631_SDP_DAC_CPS_SEL_U_LAW (0x1 << 8)
362 #define RT5631_SDP_DAC_CPS_SEL_A_LAW (0x2 << 8)
409 #define RT5631_ADC_OSR_SEL_MASK (0x3 << 8)
410 #define RT5631_ADC_OSR_SEL_128FS (0x3 << 8)
411 #define RT5631_ADC_OSR_SEL_64FS (0x3 << 8)
412 #define RT5631_ADC_OSR_SEL_32FS (0x3 << 8)
413 #define RT5631_ADC_OSR_SEL_16FS (0x3 << 8)
419 #define RT5631_PWR_MAIN_I2S_EN (0x1 << 15)
420 #define RT5631_PWR_MAIN_I2S_BIT 15
429 #define RT5631_PWR_DAC_R_CLK (0x1 << 8)
430 #define RT5631_PWR_DAC_R_CLK_BIT 8
439 #define RT5631_PWR_OUTMIXER_L (0x1 << 15)
440 #define RT5631_PWR_OUTMIXER_L_BIT 15
465 #define RT5631_PWR_VREF (0x1 << 15)
466 #define RT5631_PWR_VREF_BIT 15
477 #define RT5631_PWR_MONO_DEPOP_DIS (0x1 << 8)
478 #define RT5631_PWR_MONO_DEPOP_DIS_BIT 8
493 #define RT5631_PWR_SPK_L_VOL (0x1 << 15)
494 #define RT5631_PWR_SPK_L_VOL_BIT 15
507 #define RT5631_PWR_AXIR_IN_VOL (0x1 << 8)
508 #define RT5631_PWR_AXIR_IN_VOL_BIT 8
515 #define RT5631_SPK_AMP_AUTO_RATIO_EN (0x1 << 15)
532 #define RT5631_ADC_WIND_FILT_8_16_32K (0x0 << 4) /*8/16/32k*/
564 #define RT5631_PLL_CTRL_N_VAL(n) (((n)&0xff) << 8)
572 #define RT5631_ADC_DATA_SEL_MIC2_SHIFT 15
577 #define RT5631_GPIO_PIN_FUN_SEL_MASK (0x1 << 15)
578 #define RT5631_GPIO_PIN_FUN_SEL_IRQ (0x1 << 15)
579 #define RT5631_GPIO_PIN_FUN_SEL_GPIO_DIMC (0x0 << 15)
589 /* De-POP function Control 1(0x54) */
590 #define RT5631_POW_ON_SOFT_GEN (0x1 << 15)
602 /* De-POP Fnction Control(0x56) */
603 #define RT5631_EN_ONE_BIT_DEPOP (0x1 << 15)
619 #define RT5631_JD_SPK_L_TRI_MASK (0x1 << 8)
620 #define RT5631_JD_SPK_L_TRI_HI (0x1 << 8)
621 #define RT5631_JD_SPK_L_TRI_LO (0x0 << 8)
644 #define RT5631_ALC_ATTACK_RATE_MASK (0x1F << 8)
657 #define RT5631_ALC_LIMIT_LEVEL_MASK (0x1F << 8)
667 #define RT5631_SPATIAL_CTRL_EN (0x1 << 15)
689 #define RT5631_HW_EQ_PATH_SEL_MASK (0x1 << 15)
690 #define RT5631_HW_EQ_PATH_SEL_DAC (0x0 << 15)
691 #define RT5631_HW_EQ_PATH_SEL_ADC (0x1 << 15)